arch/arm/mach-at91/setup.c

   1 /*
   2  * Copyright (C) 2007 Atmel Corporation.
   3  * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
   4  *
   5  * Under GPLv2
   6  */
   7
   8 #define pr_fmt(fmt)     "AT91: " fmt
   9
  10 #include <linux/module.h>
  11 #include <linux/io.h>
  12 #include <linux/mm.h>
  13 #include <linux/pm.h>
  14 #include <linux/of_address.h>
  15 #include <linux/pinctrl/machine.h>
  16 #include <linux/clk/at91_pmc.h>
  17
  18 #include <asm/system_misc.h>
  19 #include <asm/mach/map.h>
  20
  21 #include <mach/hardware.h>
  22 #include <mach/cpu.h>
  23 #include <mach/at91_dbgu.h>
  24
  25 #include "soc.h"
  26 #include "generic.h"
  27 #include "pm.h"
  28
  29 struct at91_init_soc __initdata at91_boot_soc;
  30
  31 struct at91_socinfo at91_soc_initdata;
  32 EXPORT_SYMBOL(at91_soc_initdata);
  33
  34 void __iomem *at91_ramc_base[2];
  35 EXPORT_SYMBOL_GPL(at91_ramc_base);
  36
  37 static struct map_desc at91_io_desc __initdata __maybe_unused = {
  38         .virtual        = (unsigned long)AT91_VA_BASE_SYS,
  39         .pfn            = __phys_to_pfn(AT91_BASE_SYS),
  40         .length         = SZ_16K,
  41         .type           = MT_DEVICE,
  42 };
  43
  44 static struct map_desc at91_alt_io_desc __initdata __maybe_unused = {
  45         .virtual        = (unsigned long)AT91_ALT_VA_BASE_SYS,
  46         .pfn            = __phys_to_pfn(AT91_ALT_BASE_SYS),
  47         .length         = 24 * SZ_1K,
  48         .type           = MT_DEVICE,
  49 };
  50
  51 static void __init soc_detect(u32 dbgu_base)
  52 {
  53         u32 cidr, socid;
  54
  55         cidr = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
  56         socid = cidr & ~AT91_CIDR_VERSION;
  57
  58         switch (socid) {
  59         case ARCH_ID_AT91RM9200:
  60                 at91_soc_initdata.type = AT91_SOC_RM9200;
  61                 if (at91_soc_initdata.subtype == AT91_SOC_SUBTYPE_UNKNOWN)
  62                         at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
  63                 at91_boot_soc = at91rm9200_soc;
  64                 break;
  65
  66         case ARCH_ID_AT91SAM9260:
  67                 at91_soc_initdata.type = AT91_SOC_SAM9260;
  68                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
  69                 break;
  70
  71         case ARCH_ID_AT91SAM9261:
  72                 at91_soc_initdata.type = AT91_SOC_SAM9261;
  73                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
  74                 break;
  75
  76         case ARCH_ID_AT91SAM9263:
  77                 at91_soc_initdata.type = AT91_SOC_SAM9263;
  78                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
  79                 break;
  80
  81         case ARCH_ID_AT91SAM9G20:
  82                 at91_soc_initdata.type = AT91_SOC_SAM9G20;
  83                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
  84                 break;
  85
  86         case ARCH_ID_AT91SAM9G45:
  87                 at91_soc_initdata.type = AT91_SOC_SAM9G45;
  88                 if (cidr == ARCH_ID_AT91SAM9G45ES)
  89                         at91_soc_initdata.subtype = AT91_SOC_SAM9G45ES;
  90                 break;
  91
  92         case ARCH_ID_AT91SAM9RL64:
  93                 at91_soc_initdata.type = AT91_SOC_SAM9RL;
  94                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
  95                 break;
  96
  97         case ARCH_ID_AT91SAM9X5:
  98                 at91_soc_initdata.type = AT91_SOC_SAM9X5;
  99                 break;
 100
 101         case ARCH_ID_AT91SAM9N12:
 102                 at91_soc_initdata.type = AT91_SOC_SAM9N12;
 103                 break;
 104
 105         case ARCH_ID_SAMA5:
 106                 at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
 107                 if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D3) {
 108                         at91_soc_initdata.type = AT91_SOC_SAMA5D3;
 109                         at91_boot_soc = sama5d3_soc;
 110                 }
 111                 break;
 112         }
 113
 114         /* at91sam9g10 */
 115         if ((socid & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
 116                 at91_soc_initdata.type = AT91_SOC_SAM9G10;
 117                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
 118         }
 119         /* at91sam9xe */
 120         else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
 121                 at91_soc_initdata.type = AT91_SOC_SAM9260;
 122                 at91_soc_initdata.subtype = AT91_SOC_SAM9XE;
 123         }
 124
 125         if (!at91_soc_is_detected())
 126                 return;
 127
 128         at91_soc_initdata.cidr = cidr;
 129
 130         /* sub version of soc */
 131         if (!at91_soc_initdata.exid)
 132                 at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
 133
 134         if (at91_soc_initdata.type == AT91_SOC_SAM9G45) {
 135                 switch (at91_soc_initdata.exid) {
 136                 case ARCH_EXID_AT91SAM9M10:
 137                         at91_soc_initdata.subtype = AT91_SOC_SAM9M10;
 138                         break;
 139                 case ARCH_EXID_AT91SAM9G46:
 140                         at91_soc_initdata.subtype = AT91_SOC_SAM9G46;
 141                         break;
 142                 case ARCH_EXID_AT91SAM9M11:
 143                         at91_soc_initdata.subtype = AT91_SOC_SAM9M11;
 144                         break;
 145                 }
 146         }
 147
 148         if (at91_soc_initdata.type == AT91_SOC_SAM9X5) {
 149                 switch (at91_soc_initdata.exid) {
 150                 case ARCH_EXID_AT91SAM9G15:
 151                         at91_soc_initdata.subtype = AT91_SOC_SAM9G15;
 152                         break;
 153                 case ARCH_EXID_AT91SAM9G35:
 154                         at91_soc_initdata.subtype = AT91_SOC_SAM9G35;
 155                         break;
 156                 case ARCH_EXID_AT91SAM9X35:
 157                         at91_soc_initdata.subtype = AT91_SOC_SAM9X35;
 158                         break;
 159                 case ARCH_EXID_AT91SAM9G25:
 160                         at91_soc_initdata.subtype = AT91_SOC_SAM9G25;
 161                         break;
 162                 case ARCH_EXID_AT91SAM9X25:
 163                         at91_soc_initdata.subtype = AT91_SOC_SAM9X25;
 164                         break;
 165                 }
 166         }
 167
 168         if (at91_soc_initdata.type == AT91_SOC_SAMA5D3) {
 169                 switch (at91_soc_initdata.exid) {
 170                 case ARCH_EXID_SAMA5D31:
 171                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D31;
 172                         break;
 173                 case ARCH_EXID_SAMA5D33:
 174                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D33;
 175                         break;
 176                 case ARCH_EXID_SAMA5D34:
 177                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D34;
 178                         break;
 179                 case ARCH_EXID_SAMA5D35:
 180                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D35;
 181                         break;
 182                 case ARCH_EXID_SAMA5D36:
 183                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D36;
 184                         break;
 185                 }
 186         }
 187 }
 188
 189 static void __init alt_soc_detect(u32 dbgu_base)
 190 {
 191         u32 cidr, socid;
 192
 193         /* SoC ID */
 194         cidr = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
 195         socid = cidr & ~AT91_CIDR_VERSION;
 196
 197         switch (socid) {
 198         case ARCH_ID_SAMA5:
 199                 at91_soc_initdata.exid = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
 200                 if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D3) {
 201                         at91_soc_initdata.type = AT91_SOC_SAMA5D3;
 202                         at91_boot_soc = sama5d3_soc;
 203                 } else if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D4) {
 204                         at91_soc_initdata.type = AT91_SOC_SAMA5D4;
 205                         at91_boot_soc = sama5d4_soc;
 206                 }
 207                 break;
 208         }
 209
 210         if (!at91_soc_is_detected())
 211                 return;
 212
 213         at91_soc_initdata.cidr = cidr;
 214
 215         /* sub version of soc */
 216         if (!at91_soc_initdata.exid)
 217                 at91_soc_initdata.exid = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
 218
 219         if (at91_soc_initdata.type == AT91_SOC_SAMA5D4) {
 220                 switch (at91_soc_initdata.exid) {
 221                 case ARCH_EXID_SAMA5D41:
 222                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D41;
 223                         break;
 224                 case ARCH_EXID_SAMA5D42:
 225                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D42;
 226                         break;
 227                 case ARCH_EXID_SAMA5D43:
 228                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D43;
 229                         break;
 230                 case ARCH_EXID_SAMA5D44:
 231                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D44;
 232                         break;
 233                 }
 234         }
 235 }
 236
 237 static const char *soc_name[] = {
 238         [AT91_SOC_RM9200]       = "at91rm9200",
 239         [AT91_SOC_SAM9260]      = "at91sam9260",
 240         [AT91_SOC_SAM9261]      = "at91sam9261",
 241         [AT91_SOC_SAM9263]      = "at91sam9263",
 242         [AT91_SOC_SAM9G10]      = "at91sam9g10",
 243         [AT91_SOC_SAM9G20]      = "at91sam9g20",
 244         [AT91_SOC_SAM9G45]      = "at91sam9g45",
 245         [AT91_SOC_SAM9RL]       = "at91sam9rl",
 246         [AT91_SOC_SAM9X5]       = "at91sam9x5",
 247         [AT91_SOC_SAM9N12]      = "at91sam9n12",
 248         [AT91_SOC_SAMA5D3]      = "sama5d3",
 249         [AT91_SOC_SAMA5D4]      = "sama5d4",
 250         [AT91_SOC_UNKNOWN]      = "Unknown",
 251 };
 252
 253 const char *at91_get_soc_type(struct at91_socinfo *c)
 254 {
 255         return soc_name[c->type];
 256 }
 257 EXPORT_SYMBOL(at91_get_soc_type);
 258
 259 static const char *soc_subtype_name[] = {
 260         [AT91_SOC_RM9200_BGA]   = "at91rm9200 BGA",
 261         [AT91_SOC_RM9200_PQFP]  = "at91rm9200 PQFP",
 262         [AT91_SOC_SAM9XE]       = "at91sam9xe",
 263         [AT91_SOC_SAM9G45ES]    = "at91sam9g45es",
 264         [AT91_SOC_SAM9M10]      = "at91sam9m10",
 265         [AT91_SOC_SAM9G46]      = "at91sam9g46",
 266         [AT91_SOC_SAM9M11]      = "at91sam9m11",
 267         [AT91_SOC_SAM9G15]      = "at91sam9g15",
 268         [AT91_SOC_SAM9G35]      = "at91sam9g35",
 269         [AT91_SOC_SAM9X35]      = "at91sam9x35",
 270         [AT91_SOC_SAM9G25]      = "at91sam9g25",
 271         [AT91_SOC_SAM9X25]      = "at91sam9x25",
 272         [AT91_SOC_SAMA5D31]     = "sama5d31",
 273         [AT91_SOC_SAMA5D33]     = "sama5d33",
 274         [AT91_SOC_SAMA5D34]     = "sama5d34",
 275         [AT91_SOC_SAMA5D35]     = "sama5d35",
 276         [AT91_SOC_SAMA5D36]     = "sama5d36",
 277         [AT91_SOC_SAMA5D41]     = "sama5d41",
 278         [AT91_SOC_SAMA5D42]     = "sama5d42",
 279         [AT91_SOC_SAMA5D43]     = "sama5d43",
 280         [AT91_SOC_SAMA5D44]     = "sama5d44",
 281         [AT91_SOC_SUBTYPE_NONE] = "None",
 282         [AT91_SOC_SUBTYPE_UNKNOWN] = "Unknown",
 283 };
 284
 285 const char *at91_get_soc_subtype(struct at91_socinfo *c)
 286 {
 287         return soc_subtype_name[c->subtype];
 288 }
 289 EXPORT_SYMBOL(at91_get_soc_subtype);
 290
 291 void __init at91_map_io(void)
 292 {
 293         /* Map peripherals */
 294         iotable_init(&at91_io_desc, 1);
 295
 296         at91_soc_initdata.type = AT91_SOC_UNKNOWN;
 297         at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_UNKNOWN;
 298
 299         soc_detect(AT91_BASE_DBGU0);
 300         if (!at91_soc_is_detected())
 301                 soc_detect(AT91_BASE_DBGU1);
 302
 303         if (!at91_soc_is_detected())
 304                 panic(pr_fmt("Impossible to detect the SOC type"));
 305
 306         pr_info("Detected soc type: %s\n",
 307                 at91_get_soc_type(&at91_soc_initdata));
 308         if (at91_soc_initdata.subtype != AT91_SOC_SUBTYPE_NONE)
 309                 pr_info("Detected soc subtype: %s\n",
 310                         at91_get_soc_subtype(&at91_soc_initdata));
 311 }
 312
 313 void __init at91_alt_map_io(void)
 314 {
 315         /* Map peripherals */
 316         iotable_init(&at91_alt_io_desc, 1);
 317
 318         at91_soc_initdata.type = AT91_SOC_UNKNOWN;
 319         at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_UNKNOWN;
 320
 321         alt_soc_detect(AT91_BASE_DBGU2);
 322         if (!at91_soc_is_detected())
 323                 panic("AT91: Impossible to detect the SOC type");
 324
 325         pr_info("AT91: Detected soc type: %s\n",
 326                 at91_get_soc_type(&at91_soc_initdata));
 327         if (at91_soc_initdata.subtype != AT91_SOC_SUBTYPE_NONE)
 328                 pr_info("AT91: Detected soc subtype: %s\n",
 329                         at91_get_soc_subtype(&at91_soc_initdata));
 330 }
 331
 332 void __iomem *at91_matrix_base;
 333 EXPORT_SYMBOL_GPL(at91_matrix_base);
 334
 335 void __init at91_ioremap_matrix(u32 base_addr)
 336 {
 337         at91_matrix_base = ioremap(base_addr, 512);
 338         if (!at91_matrix_base)
 339                 panic(pr_fmt("Impossible to ioremap at91_matrix_base\n"));
 340 }
 341
 342 static struct of_device_id ramc_ids[] = {
 343         { .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
 344         { .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
 345         { .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby },
 346         { .compatible = "atmel,sama5d3-ddramc", .data = at91_ddr_standby },
 347         { /*sentinel*/ }
 348 };
 349
 350 static void at91_dt_ramc(void)
 351 {
 352         struct device_node *np;
 353         const struct of_device_id *of_id;
 354         int idx = 0;
 355         const void *standby = NULL;
 356
 357         for_each_matching_node_and_match(np, ramc_ids, &of_id) {
 358                 at91_ramc_base[idx] = of_iomap(np, 0);
 359                 if (!at91_ramc_base[idx])
 360                         panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
 361
 362                 if (!standby)
 363                         standby = of_id->data;
 364
 365                 idx++;
 366         }
 367
 368         if (!idx)
 369                 panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));
 370
 371         if (!standby) {
 372                 pr_warn("ramc no standby function available\n");
 373                 return;
 374         }
 375
 376         at91_pm_set_standby(standby);
 377 }
 378
 379 void __init at91_dt_initialize(void)
 380 {
 381         at91_dt_ramc();
 382 }