arch/arm/mach-at91/setup.c

   1 /*
   2  * Copyright (C) 2007 Atmel Corporation.
   3  * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
   4  *
   5  * Under GPLv2
   6  */
   7
   8 #define pr_fmt(fmt)     "AT91: " fmt
   9
  10 #include <linux/module.h>
  11 #include <linux/io.h>
  12 #include <linux/mm.h>
  13 #include <linux/pm.h>
  14 #include <linux/of_address.h>
  15 #include <linux/pinctrl/machine.h>
  16 #include <linux/clk/at91_pmc.h>
  17
  18 #include <asm/system_misc.h>
  19 #include <asm/mach/map.h>
  20
  21 #include <mach/hardware.h>
  22 #include <mach/cpu.h>
  23 #include <mach/at91_dbgu.h>
  24
  25 #include "soc.h"
  26 #include "generic.h"
  27 #include "pm.h"
  28
  29 struct at91_init_soc __initdata at91_boot_soc;
  30
  31 struct at91_socinfo at91_soc_initdata;
  32 EXPORT_SYMBOL(at91_soc_initdata);
  33
  34 void __iomem *at91_ramc_base[2];
  35 EXPORT_SYMBOL_GPL(at91_ramc_base);
  36
  37 static struct map_desc at91_io_desc __initdata __maybe_unused = {
  38         .virtual        = (unsigned long)AT91_VA_BASE_SYS,
  39         .pfn            = __phys_to_pfn(AT91_BASE_SYS),
  40         .length         = SZ_16K,
  41         .type           = MT_DEVICE,
  42 };
  43
  44 static struct map_desc at91_alt_io_desc __initdata __maybe_unused = {
  45         .virtual        = (unsigned long)AT91_ALT_VA_BASE_SYS,
  46         .pfn            = __phys_to_pfn(AT91_ALT_BASE_SYS),
  47         .length         = 24 * SZ_1K,
  48         .type           = MT_DEVICE,
  49 };
  50
  51 static void __init soc_detect(u32 dbgu_base)
  52 {
  53         u32 cidr, socid;
  54
  55         cidr = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
  56         socid = cidr & ~AT91_CIDR_VERSION;
  57
  58         switch (socid) {
  59         case ARCH_ID_AT91RM9200:
  60                 at91_soc_initdata.type = AT91_SOC_RM9200;
  61                 if (at91_soc_initdata.subtype == AT91_SOC_SUBTYPE_UNKNOWN)
  62                         at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
  63                 at91_boot_soc = at91rm9200_soc;
  64                 break;
  65
  66         case ARCH_ID_AT91SAM9260:
  67                 at91_soc_initdata.type = AT91_SOC_SAM9260;
  68                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
  69                 at91_boot_soc = at91sam9260_soc;
  70                 break;
  71
  72         case ARCH_ID_AT91SAM9261:
  73                 at91_soc_initdata.type = AT91_SOC_SAM9261;
  74                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
  75                 at91_boot_soc = at91sam9261_soc;
  76                 break;
  77
  78         case ARCH_ID_AT91SAM9263:
  79                 at91_soc_initdata.type = AT91_SOC_SAM9263;
  80                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
  81                 at91_boot_soc = at91sam9263_soc;
  82                 break;
  83
  84         case ARCH_ID_AT91SAM9G20:
  85                 at91_soc_initdata.type = AT91_SOC_SAM9G20;
  86                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
  87                 at91_boot_soc = at91sam9260_soc;
  88                 break;
  89
  90         case ARCH_ID_AT91SAM9G45:
  91                 at91_soc_initdata.type = AT91_SOC_SAM9G45;
  92                 if (cidr == ARCH_ID_AT91SAM9G45ES)
  93                         at91_soc_initdata.subtype = AT91_SOC_SAM9G45ES;
  94                 at91_boot_soc = at91sam9g45_soc;
  95                 break;
  96
  97         case ARCH_ID_AT91SAM9RL64:
  98                 at91_soc_initdata.type = AT91_SOC_SAM9RL;
  99                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
 100                 at91_boot_soc = at91sam9rl_soc;
 101                 break;
 102
 103         case ARCH_ID_AT91SAM9X5:
 104                 at91_soc_initdata.type = AT91_SOC_SAM9X5;
 105                 at91_boot_soc = at91sam9x5_soc;
 106                 break;
 107
 108         case ARCH_ID_AT91SAM9N12:
 109                 at91_soc_initdata.type = AT91_SOC_SAM9N12;
 110                 at91_boot_soc = at91sam9n12_soc;
 111                 break;
 112
 113         case ARCH_ID_SAMA5:
 114                 at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
 115                 if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D3) {
 116                         at91_soc_initdata.type = AT91_SOC_SAMA5D3;
 117                         at91_boot_soc = sama5d3_soc;
 118                 }
 119                 break;
 120         }
 121
 122         /* at91sam9g10 */
 123         if ((socid & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
 124                 at91_soc_initdata.type = AT91_SOC_SAM9G10;
 125                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
 126                 at91_boot_soc = at91sam9261_soc;
 127         }
 128         /* at91sam9xe */
 129         else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
 130                 at91_soc_initdata.type = AT91_SOC_SAM9260;
 131                 at91_soc_initdata.subtype = AT91_SOC_SAM9XE;
 132                 at91_boot_soc = at91sam9260_soc;
 133         }
 134
 135         if (!at91_soc_is_detected())
 136                 return;
 137
 138         at91_soc_initdata.cidr = cidr;
 139
 140         /* sub version of soc */
 141         if (!at91_soc_initdata.exid)
 142                 at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
 143
 144         if (at91_soc_initdata.type == AT91_SOC_SAM9G45) {
 145                 switch (at91_soc_initdata.exid) {
 146                 case ARCH_EXID_AT91SAM9M10:
 147                         at91_soc_initdata.subtype = AT91_SOC_SAM9M10;
 148                         break;
 149                 case ARCH_EXID_AT91SAM9G46:
 150                         at91_soc_initdata.subtype = AT91_SOC_SAM9G46;
 151                         break;
 152                 case ARCH_EXID_AT91SAM9M11:
 153                         at91_soc_initdata.subtype = AT91_SOC_SAM9M11;
 154                         break;
 155                 }
 156         }
 157
 158         if (at91_soc_initdata.type == AT91_SOC_SAM9X5) {
 159                 switch (at91_soc_initdata.exid) {
 160                 case ARCH_EXID_AT91SAM9G15:
 161                         at91_soc_initdata.subtype = AT91_SOC_SAM9G15;
 162                         break;
 163                 case ARCH_EXID_AT91SAM9G35:
 164                         at91_soc_initdata.subtype = AT91_SOC_SAM9G35;
 165                         break;
 166                 case ARCH_EXID_AT91SAM9X35:
 167                         at91_soc_initdata.subtype = AT91_SOC_SAM9X35;
 168                         break;
 169                 case ARCH_EXID_AT91SAM9G25:
 170                         at91_soc_initdata.subtype = AT91_SOC_SAM9G25;
 171                         break;
 172                 case ARCH_EXID_AT91SAM9X25:
 173                         at91_soc_initdata.subtype = AT91_SOC_SAM9X25;
 174                         break;
 175                 }
 176         }
 177
 178         if (at91_soc_initdata.type == AT91_SOC_SAMA5D3) {
 179                 switch (at91_soc_initdata.exid) {
 180                 case ARCH_EXID_SAMA5D31:
 181                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D31;
 182                         break;
 183                 case ARCH_EXID_SAMA5D33:
 184                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D33;
 185                         break;
 186                 case ARCH_EXID_SAMA5D34:
 187                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D34;
 188                         break;
 189                 case ARCH_EXID_SAMA5D35:
 190                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D35;
 191                         break;
 192                 case ARCH_EXID_SAMA5D36:
 193                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D36;
 194                         break;
 195                 }
 196         }
 197 }
 198
 199 static void __init alt_soc_detect(u32 dbgu_base)
 200 {
 201         u32 cidr, socid;
 202
 203         /* SoC ID */
 204         cidr = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
 205         socid = cidr & ~AT91_CIDR_VERSION;
 206
 207         switch (socid) {
 208         case ARCH_ID_SAMA5:
 209                 at91_soc_initdata.exid = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
 210                 if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D3) {
 211                         at91_soc_initdata.type = AT91_SOC_SAMA5D3;
 212                         at91_boot_soc = sama5d3_soc;
 213                 } else if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D4) {
 214                         at91_soc_initdata.type = AT91_SOC_SAMA5D4;
 215                         at91_boot_soc = sama5d4_soc;
 216                 }
 217                 break;
 218         }
 219
 220         if (!at91_soc_is_detected())
 221                 return;
 222
 223         at91_soc_initdata.cidr = cidr;
 224
 225         /* sub version of soc */
 226         if (!at91_soc_initdata.exid)
 227                 at91_soc_initdata.exid = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
 228
 229         if (at91_soc_initdata.type == AT91_SOC_SAMA5D4) {
 230                 switch (at91_soc_initdata.exid) {
 231                 case ARCH_EXID_SAMA5D41:
 232                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D41;
 233                         break;
 234                 case ARCH_EXID_SAMA5D42:
 235                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D42;
 236                         break;
 237                 case ARCH_EXID_SAMA5D43:
 238                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D43;
 239                         break;
 240                 case ARCH_EXID_SAMA5D44:
 241                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D44;
 242                         break;
 243                 }
 244         }
 245 }
 246
 247 static const char *soc_name[] = {
 248         [AT91_SOC_RM9200]       = "at91rm9200",
 249         [AT91_SOC_SAM9260]      = "at91sam9260",
 250         [AT91_SOC_SAM9261]      = "at91sam9261",
 251         [AT91_SOC_SAM9263]      = "at91sam9263",
 252         [AT91_SOC_SAM9G10]      = "at91sam9g10",
 253         [AT91_SOC_SAM9G20]      = "at91sam9g20",
 254         [AT91_SOC_SAM9G45]      = "at91sam9g45",
 255         [AT91_SOC_SAM9RL]       = "at91sam9rl",
 256         [AT91_SOC_SAM9X5]       = "at91sam9x5",
 257         [AT91_SOC_SAM9N12]      = "at91sam9n12",
 258         [AT91_SOC_SAMA5D3]      = "sama5d3",
 259         [AT91_SOC_SAMA5D4]      = "sama5d4",
 260         [AT91_SOC_UNKNOWN]      = "Unknown",
 261 };
 262
 263 const char *at91_get_soc_type(struct at91_socinfo *c)
 264 {
 265         return soc_name[c->type];
 266 }
 267 EXPORT_SYMBOL(at91_get_soc_type);
 268
 269 static const char *soc_subtype_name[] = {
 270         [AT91_SOC_RM9200_BGA]   = "at91rm9200 BGA",
 271         [AT91_SOC_RM9200_PQFP]  = "at91rm9200 PQFP",
 272         [AT91_SOC_SAM9XE]       = "at91sam9xe",
 273         [AT91_SOC_SAM9G45ES]    = "at91sam9g45es",
 274         [AT91_SOC_SAM9M10]      = "at91sam9m10",
 275         [AT91_SOC_SAM9G46]      = "at91sam9g46",
 276         [AT91_SOC_SAM9M11]      = "at91sam9m11",
 277         [AT91_SOC_SAM9G15]      = "at91sam9g15",
 278         [AT91_SOC_SAM9G35]      = "at91sam9g35",
 279         [AT91_SOC_SAM9X35]      = "at91sam9x35",
 280         [AT91_SOC_SAM9G25]      = "at91sam9g25",
 281         [AT91_SOC_SAM9X25]      = "at91sam9x25",
 282         [AT91_SOC_SAMA5D31]     = "sama5d31",
 283         [AT91_SOC_SAMA5D33]     = "sama5d33",
 284         [AT91_SOC_SAMA5D34]     = "sama5d34",
 285         [AT91_SOC_SAMA5D35]     = "sama5d35",
 286         [AT91_SOC_SAMA5D36]     = "sama5d36",
 287         [AT91_SOC_SAMA5D41]     = "sama5d41",
 288         [AT91_SOC_SAMA5D42]     = "sama5d42",
 289         [AT91_SOC_SAMA5D43]     = "sama5d43",
 290         [AT91_SOC_SAMA5D44]     = "sama5d44",
 291         [AT91_SOC_SUBTYPE_NONE] = "None",
 292         [AT91_SOC_SUBTYPE_UNKNOWN] = "Unknown",
 293 };
 294
 295 const char *at91_get_soc_subtype(struct at91_socinfo *c)
 296 {
 297         return soc_subtype_name[c->subtype];
 298 }
 299 EXPORT_SYMBOL(at91_get_soc_subtype);
 300
 301 void __init at91_map_io(void)
 302 {
 303         /* Map peripherals */
 304         iotable_init(&at91_io_desc, 1);
 305
 306         at91_soc_initdata.type = AT91_SOC_UNKNOWN;
 307         at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_UNKNOWN;
 308
 309         soc_detect(AT91_BASE_DBGU0);
 310         if (!at91_soc_is_detected())
 311                 soc_detect(AT91_BASE_DBGU1);
 312
 313         if (!at91_soc_is_detected())
 314                 panic(pr_fmt("Impossible to detect the SOC type"));
 315
 316         pr_info("Detected soc type: %s\n",
 317                 at91_get_soc_type(&at91_soc_initdata));
 318         if (at91_soc_initdata.subtype != AT91_SOC_SUBTYPE_NONE)
 319                 pr_info("Detected soc subtype: %s\n",
 320                         at91_get_soc_subtype(&at91_soc_initdata));
 321
 322         if (!at91_soc_is_enabled())
 323                 panic(pr_fmt("Soc not enabled"));
 324
 325         if (at91_boot_soc.map_io)
 326                 at91_boot_soc.map_io();
 327 }
 328
 329 void __init at91_alt_map_io(void)
 330 {
 331         /* Map peripherals */
 332         iotable_init(&at91_alt_io_desc, 1);
 333
 334         at91_soc_initdata.type = AT91_SOC_UNKNOWN;
 335         at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_UNKNOWN;
 336
 337         alt_soc_detect(AT91_BASE_DBGU2);
 338         if (!at91_soc_is_detected())
 339                 panic("AT91: Impossible to detect the SOC type");
 340
 341         pr_info("AT91: Detected soc type: %s\n",
 342                 at91_get_soc_type(&at91_soc_initdata));
 343         if (at91_soc_initdata.subtype != AT91_SOC_SUBTYPE_NONE)
 344                 pr_info("AT91: Detected soc subtype: %s\n",
 345                         at91_get_soc_subtype(&at91_soc_initdata));
 346
 347         if (!at91_soc_is_enabled())
 348                 panic("AT91: Soc not enabled");
 349
 350         if (at91_boot_soc.map_io)
 351                 at91_boot_soc.map_io();
 352 }
 353
 354 void __iomem *at91_matrix_base;
 355 EXPORT_SYMBOL_GPL(at91_matrix_base);
 356
 357 void __init at91_ioremap_matrix(u32 base_addr)
 358 {
 359         at91_matrix_base = ioremap(base_addr, 512);
 360         if (!at91_matrix_base)
 361                 panic(pr_fmt("Impossible to ioremap at91_matrix_base\n"));
 362 }
 363
 364 static struct of_device_id ramc_ids[] = {
 365         { .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
 366         { .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
 367         { .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby },
 368         { .compatible = "atmel,sama5d3-ddramc", .data = at91_ddr_standby },
 369         { /*sentinel*/ }
 370 };
 371
 372 static void at91_dt_ramc(void)
 373 {
 374         struct device_node *np;
 375         const struct of_device_id *of_id;
 376         int idx = 0;
 377         const void *standby = NULL;
 378
 379         for_each_matching_node_and_match(np, ramc_ids, &of_id) {
 380                 at91_ramc_base[idx] = of_iomap(np, 0);
 381                 if (!at91_ramc_base[idx])
 382                         panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
 383
 384                 if (!standby)
 385                         standby = of_id->data;
 386
 387                 idx++;
 388         }
 389
 390         if (!idx)
 391                 panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));
 392
 393         if (!standby) {
 394                 pr_warn("ramc no standby function available\n");
 395                 return;
 396         }
 397
 398         at91_pm_set_standby(standby);
 399 }
 400
 401 void __init at91_dt_initialize(void)
 402 {
 403         at91_dt_ramc();
 404
 405         if (at91_boot_soc.init)
 406                 at91_boot_soc.init();
 407 }