arch/arm/mach-at91/setup.c

   1 /*
   2  * Copyright (C) 2007 Atmel Corporation.
   3  * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
   4  *
   5  * Under GPLv2
   6  */
   7
   8 #include <linux/module.h>
   9 #include <linux/io.h>
  10 #include <linux/mm.h>
  11 #include <linux/pm.h>
  12 #include <linux/of_address.h>
  13 #include <linux/pinctrl/machine.h>
  14
  15 #include <asm/system_misc.h>
  16 #include <asm/mach/map.h>
  17
  18 #include <mach/hardware.h>
  19 #include <mach/cpu.h>
  20 #include <mach/at91_dbgu.h>
  21 #include <mach/at91_pmc.h>
  22
  23 #include "at91_shdwc.h"
  24 #include "soc.h"
  25 #include "generic.h"
  26
  27 struct at91_init_soc __initdata at91_boot_soc;
  28
  29 struct at91_socinfo at91_soc_initdata;
  30 EXPORT_SYMBOL(at91_soc_initdata);
  31
  32 void __init at91rm9200_set_type(int type)
  33 {
  34         if (type == ARCH_REVISON_9200_PQFP)
  35                 at91_soc_initdata.subtype = AT91_SOC_RM9200_PQFP;
  36         else
  37                 at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
  38
  39         pr_info("AT91: filled in soc subtype: %s\n",
  40                 at91_get_soc_subtype(&at91_soc_initdata));
  41 }
  42
  43 void __init at91_init_irq_default(void)
  44 {
  45         at91_init_interrupts(at91_boot_soc.default_irq_priority);
  46 }
  47
  48 void __init at91_init_interrupts(unsigned int *priority)
  49 {
  50         /* Initialize the AIC interrupt controller */
  51         at91_aic_init(priority, at91_extern_irq);
  52
  53         /* Enable GPIO interrupts */
  54         at91_gpio_irq_setup();
  55 }
  56
  57 void __iomem *at91_ramc_base[2];
  58 EXPORT_SYMBOL_GPL(at91_ramc_base);
  59
  60 void __init at91_ioremap_ramc(int id, u32 addr, u32 size)
  61 {
  62         if (id < 0 || id > 1) {
  63                 pr_emerg("Wrong RAM controller id (%d), cannot continue\n", id);
  64                 BUG();
  65         }
  66         at91_ramc_base[id] = ioremap(addr, size);
  67         if (!at91_ramc_base[id])
  68                 panic("Impossible to ioremap ramc.%d 0x%x\n", id, addr);
  69 }
  70
  71 static struct map_desc sram_desc[2] __initdata;
  72
  73 void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
  74 {
  75         struct map_desc *desc = &sram_desc[bank];
  76
  77         desc->virtual = (unsigned long)AT91_IO_VIRT_BASE - length;
  78         if (bank > 0)
  79                 desc->virtual -= sram_desc[bank - 1].length;
  80
  81         desc->pfn = __phys_to_pfn(base);
  82         desc->length = length;
  83         desc->type = MT_DEVICE;
  84
  85         pr_info("AT91: sram at 0x%lx of 0x%x mapped at 0x%lx\n",
  86                 base, length, desc->virtual);
  87
  88         iotable_init(desc, 1);
  89 }
  90
  91 static struct map_desc at91_io_desc __initdata __maybe_unused = {
  92         .virtual        = (unsigned long)AT91_VA_BASE_SYS,
  93         .pfn            = __phys_to_pfn(AT91_BASE_SYS),
  94         .length         = SZ_16K,
  95         .type           = MT_DEVICE,
  96 };
  97
  98 static void __init soc_detect(u32 dbgu_base)
  99 {
 100         u32 cidr, socid;
 101
 102         cidr = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
 103         socid = cidr & ~AT91_CIDR_VERSION;
 104
 105         switch (socid) {
 106         case ARCH_ID_AT91RM9200:
 107                 at91_soc_initdata.type = AT91_SOC_RM9200;
 108                 at91_boot_soc = at91rm9200_soc;
 109                 break;
 110
 111         case ARCH_ID_AT91SAM9260:
 112                 at91_soc_initdata.type = AT91_SOC_SAM9260;
 113                 at91_boot_soc = at91sam9260_soc;
 114                 break;
 115
 116         case ARCH_ID_AT91SAM9261:
 117                 at91_soc_initdata.type = AT91_SOC_SAM9261;
 118                 at91_boot_soc = at91sam9261_soc;
 119                 break;
 120
 121         case ARCH_ID_AT91SAM9263:
 122                 at91_soc_initdata.type = AT91_SOC_SAM9263;
 123                 at91_boot_soc = at91sam9263_soc;
 124                 break;
 125
 126         case ARCH_ID_AT91SAM9G20:
 127                 at91_soc_initdata.type = AT91_SOC_SAM9G20;
 128                 at91_boot_soc = at91sam9260_soc;
 129                 break;
 130
 131         case ARCH_ID_AT91SAM9G45:
 132                 at91_soc_initdata.type = AT91_SOC_SAM9G45;
 133                 if (cidr == ARCH_ID_AT91SAM9G45ES)
 134                         at91_soc_initdata.subtype = AT91_SOC_SAM9G45ES;
 135                 at91_boot_soc = at91sam9g45_soc;
 136                 break;
 137
 138         case ARCH_ID_AT91SAM9RL64:
 139                 at91_soc_initdata.type = AT91_SOC_SAM9RL;
 140                 at91_boot_soc = at91sam9rl_soc;
 141                 break;
 142
 143         case ARCH_ID_AT91SAM9X5:
 144                 at91_soc_initdata.type = AT91_SOC_SAM9X5;
 145                 at91_boot_soc = at91sam9x5_soc;
 146                 break;
 147
 148         case ARCH_ID_AT91SAM9N12:
 149                 at91_soc_initdata.type = AT91_SOC_SAM9N12;
 150                 at91_boot_soc = at91sam9n12_soc;
 151                 break;
 152         }
 153
 154         /* at91sam9g10 */
 155         if ((socid & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
 156                 at91_soc_initdata.type = AT91_SOC_SAM9G10;
 157                 at91_boot_soc = at91sam9261_soc;
 158         }
 159         /* at91sam9xe */
 160         else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
 161                 at91_soc_initdata.type = AT91_SOC_SAM9260;
 162                 at91_soc_initdata.subtype = AT91_SOC_SAM9XE;
 163                 at91_boot_soc = at91sam9260_soc;
 164         }
 165
 166         if (!at91_soc_is_detected())
 167                 return;
 168
 169         at91_soc_initdata.cidr = cidr;
 170
 171         /* sub version of soc */
 172         at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
 173
 174         if (at91_soc_initdata.type == AT91_SOC_SAM9G45) {
 175                 switch (at91_soc_initdata.exid) {
 176                 case ARCH_EXID_AT91SAM9M10:
 177                         at91_soc_initdata.subtype = AT91_SOC_SAM9M10;
 178                         break;
 179                 case ARCH_EXID_AT91SAM9G46:
 180                         at91_soc_initdata.subtype = AT91_SOC_SAM9G46;
 181                         break;
 182                 case ARCH_EXID_AT91SAM9M11:
 183                         at91_soc_initdata.subtype = AT91_SOC_SAM9M11;
 184                         break;
 185                 }
 186         }
 187
 188         if (at91_soc_initdata.type == AT91_SOC_SAM9X5) {
 189                 switch (at91_soc_initdata.exid) {
 190                 case ARCH_EXID_AT91SAM9G15:
 191                         at91_soc_initdata.subtype = AT91_SOC_SAM9G15;
 192                         break;
 193                 case ARCH_EXID_AT91SAM9G35:
 194                         at91_soc_initdata.subtype = AT91_SOC_SAM9G35;
 195                         break;
 196                 case ARCH_EXID_AT91SAM9X35:
 197                         at91_soc_initdata.subtype = AT91_SOC_SAM9X35;
 198                         break;
 199                 case ARCH_EXID_AT91SAM9G25:
 200                         at91_soc_initdata.subtype = AT91_SOC_SAM9G25;
 201                         break;
 202                 case ARCH_EXID_AT91SAM9X25:
 203                         at91_soc_initdata.subtype = AT91_SOC_SAM9X25;
 204                         break;
 205                 }
 206         }
 207 }
 208
 209 static const char *soc_name[] = {
 210         [AT91_SOC_RM9200]       = "at91rm9200",
 211         [AT91_SOC_SAM9260]      = "at91sam9260",
 212         [AT91_SOC_SAM9261]      = "at91sam9261",
 213         [AT91_SOC_SAM9263]      = "at91sam9263",
 214         [AT91_SOC_SAM9G10]      = "at91sam9g10",
 215         [AT91_SOC_SAM9G20]      = "at91sam9g20",
 216         [AT91_SOC_SAM9G45]      = "at91sam9g45",
 217         [AT91_SOC_SAM9RL]       = "at91sam9rl",
 218         [AT91_SOC_SAM9X5]       = "at91sam9x5",
 219         [AT91_SOC_SAM9N12]      = "at91sam9n12",
 220         [AT91_SOC_NONE]         = "Unknown"
 221 };
 222
 223 const char *at91_get_soc_type(struct at91_socinfo *c)
 224 {
 225         return soc_name[c->type];
 226 }
 227 EXPORT_SYMBOL(at91_get_soc_type);
 228
 229 static const char *soc_subtype_name[] = {
 230         [AT91_SOC_RM9200_BGA]   = "at91rm9200 BGA",
 231         [AT91_SOC_RM9200_PQFP]  = "at91rm9200 PQFP",
 232         [AT91_SOC_SAM9XE]       = "at91sam9xe",
 233         [AT91_SOC_SAM9G45ES]    = "at91sam9g45es",
 234         [AT91_SOC_SAM9M10]      = "at91sam9m10",
 235         [AT91_SOC_SAM9G46]      = "at91sam9g46",
 236         [AT91_SOC_SAM9M11]      = "at91sam9m11",
 237         [AT91_SOC_SAM9G15]      = "at91sam9g15",
 238         [AT91_SOC_SAM9G35]      = "at91sam9g35",
 239         [AT91_SOC_SAM9X35]      = "at91sam9x35",
 240         [AT91_SOC_SAM9G25]      = "at91sam9g25",
 241         [AT91_SOC_SAM9X25]      = "at91sam9x25",
 242         [AT91_SOC_SUBTYPE_NONE] = "Unknown"
 243 };
 244
 245 const char *at91_get_soc_subtype(struct at91_socinfo *c)
 246 {
 247         return soc_subtype_name[c->subtype];
 248 }
 249 EXPORT_SYMBOL(at91_get_soc_subtype);
 250
 251 void __init at91_map_io(void)
 252 {
 253         /* Map peripherals */
 254         iotable_init(&at91_io_desc, 1);
 255
 256         at91_soc_initdata.type = AT91_SOC_NONE;
 257         at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
 258
 259         soc_detect(AT91_BASE_DBGU0);
 260         if (!at91_soc_is_detected())
 261                 soc_detect(AT91_BASE_DBGU1);
 262
 263         if (!at91_soc_is_detected())
 264                 panic("AT91: Impossible to detect the SOC type");
 265
 266         pr_info("AT91: Detected soc type: %s\n",
 267                 at91_get_soc_type(&at91_soc_initdata));
 268         pr_info("AT91: Detected soc subtype: %s\n",
 269                 at91_get_soc_subtype(&at91_soc_initdata));
 270
 271         if (!at91_soc_is_enabled())
 272                 panic("AT91: Soc not enabled");
 273
 274         if (at91_boot_soc.map_io)
 275                 at91_boot_soc.map_io();
 276 }
 277
 278 void __iomem *at91_shdwc_base = NULL;
 279
 280 static void at91sam9_poweroff(void)
 281 {
 282         at91_shdwc_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
 283 }
 284
 285 void __init at91_ioremap_shdwc(u32 base_addr)
 286 {
 287         at91_shdwc_base = ioremap(base_addr, 16);
 288         if (!at91_shdwc_base)
 289                 panic("Impossible to ioremap at91_shdwc_base\n");
 290         pm_power_off = at91sam9_poweroff;
 291 }
 292
 293 void __iomem *at91_rstc_base;
 294
 295 void __init at91_ioremap_rstc(u32 base_addr)
 296 {
 297         at91_rstc_base = ioremap(base_addr, 16);
 298         if (!at91_rstc_base)
 299                 panic("Impossible to ioremap at91_rstc_base\n");
 300 }
 301
 302 void __iomem *at91_matrix_base;
 303 EXPORT_SYMBOL_GPL(at91_matrix_base);
 304
 305 void __init at91_ioremap_matrix(u32 base_addr)
 306 {
 307         at91_matrix_base = ioremap(base_addr, 512);
 308         if (!at91_matrix_base)
 309                 panic("Impossible to ioremap at91_matrix_base\n");
 310 }
 311
 312 #if defined(CONFIG_OF)
 313 static struct of_device_id rstc_ids[] = {
 314         { .compatible = "atmel,at91sam9260-rstc", .data = at91sam9_alt_restart },
 315         { .compatible = "atmel,at91sam9g45-rstc", .data = at91sam9g45_restart },
 316         { /*sentinel*/ }
 317 };
 318
 319 static void at91_dt_rstc(void)
 320 {
 321         struct device_node *np;
 322         const struct of_device_id *of_id;
 323
 324         np = of_find_matching_node(NULL, rstc_ids);
 325         if (!np)
 326                 panic("unable to find compatible rstc node in dtb\n");
 327
 328         at91_rstc_base = of_iomap(np, 0);
 329         if (!at91_rstc_base)
 330                 panic("unable to map rstc cpu registers\n");
 331
 332         of_id = of_match_node(rstc_ids, np);
 333         if (!of_id)
 334                 panic("AT91: rtsc no restart function availlable\n");
 335
 336         arm_pm_restart = of_id->data;
 337
 338         of_node_put(np);
 339 }
 340
 341 static struct of_device_id ramc_ids[] = {
 342         { .compatible = "atmel,at91rm9200-sdramc" },
 343         { .compatible = "atmel,at91sam9260-sdramc" },
 344         { .compatible = "atmel,at91sam9g45-ddramc" },
 345         { /*sentinel*/ }
 346 };
 347
 348 static void at91_dt_ramc(void)
 349 {
 350         struct device_node *np;
 351
 352         np = of_find_matching_node(NULL, ramc_ids);
 353         if (!np)
 354                 panic("unable to find compatible ram conroller node in dtb\n");
 355
 356         at91_ramc_base[0] = of_iomap(np, 0);
 357         if (!at91_ramc_base[0])
 358                 panic("unable to map ramc[0] cpu registers\n");
 359         /* the controller may have 2 banks */
 360         at91_ramc_base[1] = of_iomap(np, 1);
 361
 362         of_node_put(np);
 363 }
 364
 365 static struct of_device_id shdwc_ids[] = {
 366         { .compatible = "atmel,at91sam9260-shdwc", },
 367         { .compatible = "atmel,at91sam9rl-shdwc", },
 368         { .compatible = "atmel,at91sam9x5-shdwc", },
 369         { /*sentinel*/ }
 370 };
 371
 372 static const char *shdwc_wakeup_modes[] = {
 373         [AT91_SHDW_WKMODE0_NONE]        = "none",
 374         [AT91_SHDW_WKMODE0_HIGH]        = "high",
 375         [AT91_SHDW_WKMODE0_LOW]         = "low",
 376         [AT91_SHDW_WKMODE0_ANYLEVEL]    = "any",
 377 };
 378
 379 const int at91_dtget_shdwc_wakeup_mode(struct device_node *np)
 380 {
 381         const char *pm;
 382         int err, i;
 383
 384         err = of_property_read_string(np, "atmel,wakeup-mode", &pm);
 385         if (err < 0)
 386                 return AT91_SHDW_WKMODE0_ANYLEVEL;
 387
 388         for (i = 0; i < ARRAY_SIZE(shdwc_wakeup_modes); i++)
 389                 if (!strcasecmp(pm, shdwc_wakeup_modes[i]))
 390                         return i;
 391
 392         return -ENODEV;
 393 }
 394
 395 static void at91_dt_shdwc(void)
 396 {
 397         struct device_node *np;
 398         int wakeup_mode;
 399         u32 reg;
 400         u32 mode = 0;
 401
 402         np = of_find_matching_node(NULL, shdwc_ids);
 403         if (!np) {
 404                 pr_debug("AT91: unable to find compatible shutdown (shdwc) conroller node in dtb\n");
 405                 return;
 406         }
 407
 408         at91_shdwc_base = of_iomap(np, 0);
 409         if (!at91_shdwc_base)
 410                 panic("AT91: unable to map shdwc cpu registers\n");
 411
 412         wakeup_mode = at91_dtget_shdwc_wakeup_mode(np);
 413         if (wakeup_mode < 0) {
 414                 pr_warn("AT91: shdwc unknown wakeup mode\n");
 415                 goto end;
 416         }
 417
 418         if (!of_property_read_u32(np, "atmel,wakeup-counter", &reg)) {
 419                 if (reg > AT91_SHDW_CPTWK0_MAX) {
 420                         pr_warn("AT91: shdwc wakeup conter 0x%x > 0x%x reduce it to 0x%x\n",
 421                                 reg, AT91_SHDW_CPTWK0_MAX, AT91_SHDW_CPTWK0_MAX);
 422                         reg = AT91_SHDW_CPTWK0_MAX;
 423                 }
 424                 mode |= AT91_SHDW_CPTWK0_(reg);
 425         }
 426
 427         if (of_property_read_bool(np, "atmel,wakeup-rtc-timer"))
 428                         mode |= AT91_SHDW_RTCWKEN;
 429
 430         if (of_property_read_bool(np, "atmel,wakeup-rtt-timer"))
 431                         mode |= AT91_SHDW_RTTWKEN;
 432
 433         at91_shdwc_write(AT91_SHDW_MR, wakeup_mode | mode);
 434
 435 end:
 436         pm_power_off = at91sam9_poweroff;
 437
 438         of_node_put(np);
 439 }
 440
 441 void __init at91rm9200_dt_initialize(void)
 442 {
 443         at91_dt_ramc();
 444
 445         /* Init clock subsystem */
 446         at91_dt_clock_init();
 447
 448         /* Register the processor-specific clocks */
 449         at91_boot_soc.register_clocks();
 450
 451         at91_boot_soc.init();
 452 }
 453
 454 void __init at91_dt_initialize(void)
 455 {
 456         at91_dt_rstc();
 457         at91_dt_ramc();
 458         at91_dt_shdwc();
 459
 460         /* Init clock subsystem */
 461         at91_dt_clock_init();
 462
 463         /* Register the processor-specific clocks */
 464         at91_boot_soc.register_clocks();
 465
 466         if (at91_boot_soc.init)
 467                 at91_boot_soc.init();
 468 }
 469 #endif
 470
 471 void __init at91_initialize(unsigned long main_clock)
 472 {
 473         at91_boot_soc.ioremap_registers();
 474
 475         /* Init clock subsystem */
 476         at91_clock_init(main_clock);
 477
 478         /* Register the processor-specific clocks */
 479         at91_boot_soc.register_clocks();
 480
 481         at91_boot_soc.init();
 482
 483         pinctrl_provide_dummies();
 484 }