2 * On-Chip devices setup code for the AT91SAM9G45 family
4 * Copyright (C) 2009 Atmel Corporation.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #include <asm/mach/arch.h>
13 #include <asm/mach/map.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/gpio.h>
17 #include <linux/clk.h>
18 #include <linux/platform_device.h>
19 #include <linux/i2c-gpio.h>
20 #include <linux/atmel-mci.h>
23 #include <video/atmel_lcdc.h>
25 #include <mach/board.h>
26 #include <mach/at91sam9g45.h>
27 #include <mach/at91sam9g45_matrix.h>
28 #include <mach/at91_matrix.h>
29 #include <mach/at91sam9_smc.h>
30 #include <mach/at_hdmac.h>
31 #include <mach/atmel-mci.h>
33 #include <media/atmel-isi.h>
39 /* --------------------------------------------------------------------
40 * HDMAC - AHB DMA Controller
41 * -------------------------------------------------------------------- */
43 #if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
44 static u64 hdmac_dmamask = DMA_BIT_MASK(32);
46 static struct resource hdmac_resources[] = {
48 .start = AT91SAM9G45_BASE_DMA,
49 .end = AT91SAM9G45_BASE_DMA + SZ_512 - 1,
50 .flags = IORESOURCE_MEM,
53 .start = AT91SAM9G45_ID_DMA,
54 .end = AT91SAM9G45_ID_DMA,
55 .flags = IORESOURCE_IRQ,
59 static struct platform_device at_hdmac_device = {
60 .name = "at91sam9g45_dma",
63 .dma_mask = &hdmac_dmamask,
64 .coherent_dma_mask = DMA_BIT_MASK(32),
66 .resource = hdmac_resources,
67 .num_resources = ARRAY_SIZE(hdmac_resources),
70 void __init at91_add_device_hdmac(void)
72 #if defined(CONFIG_OF)
73 struct device_node *of_node =
74 of_find_node_by_name(NULL, "dma-controller");
80 platform_device_register(&at_hdmac_device);
83 void __init at91_add_device_hdmac(void) {}
87 /* --------------------------------------------------------------------
89 * -------------------------------------------------------------------- */
91 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
92 static u64 ohci_dmamask = DMA_BIT_MASK(32);
93 static struct at91_usbh_data usbh_ohci_data;
95 static struct resource usbh_ohci_resources[] = {
97 .start = AT91SAM9G45_OHCI_BASE,
98 .end = AT91SAM9G45_OHCI_BASE + SZ_1M - 1,
99 .flags = IORESOURCE_MEM,
102 .start = AT91SAM9G45_ID_UHPHS,
103 .end = AT91SAM9G45_ID_UHPHS,
104 .flags = IORESOURCE_IRQ,
108 static struct platform_device at91_usbh_ohci_device = {
112 .dma_mask = &ohci_dmamask,
113 .coherent_dma_mask = DMA_BIT_MASK(32),
114 .platform_data = &usbh_ohci_data,
116 .resource = usbh_ohci_resources,
117 .num_resources = ARRAY_SIZE(usbh_ohci_resources),
120 void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
127 /* Enable VBus control for UHP ports */
128 for (i = 0; i < data->ports; i++) {
129 if (gpio_is_valid(data->vbus_pin[i]))
130 at91_set_gpio_output(data->vbus_pin[i],
131 data->vbus_pin_active_low[i]);
134 /* Enable overcurrent notification */
135 for (i = 0; i < data->ports; i++) {
136 if (gpio_is_valid(data->overcurrent_pin[i]))
137 at91_set_gpio_input(data->overcurrent_pin[i], 1);
140 usbh_ohci_data = *data;
141 platform_device_register(&at91_usbh_ohci_device);
144 void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {}
148 /* --------------------------------------------------------------------
150 * Needs an OHCI host for low and full speed management
151 * -------------------------------------------------------------------- */
153 #if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE)
154 static u64 ehci_dmamask = DMA_BIT_MASK(32);
155 static struct at91_usbh_data usbh_ehci_data;
157 static struct resource usbh_ehci_resources[] = {
159 .start = AT91SAM9G45_EHCI_BASE,
160 .end = AT91SAM9G45_EHCI_BASE + SZ_1M - 1,
161 .flags = IORESOURCE_MEM,
164 .start = AT91SAM9G45_ID_UHPHS,
165 .end = AT91SAM9G45_ID_UHPHS,
166 .flags = IORESOURCE_IRQ,
170 static struct platform_device at91_usbh_ehci_device = {
171 .name = "atmel-ehci",
174 .dma_mask = &ehci_dmamask,
175 .coherent_dma_mask = DMA_BIT_MASK(32),
176 .platform_data = &usbh_ehci_data,
178 .resource = usbh_ehci_resources,
179 .num_resources = ARRAY_SIZE(usbh_ehci_resources),
182 void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data)
189 /* Enable VBus control for UHP ports */
190 for (i = 0; i < data->ports; i++) {
191 if (gpio_is_valid(data->vbus_pin[i]))
192 at91_set_gpio_output(data->vbus_pin[i],
193 data->vbus_pin_active_low[i]);
196 usbh_ehci_data = *data;
197 platform_device_register(&at91_usbh_ehci_device);
200 void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data) {}
204 /* --------------------------------------------------------------------
205 * USB HS Device (Gadget)
206 * -------------------------------------------------------------------- */
208 #if defined(CONFIG_USB_ATMEL_USBA) || defined(CONFIG_USB_ATMEL_USBA_MODULE)
209 static struct resource usba_udc_resources[] = {
211 .start = AT91SAM9G45_UDPHS_FIFO,
212 .end = AT91SAM9G45_UDPHS_FIFO + SZ_512K - 1,
213 .flags = IORESOURCE_MEM,
216 .start = AT91SAM9G45_BASE_UDPHS,
217 .end = AT91SAM9G45_BASE_UDPHS + SZ_1K - 1,
218 .flags = IORESOURCE_MEM,
221 .start = AT91SAM9G45_ID_UDPHS,
222 .end = AT91SAM9G45_ID_UDPHS,
223 .flags = IORESOURCE_IRQ,
227 #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
231 .fifo_size = maxpkt, \
237 static struct usba_ep_data usba_udc_ep[] __initdata = {
238 EP("ep0", 0, 64, 1, 0, 0),
239 EP("ep1", 1, 1024, 2, 1, 1),
240 EP("ep2", 2, 1024, 2, 1, 1),
241 EP("ep3", 3, 1024, 3, 1, 0),
242 EP("ep4", 4, 1024, 3, 1, 0),
243 EP("ep5", 5, 1024, 3, 1, 1),
244 EP("ep6", 6, 1024, 3, 1, 1),
250 * pdata doesn't have room for any endpoints, so we need to
251 * append room for the ones we need right after it.
254 struct usba_platform_data pdata;
255 struct usba_ep_data ep[7];
258 static struct platform_device at91_usba_udc_device = {
259 .name = "atmel_usba_udc",
262 .platform_data = &usba_udc_data.pdata,
264 .resource = usba_udc_resources,
265 .num_resources = ARRAY_SIZE(usba_udc_resources),
268 void __init at91_add_device_usba(struct usba_platform_data *data)
270 usba_udc_data.pdata.vbus_pin = -EINVAL;
271 usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
272 memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));
274 if (data && gpio_is_valid(data->vbus_pin)) {
275 at91_set_gpio_input(data->vbus_pin, 0);
276 at91_set_deglitch(data->vbus_pin, 1);
277 usba_udc_data.pdata.vbus_pin = data->vbus_pin;
280 /* Pullup pin is handled internally by USB device peripheral */
282 platform_device_register(&at91_usba_udc_device);
285 void __init at91_add_device_usba(struct usba_platform_data *data) {}
289 /* --------------------------------------------------------------------
291 * -------------------------------------------------------------------- */
293 #if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
294 static u64 eth_dmamask = DMA_BIT_MASK(32);
295 static struct macb_platform_data eth_data;
297 static struct resource eth_resources[] = {
299 .start = AT91SAM9G45_BASE_EMAC,
300 .end = AT91SAM9G45_BASE_EMAC + SZ_16K - 1,
301 .flags = IORESOURCE_MEM,
304 .start = AT91SAM9G45_ID_EMAC,
305 .end = AT91SAM9G45_ID_EMAC,
306 .flags = IORESOURCE_IRQ,
310 static struct platform_device at91sam9g45_eth_device = {
314 .dma_mask = ð_dmamask,
315 .coherent_dma_mask = DMA_BIT_MASK(32),
316 .platform_data = ð_data,
318 .resource = eth_resources,
319 .num_resources = ARRAY_SIZE(eth_resources),
322 void __init at91_add_device_eth(struct macb_platform_data *data)
327 if (gpio_is_valid(data->phy_irq_pin)) {
328 at91_set_gpio_input(data->phy_irq_pin, 0);
329 at91_set_deglitch(data->phy_irq_pin, 1);
332 /* Pins used for MII and RMII */
333 at91_set_A_periph(AT91_PIN_PA17, 0); /* ETXCK_EREFCK */
334 at91_set_A_periph(AT91_PIN_PA15, 0); /* ERXDV */
335 at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */
336 at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */
337 at91_set_A_periph(AT91_PIN_PA16, 0); /* ERXER */
338 at91_set_A_periph(AT91_PIN_PA14, 0); /* ETXEN */
339 at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX0 */
340 at91_set_A_periph(AT91_PIN_PA11, 0); /* ETX1 */
341 at91_set_A_periph(AT91_PIN_PA19, 0); /* EMDIO */
342 at91_set_A_periph(AT91_PIN_PA18, 0); /* EMDC */
344 if (!data->is_rmii) {
345 at91_set_B_periph(AT91_PIN_PA29, 0); /* ECRS */
346 at91_set_B_periph(AT91_PIN_PA30, 0); /* ECOL */
347 at91_set_B_periph(AT91_PIN_PA8, 0); /* ERX2 */
348 at91_set_B_periph(AT91_PIN_PA9, 0); /* ERX3 */
349 at91_set_B_periph(AT91_PIN_PA28, 0); /* ERXCK */
350 at91_set_B_periph(AT91_PIN_PA6, 0); /* ETX2 */
351 at91_set_B_periph(AT91_PIN_PA7, 0); /* ETX3 */
352 at91_set_B_periph(AT91_PIN_PA27, 0); /* ETXER */
356 platform_device_register(&at91sam9g45_eth_device);
359 void __init at91_add_device_eth(struct macb_platform_data *data) {}
363 /* --------------------------------------------------------------------
365 * -------------------------------------------------------------------- */
367 #if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
368 static u64 mmc_dmamask = DMA_BIT_MASK(32);
369 static struct mci_platform_data mmc0_data, mmc1_data;
371 static struct resource mmc0_resources[] = {
373 .start = AT91SAM9G45_BASE_MCI0,
374 .end = AT91SAM9G45_BASE_MCI0 + SZ_16K - 1,
375 .flags = IORESOURCE_MEM,
378 .start = AT91SAM9G45_ID_MCI0,
379 .end = AT91SAM9G45_ID_MCI0,
380 .flags = IORESOURCE_IRQ,
384 static struct platform_device at91sam9g45_mmc0_device = {
388 .dma_mask = &mmc_dmamask,
389 .coherent_dma_mask = DMA_BIT_MASK(32),
390 .platform_data = &mmc0_data,
392 .resource = mmc0_resources,
393 .num_resources = ARRAY_SIZE(mmc0_resources),
396 static struct resource mmc1_resources[] = {
398 .start = AT91SAM9G45_BASE_MCI1,
399 .end = AT91SAM9G45_BASE_MCI1 + SZ_16K - 1,
400 .flags = IORESOURCE_MEM,
403 .start = AT91SAM9G45_ID_MCI1,
404 .end = AT91SAM9G45_ID_MCI1,
405 .flags = IORESOURCE_IRQ,
409 static struct platform_device at91sam9g45_mmc1_device = {
413 .dma_mask = &mmc_dmamask,
414 .coherent_dma_mask = DMA_BIT_MASK(32),
415 .platform_data = &mmc1_data,
417 .resource = mmc1_resources,
418 .num_resources = ARRAY_SIZE(mmc1_resources),
421 /* Consider only one slot : slot 0 */
422 void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
428 /* Must have at least one usable slot */
429 if (!data->slot[0].bus_width)
432 #if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
434 struct at_dma_slave *atslave;
435 struct mci_dma_data *alt_atslave;
437 alt_atslave = kzalloc(sizeof(struct mci_dma_data), GFP_KERNEL);
438 atslave = &alt_atslave->sdata;
440 /* DMA slave channel configuration */
441 atslave->dma_dev = &at_hdmac_device.dev;
442 atslave->cfg = ATC_FIFOCFG_HALFFIFO
443 | ATC_SRC_H2SEL_HW | ATC_DST_H2SEL_HW;
444 atslave->ctrla = ATC_SCSIZE_16 | ATC_DCSIZE_16;
445 if (mmc_id == 0) /* MCI0 */
446 atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI0)
447 | ATC_DST_PER(AT_DMA_ID_MCI0);
450 atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI1)
451 | ATC_DST_PER(AT_DMA_ID_MCI1);
453 data->dma_slave = alt_atslave;
459 if (gpio_is_valid(data->slot[0].detect_pin)) {
460 at91_set_gpio_input(data->slot[0].detect_pin, 1);
461 at91_set_deglitch(data->slot[0].detect_pin, 1);
463 if (gpio_is_valid(data->slot[0].wp_pin))
464 at91_set_gpio_input(data->slot[0].wp_pin, 1);
466 if (mmc_id == 0) { /* MCI0 */
469 at91_set_A_periph(AT91_PIN_PA0, 0);
472 at91_set_A_periph(AT91_PIN_PA1, 1);
474 /* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */
475 at91_set_A_periph(AT91_PIN_PA2, 1);
476 if (data->slot[0].bus_width == 4) {
477 at91_set_A_periph(AT91_PIN_PA3, 1);
478 at91_set_A_periph(AT91_PIN_PA4, 1);
479 at91_set_A_periph(AT91_PIN_PA5, 1);
480 if (data->slot[0].bus_width == 8) {
481 at91_set_A_periph(AT91_PIN_PA6, 1);
482 at91_set_A_periph(AT91_PIN_PA7, 1);
483 at91_set_A_periph(AT91_PIN_PA8, 1);
484 at91_set_A_periph(AT91_PIN_PA9, 1);
489 platform_device_register(&at91sam9g45_mmc0_device);
494 at91_set_A_periph(AT91_PIN_PA31, 0);
497 at91_set_A_periph(AT91_PIN_PA22, 1);
499 /* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */
500 at91_set_A_periph(AT91_PIN_PA23, 1);
501 if (data->slot[0].bus_width == 4) {
502 at91_set_A_periph(AT91_PIN_PA24, 1);
503 at91_set_A_periph(AT91_PIN_PA25, 1);
504 at91_set_A_periph(AT91_PIN_PA26, 1);
505 if (data->slot[0].bus_width == 8) {
506 at91_set_A_periph(AT91_PIN_PA27, 1);
507 at91_set_A_periph(AT91_PIN_PA28, 1);
508 at91_set_A_periph(AT91_PIN_PA29, 1);
509 at91_set_A_periph(AT91_PIN_PA30, 1);
514 platform_device_register(&at91sam9g45_mmc1_device);
519 void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
523 /* --------------------------------------------------------------------
525 * -------------------------------------------------------------------- */
527 #if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
528 static struct atmel_nand_data nand_data;
530 #define NAND_BASE AT91_CHIPSELECT_3
532 static struct resource nand_resources[] = {
535 .end = NAND_BASE + SZ_256M - 1,
536 .flags = IORESOURCE_MEM,
539 .start = AT91SAM9G45_BASE_ECC,
540 .end = AT91SAM9G45_BASE_ECC + SZ_512 - 1,
541 .flags = IORESOURCE_MEM,
545 static struct platform_device at91sam9g45_nand_device = {
546 .name = "atmel_nand",
549 .platform_data = &nand_data,
551 .resource = nand_resources,
552 .num_resources = ARRAY_SIZE(nand_resources),
555 void __init at91_add_device_nand(struct atmel_nand_data *data)
562 csa = at91_matrix_read(AT91_MATRIX_EBICSA);
563 at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
566 if (gpio_is_valid(data->enable_pin))
567 at91_set_gpio_output(data->enable_pin, 1);
570 if (gpio_is_valid(data->rdy_pin))
571 at91_set_gpio_input(data->rdy_pin, 1);
573 /* card detect pin */
574 if (gpio_is_valid(data->det_pin))
575 at91_set_gpio_input(data->det_pin, 1);
578 platform_device_register(&at91sam9g45_nand_device);
581 void __init at91_add_device_nand(struct atmel_nand_data *data) {}
585 /* --------------------------------------------------------------------
587 * -------------------------------------------------------------------- */
590 * Prefer the GPIO code since the TWI controller isn't robust
591 * (gets overruns and underruns under load) and can only issue
592 * repeated STARTs in one scenario (the driver doesn't yet handle them).
594 #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
595 static struct i2c_gpio_platform_data pdata_i2c0 = {
596 .sda_pin = AT91_PIN_PA20,
597 .sda_is_open_drain = 1,
598 .scl_pin = AT91_PIN_PA21,
599 .scl_is_open_drain = 1,
600 .udelay = 5, /* ~100 kHz */
603 static struct platform_device at91sam9g45_twi0_device = {
606 .dev.platform_data = &pdata_i2c0,
609 static struct i2c_gpio_platform_data pdata_i2c1 = {
610 .sda_pin = AT91_PIN_PB10,
611 .sda_is_open_drain = 1,
612 .scl_pin = AT91_PIN_PB11,
613 .scl_is_open_drain = 1,
614 .udelay = 5, /* ~100 kHz */
617 static struct platform_device at91sam9g45_twi1_device = {
620 .dev.platform_data = &pdata_i2c1,
623 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
625 i2c_register_board_info(i2c_id, devices, nr_devices);
628 at91_set_GPIO_periph(AT91_PIN_PA20, 1); /* TWD (SDA) */
629 at91_set_multi_drive(AT91_PIN_PA20, 1);
631 at91_set_GPIO_periph(AT91_PIN_PA21, 1); /* TWCK (SCL) */
632 at91_set_multi_drive(AT91_PIN_PA21, 1);
634 platform_device_register(&at91sam9g45_twi0_device);
636 at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* TWD (SDA) */
637 at91_set_multi_drive(AT91_PIN_PB10, 1);
639 at91_set_GPIO_periph(AT91_PIN_PB11, 1); /* TWCK (SCL) */
640 at91_set_multi_drive(AT91_PIN_PB11, 1);
642 platform_device_register(&at91sam9g45_twi1_device);
646 #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
647 static struct resource twi0_resources[] = {
649 .start = AT91SAM9G45_BASE_TWI0,
650 .end = AT91SAM9G45_BASE_TWI0 + SZ_16K - 1,
651 .flags = IORESOURCE_MEM,
654 .start = AT91SAM9G45_ID_TWI0,
655 .end = AT91SAM9G45_ID_TWI0,
656 .flags = IORESOURCE_IRQ,
660 static struct platform_device at91sam9g45_twi0_device = {
663 .resource = twi0_resources,
664 .num_resources = ARRAY_SIZE(twi0_resources),
667 static struct resource twi1_resources[] = {
669 .start = AT91SAM9G45_BASE_TWI1,
670 .end = AT91SAM9G45_BASE_TWI1 + SZ_16K - 1,
671 .flags = IORESOURCE_MEM,
674 .start = AT91SAM9G45_ID_TWI1,
675 .end = AT91SAM9G45_ID_TWI1,
676 .flags = IORESOURCE_IRQ,
680 static struct platform_device at91sam9g45_twi1_device = {
683 .resource = twi1_resources,
684 .num_resources = ARRAY_SIZE(twi1_resources),
687 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
689 i2c_register_board_info(i2c_id, devices, nr_devices);
691 /* pins used for TWI interface */
693 at91_set_A_periph(AT91_PIN_PA20, 0); /* TWD */
694 at91_set_multi_drive(AT91_PIN_PA20, 1);
696 at91_set_A_periph(AT91_PIN_PA21, 0); /* TWCK */
697 at91_set_multi_drive(AT91_PIN_PA21, 1);
699 platform_device_register(&at91sam9g45_twi0_device);
701 at91_set_A_periph(AT91_PIN_PB10, 0); /* TWD */
702 at91_set_multi_drive(AT91_PIN_PB10, 1);
704 at91_set_A_periph(AT91_PIN_PB11, 0); /* TWCK */
705 at91_set_multi_drive(AT91_PIN_PB11, 1);
707 platform_device_register(&at91sam9g45_twi1_device);
711 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices) {}
715 /* --------------------------------------------------------------------
717 * -------------------------------------------------------------------- */
719 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
720 static u64 spi_dmamask = DMA_BIT_MASK(32);
722 static struct resource spi0_resources[] = {
724 .start = AT91SAM9G45_BASE_SPI0,
725 .end = AT91SAM9G45_BASE_SPI0 + SZ_16K - 1,
726 .flags = IORESOURCE_MEM,
729 .start = AT91SAM9G45_ID_SPI0,
730 .end = AT91SAM9G45_ID_SPI0,
731 .flags = IORESOURCE_IRQ,
735 static struct platform_device at91sam9g45_spi0_device = {
739 .dma_mask = &spi_dmamask,
740 .coherent_dma_mask = DMA_BIT_MASK(32),
742 .resource = spi0_resources,
743 .num_resources = ARRAY_SIZE(spi0_resources),
746 static const unsigned spi0_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PB18, AT91_PIN_PB19, AT91_PIN_PD27 };
748 static struct resource spi1_resources[] = {
750 .start = AT91SAM9G45_BASE_SPI1,
751 .end = AT91SAM9G45_BASE_SPI1 + SZ_16K - 1,
752 .flags = IORESOURCE_MEM,
755 .start = AT91SAM9G45_ID_SPI1,
756 .end = AT91SAM9G45_ID_SPI1,
757 .flags = IORESOURCE_IRQ,
761 static struct platform_device at91sam9g45_spi1_device = {
765 .dma_mask = &spi_dmamask,
766 .coherent_dma_mask = DMA_BIT_MASK(32),
768 .resource = spi1_resources,
769 .num_resources = ARRAY_SIZE(spi1_resources),
772 static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB17, AT91_PIN_PD28, AT91_PIN_PD18, AT91_PIN_PD19 };
774 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
777 unsigned long cs_pin;
778 short enable_spi0 = 0;
779 short enable_spi1 = 0;
781 /* Choose SPI chip-selects */
782 for (i = 0; i < nr_devices; i++) {
783 if (devices[i].controller_data)
784 cs_pin = (unsigned long) devices[i].controller_data;
785 else if (devices[i].bus_num == 0)
786 cs_pin = spi0_standard_cs[devices[i].chip_select];
788 cs_pin = spi1_standard_cs[devices[i].chip_select];
790 if (!gpio_is_valid(cs_pin))
793 if (devices[i].bus_num == 0)
798 /* enable chip-select pin */
799 at91_set_gpio_output(cs_pin, 1);
801 /* pass chip-select pin to driver */
802 devices[i].controller_data = (void *) cs_pin;
805 spi_register_board_info(devices, nr_devices);
807 /* Configure SPI bus(es) */
809 at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI0_MISO */
810 at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI0_MOSI */
811 at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI0_SPCK */
813 platform_device_register(&at91sam9g45_spi0_device);
816 at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_MISO */
817 at91_set_A_periph(AT91_PIN_PB15, 0); /* SPI1_MOSI */
818 at91_set_A_periph(AT91_PIN_PB16, 0); /* SPI1_SPCK */
820 platform_device_register(&at91sam9g45_spi1_device);
824 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
828 /* --------------------------------------------------------------------
830 * -------------------------------------------------------------------- */
832 #if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
833 static u64 ac97_dmamask = DMA_BIT_MASK(32);
834 static struct ac97c_platform_data ac97_data;
836 static struct resource ac97_resources[] = {
838 .start = AT91SAM9G45_BASE_AC97C,
839 .end = AT91SAM9G45_BASE_AC97C + SZ_16K - 1,
840 .flags = IORESOURCE_MEM,
843 .start = AT91SAM9G45_ID_AC97C,
844 .end = AT91SAM9G45_ID_AC97C,
845 .flags = IORESOURCE_IRQ,
849 static struct platform_device at91sam9g45_ac97_device = {
850 .name = "atmel_ac97c",
853 .dma_mask = &ac97_dmamask,
854 .coherent_dma_mask = DMA_BIT_MASK(32),
855 .platform_data = &ac97_data,
857 .resource = ac97_resources,
858 .num_resources = ARRAY_SIZE(ac97_resources),
861 void __init at91_add_device_ac97(struct ac97c_platform_data *data)
866 at91_set_A_periph(AT91_PIN_PD8, 0); /* AC97FS */
867 at91_set_A_periph(AT91_PIN_PD9, 0); /* AC97CK */
868 at91_set_A_periph(AT91_PIN_PD7, 0); /* AC97TX */
869 at91_set_A_periph(AT91_PIN_PD6, 0); /* AC97RX */
872 if (gpio_is_valid(data->reset_pin))
873 at91_set_gpio_output(data->reset_pin, 0);
876 platform_device_register(&at91sam9g45_ac97_device);
879 void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
882 /* --------------------------------------------------------------------
883 * Image Sensor Interface
884 * -------------------------------------------------------------------- */
885 #if defined(CONFIG_VIDEO_ATMEL_ISI) || defined(CONFIG_VIDEO_ATMEL_ISI_MODULE)
886 static u64 isi_dmamask = DMA_BIT_MASK(32);
887 static struct isi_platform_data isi_data;
889 struct resource isi_resources[] = {
891 .start = AT91SAM9G45_BASE_ISI,
892 .end = AT91SAM9G45_BASE_ISI + SZ_16K - 1,
893 .flags = IORESOURCE_MEM,
896 .start = AT91SAM9G45_ID_ISI,
897 .end = AT91SAM9G45_ID_ISI,
898 .flags = IORESOURCE_IRQ,
902 static struct platform_device at91sam9g45_isi_device = {
906 .dma_mask = &isi_dmamask,
907 .coherent_dma_mask = DMA_BIT_MASK(32),
908 .platform_data = &isi_data,
910 .resource = isi_resources,
911 .num_resources = ARRAY_SIZE(isi_resources),
914 static struct clk_lookup isi_mck_lookups[] = {
915 CLKDEV_CON_DEV_ID("isi_mck", "atmel_isi.0", NULL),
918 void __init at91_add_device_isi(struct isi_platform_data *data,
928 at91_set_A_periph(AT91_PIN_PB20, 0); /* ISI_D0 */
929 at91_set_A_periph(AT91_PIN_PB21, 0); /* ISI_D1 */
930 at91_set_A_periph(AT91_PIN_PB22, 0); /* ISI_D2 */
931 at91_set_A_periph(AT91_PIN_PB23, 0); /* ISI_D3 */
932 at91_set_A_periph(AT91_PIN_PB24, 0); /* ISI_D4 */
933 at91_set_A_periph(AT91_PIN_PB25, 0); /* ISI_D5 */
934 at91_set_A_periph(AT91_PIN_PB26, 0); /* ISI_D6 */
935 at91_set_A_periph(AT91_PIN_PB27, 0); /* ISI_D7 */
936 at91_set_A_periph(AT91_PIN_PB28, 0); /* ISI_PCK */
937 at91_set_A_periph(AT91_PIN_PB30, 0); /* ISI_HSYNC */
938 at91_set_A_periph(AT91_PIN_PB29, 0); /* ISI_VSYNC */
939 at91_set_B_periph(AT91_PIN_PB8, 0); /* ISI_PD8 */
940 at91_set_B_periph(AT91_PIN_PB9, 0); /* ISI_PD9 */
941 at91_set_B_periph(AT91_PIN_PB10, 0); /* ISI_PD10 */
942 at91_set_B_periph(AT91_PIN_PB11, 0); /* ISI_PD11 */
944 platform_device_register(&at91sam9g45_isi_device);
946 if (use_pck_as_mck) {
947 at91_set_B_periph(AT91_PIN_PB31, 0); /* ISI_MCK (PCK1) */
949 pck = clk_get(NULL, "pck1");
950 parent = clk_get(NULL, "plla");
952 BUG_ON(IS_ERR(pck) || IS_ERR(parent));
954 if (clk_set_parent(pck, parent)) {
955 pr_err("Failed to set PCK's parent\n");
957 /* Register PCK as ISI_MCK */
958 isi_mck_lookups[0].clk = pck;
959 clkdev_add_table(isi_mck_lookups,
960 ARRAY_SIZE(isi_mck_lookups));
968 void __init at91_add_device_isi(struct isi_platform_data *data,
969 bool use_pck_as_mck) {}
973 /* --------------------------------------------------------------------
975 * -------------------------------------------------------------------- */
977 #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
978 static u64 lcdc_dmamask = DMA_BIT_MASK(32);
979 static struct atmel_lcdfb_info lcdc_data;
981 static struct resource lcdc_resources[] = {
983 .start = AT91SAM9G45_LCDC_BASE,
984 .end = AT91SAM9G45_LCDC_BASE + SZ_4K - 1,
985 .flags = IORESOURCE_MEM,
988 .start = AT91SAM9G45_ID_LCDC,
989 .end = AT91SAM9G45_ID_LCDC,
990 .flags = IORESOURCE_IRQ,
994 static struct platform_device at91_lcdc_device = {
995 .name = "atmel_lcdfb",
998 .dma_mask = &lcdc_dmamask,
999 .coherent_dma_mask = DMA_BIT_MASK(32),
1000 .platform_data = &lcdc_data,
1002 .resource = lcdc_resources,
1003 .num_resources = ARRAY_SIZE(lcdc_resources),
1006 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
1011 at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
1013 at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
1014 at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
1015 at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
1016 at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
1017 at91_set_A_periph(AT91_PIN_PE6, 0); /* LCDDEN */
1018 at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
1019 at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
1020 at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
1021 at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
1022 at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
1023 at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
1024 at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
1025 at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
1026 at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
1027 at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
1028 at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
1029 at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
1030 at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
1031 at91_set_A_periph(AT91_PIN_PE20, 0); /* LCDD13 */
1032 at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
1033 at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
1034 at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
1035 at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
1036 at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
1037 at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
1038 at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
1039 at91_set_A_periph(AT91_PIN_PE28, 0); /* LCDD21 */
1040 at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
1041 at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
1044 platform_device_register(&at91_lcdc_device);
1047 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
1051 /* --------------------------------------------------------------------
1052 * Timer/Counter block
1053 * -------------------------------------------------------------------- */
1055 #ifdef CONFIG_ATMEL_TCLIB
1056 static struct resource tcb0_resources[] = {
1058 .start = AT91SAM9G45_BASE_TCB0,
1059 .end = AT91SAM9G45_BASE_TCB0 + SZ_256 - 1,
1060 .flags = IORESOURCE_MEM,
1063 .start = AT91SAM9G45_ID_TCB,
1064 .end = AT91SAM9G45_ID_TCB,
1065 .flags = IORESOURCE_IRQ,
1069 static struct platform_device at91sam9g45_tcb0_device = {
1070 .name = "atmel_tcb",
1072 .resource = tcb0_resources,
1073 .num_resources = ARRAY_SIZE(tcb0_resources),
1076 /* TCB1 begins with TC3 */
1077 static struct resource tcb1_resources[] = {
1079 .start = AT91SAM9G45_BASE_TCB1,
1080 .end = AT91SAM9G45_BASE_TCB1 + SZ_256 - 1,
1081 .flags = IORESOURCE_MEM,
1084 .start = AT91SAM9G45_ID_TCB,
1085 .end = AT91SAM9G45_ID_TCB,
1086 .flags = IORESOURCE_IRQ,
1090 static struct platform_device at91sam9g45_tcb1_device = {
1091 .name = "atmel_tcb",
1093 .resource = tcb1_resources,
1094 .num_resources = ARRAY_SIZE(tcb1_resources),
1097 #if defined(CONFIG_OF)
1098 static struct of_device_id tcb_ids[] = {
1099 { .compatible = "atmel,at91rm9200-tcb" },
1104 static void __init at91_add_device_tc(void)
1106 #if defined(CONFIG_OF)
1107 struct device_node *np;
1109 np = of_find_matching_node(NULL, tcb_ids);
1116 platform_device_register(&at91sam9g45_tcb0_device);
1117 platform_device_register(&at91sam9g45_tcb1_device);
1120 static void __init at91_add_device_tc(void) { }
1124 /* --------------------------------------------------------------------
1126 * -------------------------------------------------------------------- */
1128 #if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
1129 static struct resource rtc_resources[] = {
1131 .start = AT91SAM9G45_BASE_RTC,
1132 .end = AT91SAM9G45_BASE_RTC + SZ_256 - 1,
1133 .flags = IORESOURCE_MEM,
1136 .start = AT91_ID_SYS,
1138 .flags = IORESOURCE_IRQ,
1142 static struct platform_device at91sam9g45_rtc_device = {
1145 .resource = rtc_resources,
1146 .num_resources = ARRAY_SIZE(rtc_resources),
1149 static void __init at91_add_device_rtc(void)
1151 platform_device_register(&at91sam9g45_rtc_device);
1154 static void __init at91_add_device_rtc(void) {}
1158 /* --------------------------------------------------------------------
1160 * -------------------------------------------------------------------- */
1162 #if defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC) || defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC_MODULE)
1163 static u64 tsadcc_dmamask = DMA_BIT_MASK(32);
1164 static struct at91_tsadcc_data tsadcc_data;
1166 static struct resource tsadcc_resources[] = {
1168 .start = AT91SAM9G45_BASE_TSC,
1169 .end = AT91SAM9G45_BASE_TSC + SZ_16K - 1,
1170 .flags = IORESOURCE_MEM,
1173 .start = AT91SAM9G45_ID_TSC,
1174 .end = AT91SAM9G45_ID_TSC,
1175 .flags = IORESOURCE_IRQ,
1179 static struct platform_device at91sam9g45_tsadcc_device = {
1180 .name = "atmel_tsadcc",
1183 .dma_mask = &tsadcc_dmamask,
1184 .coherent_dma_mask = DMA_BIT_MASK(32),
1185 .platform_data = &tsadcc_data,
1187 .resource = tsadcc_resources,
1188 .num_resources = ARRAY_SIZE(tsadcc_resources),
1191 void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data)
1196 at91_set_gpio_input(AT91_PIN_PD20, 0); /* AD0_XR */
1197 at91_set_gpio_input(AT91_PIN_PD21, 0); /* AD1_XL */
1198 at91_set_gpio_input(AT91_PIN_PD22, 0); /* AD2_YT */
1199 at91_set_gpio_input(AT91_PIN_PD23, 0); /* AD3_TB */
1201 tsadcc_data = *data;
1202 platform_device_register(&at91sam9g45_tsadcc_device);
1205 void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data) {}
1209 /* --------------------------------------------------------------------
1211 * -------------------------------------------------------------------- */
1213 static struct resource rtt_resources[] = {
1215 .start = AT91SAM9G45_BASE_RTT,
1216 .end = AT91SAM9G45_BASE_RTT + SZ_16 - 1,
1217 .flags = IORESOURCE_MEM,
1219 .flags = IORESOURCE_MEM,
1223 static struct platform_device at91sam9g45_rtt_device = {
1226 .resource = rtt_resources,
1229 #if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
1230 static void __init at91_add_device_rtt_rtc(void)
1232 at91sam9g45_rtt_device.name = "rtc-at91sam9";
1234 * The second resource is needed:
1235 * GPBR will serve as the storage for RTC time offset
1237 at91sam9g45_rtt_device.num_resources = 2;
1238 rtt_resources[1].start = AT91SAM9G45_BASE_GPBR +
1239 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
1240 rtt_resources[1].end = rtt_resources[1].start + 3;
1243 static void __init at91_add_device_rtt_rtc(void)
1245 /* Only one resource is needed: RTT not used as RTC */
1246 at91sam9g45_rtt_device.num_resources = 1;
1250 static void __init at91_add_device_rtt(void)
1252 at91_add_device_rtt_rtc();
1253 platform_device_register(&at91sam9g45_rtt_device);
1257 /* --------------------------------------------------------------------
1259 * -------------------------------------------------------------------- */
1261 #if defined(CONFIG_HW_RANDOM_ATMEL) || defined(CONFIG_HW_RANDOM_ATMEL_MODULE)
1262 static struct resource trng_resources[] = {
1264 .start = AT91SAM9G45_BASE_TRNG,
1265 .end = AT91SAM9G45_BASE_TRNG + SZ_16K - 1,
1266 .flags = IORESOURCE_MEM,
1270 static struct platform_device at91sam9g45_trng_device = {
1271 .name = "atmel-trng",
1273 .resource = trng_resources,
1274 .num_resources = ARRAY_SIZE(trng_resources),
1277 static void __init at91_add_device_trng(void)
1279 platform_device_register(&at91sam9g45_trng_device);
1282 static void __init at91_add_device_trng(void) {}
1285 /* --------------------------------------------------------------------
1287 * -------------------------------------------------------------------- */
1289 #if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
1290 static struct resource wdt_resources[] = {
1292 .start = AT91SAM9G45_BASE_WDT,
1293 .end = AT91SAM9G45_BASE_WDT + SZ_16 - 1,
1294 .flags = IORESOURCE_MEM,
1298 static struct platform_device at91sam9g45_wdt_device = {
1301 .resource = wdt_resources,
1302 .num_resources = ARRAY_SIZE(wdt_resources),
1305 static void __init at91_add_device_watchdog(void)
1307 platform_device_register(&at91sam9g45_wdt_device);
1310 static void __init at91_add_device_watchdog(void) {}
1314 /* --------------------------------------------------------------------
1316 * --------------------------------------------------------------------*/
1318 #if defined(CONFIG_ATMEL_PWM) || defined(CONFIG_ATMEL_PWM_MODULE)
1319 static u32 pwm_mask;
1321 static struct resource pwm_resources[] = {
1323 .start = AT91SAM9G45_BASE_PWMC,
1324 .end = AT91SAM9G45_BASE_PWMC + SZ_16K - 1,
1325 .flags = IORESOURCE_MEM,
1328 .start = AT91SAM9G45_ID_PWMC,
1329 .end = AT91SAM9G45_ID_PWMC,
1330 .flags = IORESOURCE_IRQ,
1334 static struct platform_device at91sam9g45_pwm0_device = {
1335 .name = "atmel_pwm",
1338 .platform_data = &pwm_mask,
1340 .resource = pwm_resources,
1341 .num_resources = ARRAY_SIZE(pwm_resources),
1344 void __init at91_add_device_pwm(u32 mask)
1346 if (mask & (1 << AT91_PWM0))
1347 at91_set_B_periph(AT91_PIN_PD24, 1); /* enable PWM0 */
1349 if (mask & (1 << AT91_PWM1))
1350 at91_set_B_periph(AT91_PIN_PD31, 1); /* enable PWM1 */
1352 if (mask & (1 << AT91_PWM2))
1353 at91_set_B_periph(AT91_PIN_PD26, 1); /* enable PWM2 */
1355 if (mask & (1 << AT91_PWM3))
1356 at91_set_B_periph(AT91_PIN_PD0, 1); /* enable PWM3 */
1360 platform_device_register(&at91sam9g45_pwm0_device);
1363 void __init at91_add_device_pwm(u32 mask) {}
1367 /* --------------------------------------------------------------------
1368 * SSC -- Synchronous Serial Controller
1369 * -------------------------------------------------------------------- */
1371 #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
1372 static u64 ssc0_dmamask = DMA_BIT_MASK(32);
1374 static struct resource ssc0_resources[] = {
1376 .start = AT91SAM9G45_BASE_SSC0,
1377 .end = AT91SAM9G45_BASE_SSC0 + SZ_16K - 1,
1378 .flags = IORESOURCE_MEM,
1381 .start = AT91SAM9G45_ID_SSC0,
1382 .end = AT91SAM9G45_ID_SSC0,
1383 .flags = IORESOURCE_IRQ,
1387 static struct platform_device at91sam9g45_ssc0_device = {
1391 .dma_mask = &ssc0_dmamask,
1392 .coherent_dma_mask = DMA_BIT_MASK(32),
1394 .resource = ssc0_resources,
1395 .num_resources = ARRAY_SIZE(ssc0_resources),
1398 static inline void configure_ssc0_pins(unsigned pins)
1400 if (pins & ATMEL_SSC_TF)
1401 at91_set_A_periph(AT91_PIN_PD1, 1);
1402 if (pins & ATMEL_SSC_TK)
1403 at91_set_A_periph(AT91_PIN_PD0, 1);
1404 if (pins & ATMEL_SSC_TD)
1405 at91_set_A_periph(AT91_PIN_PD2, 1);
1406 if (pins & ATMEL_SSC_RD)
1407 at91_set_A_periph(AT91_PIN_PD3, 1);
1408 if (pins & ATMEL_SSC_RK)
1409 at91_set_A_periph(AT91_PIN_PD4, 1);
1410 if (pins & ATMEL_SSC_RF)
1411 at91_set_A_periph(AT91_PIN_PD5, 1);
1414 static u64 ssc1_dmamask = DMA_BIT_MASK(32);
1416 static struct resource ssc1_resources[] = {
1418 .start = AT91SAM9G45_BASE_SSC1,
1419 .end = AT91SAM9G45_BASE_SSC1 + SZ_16K - 1,
1420 .flags = IORESOURCE_MEM,
1423 .start = AT91SAM9G45_ID_SSC1,
1424 .end = AT91SAM9G45_ID_SSC1,
1425 .flags = IORESOURCE_IRQ,
1429 static struct platform_device at91sam9g45_ssc1_device = {
1433 .dma_mask = &ssc1_dmamask,
1434 .coherent_dma_mask = DMA_BIT_MASK(32),
1436 .resource = ssc1_resources,
1437 .num_resources = ARRAY_SIZE(ssc1_resources),
1440 static inline void configure_ssc1_pins(unsigned pins)
1442 if (pins & ATMEL_SSC_TF)
1443 at91_set_A_periph(AT91_PIN_PD14, 1);
1444 if (pins & ATMEL_SSC_TK)
1445 at91_set_A_periph(AT91_PIN_PD12, 1);
1446 if (pins & ATMEL_SSC_TD)
1447 at91_set_A_periph(AT91_PIN_PD10, 1);
1448 if (pins & ATMEL_SSC_RD)
1449 at91_set_A_periph(AT91_PIN_PD11, 1);
1450 if (pins & ATMEL_SSC_RK)
1451 at91_set_A_periph(AT91_PIN_PD13, 1);
1452 if (pins & ATMEL_SSC_RF)
1453 at91_set_A_periph(AT91_PIN_PD15, 1);
1457 * SSC controllers are accessed through library code, instead of any
1458 * kind of all-singing/all-dancing driver. For example one could be
1459 * used by a particular I2S audio codec's driver, while another one
1460 * on the same system might be used by a custom data capture driver.
1462 void __init at91_add_device_ssc(unsigned id, unsigned pins)
1464 struct platform_device *pdev;
1467 * NOTE: caller is responsible for passing information matching
1468 * "pins" to whatever will be using each particular controller.
1471 case AT91SAM9G45_ID_SSC0:
1472 pdev = &at91sam9g45_ssc0_device;
1473 configure_ssc0_pins(pins);
1475 case AT91SAM9G45_ID_SSC1:
1476 pdev = &at91sam9g45_ssc1_device;
1477 configure_ssc1_pins(pins);
1483 platform_device_register(pdev);
1487 void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
1491 /* --------------------------------------------------------------------
1493 * -------------------------------------------------------------------- */
1495 #if defined(CONFIG_SERIAL_ATMEL)
1496 static struct resource dbgu_resources[] = {
1498 .start = AT91SAM9G45_BASE_DBGU,
1499 .end = AT91SAM9G45_BASE_DBGU + SZ_512 - 1,
1500 .flags = IORESOURCE_MEM,
1503 .start = AT91_ID_SYS,
1505 .flags = IORESOURCE_IRQ,
1509 static struct atmel_uart_data dbgu_data = {
1514 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
1516 static struct platform_device at91sam9g45_dbgu_device = {
1517 .name = "atmel_usart",
1520 .dma_mask = &dbgu_dmamask,
1521 .coherent_dma_mask = DMA_BIT_MASK(32),
1522 .platform_data = &dbgu_data,
1524 .resource = dbgu_resources,
1525 .num_resources = ARRAY_SIZE(dbgu_resources),
1528 static inline void configure_dbgu_pins(void)
1530 at91_set_A_periph(AT91_PIN_PB12, 0); /* DRXD */
1531 at91_set_A_periph(AT91_PIN_PB13, 1); /* DTXD */
1534 static struct resource uart0_resources[] = {
1536 .start = AT91SAM9G45_BASE_US0,
1537 .end = AT91SAM9G45_BASE_US0 + SZ_16K - 1,
1538 .flags = IORESOURCE_MEM,
1541 .start = AT91SAM9G45_ID_US0,
1542 .end = AT91SAM9G45_ID_US0,
1543 .flags = IORESOURCE_IRQ,
1547 static struct atmel_uart_data uart0_data = {
1552 static u64 uart0_dmamask = DMA_BIT_MASK(32);
1554 static struct platform_device at91sam9g45_uart0_device = {
1555 .name = "atmel_usart",
1558 .dma_mask = &uart0_dmamask,
1559 .coherent_dma_mask = DMA_BIT_MASK(32),
1560 .platform_data = &uart0_data,
1562 .resource = uart0_resources,
1563 .num_resources = ARRAY_SIZE(uart0_resources),
1566 static inline void configure_usart0_pins(unsigned pins)
1568 at91_set_A_periph(AT91_PIN_PB19, 1); /* TXD0 */
1569 at91_set_A_periph(AT91_PIN_PB18, 0); /* RXD0 */
1571 if (pins & ATMEL_UART_RTS)
1572 at91_set_B_periph(AT91_PIN_PB17, 0); /* RTS0 */
1573 if (pins & ATMEL_UART_CTS)
1574 at91_set_B_periph(AT91_PIN_PB15, 0); /* CTS0 */
1577 static struct resource uart1_resources[] = {
1579 .start = AT91SAM9G45_BASE_US1,
1580 .end = AT91SAM9G45_BASE_US1 + SZ_16K - 1,
1581 .flags = IORESOURCE_MEM,
1584 .start = AT91SAM9G45_ID_US1,
1585 .end = AT91SAM9G45_ID_US1,
1586 .flags = IORESOURCE_IRQ,
1590 static struct atmel_uart_data uart1_data = {
1595 static u64 uart1_dmamask = DMA_BIT_MASK(32);
1597 static struct platform_device at91sam9g45_uart1_device = {
1598 .name = "atmel_usart",
1601 .dma_mask = &uart1_dmamask,
1602 .coherent_dma_mask = DMA_BIT_MASK(32),
1603 .platform_data = &uart1_data,
1605 .resource = uart1_resources,
1606 .num_resources = ARRAY_SIZE(uart1_resources),
1609 static inline void configure_usart1_pins(unsigned pins)
1611 at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD1 */
1612 at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD1 */
1614 if (pins & ATMEL_UART_RTS)
1615 at91_set_A_periph(AT91_PIN_PD16, 0); /* RTS1 */
1616 if (pins & ATMEL_UART_CTS)
1617 at91_set_A_periph(AT91_PIN_PD17, 0); /* CTS1 */
1620 static struct resource uart2_resources[] = {
1622 .start = AT91SAM9G45_BASE_US2,
1623 .end = AT91SAM9G45_BASE_US2 + SZ_16K - 1,
1624 .flags = IORESOURCE_MEM,
1627 .start = AT91SAM9G45_ID_US2,
1628 .end = AT91SAM9G45_ID_US2,
1629 .flags = IORESOURCE_IRQ,
1633 static struct atmel_uart_data uart2_data = {
1638 static u64 uart2_dmamask = DMA_BIT_MASK(32);
1640 static struct platform_device at91sam9g45_uart2_device = {
1641 .name = "atmel_usart",
1644 .dma_mask = &uart2_dmamask,
1645 .coherent_dma_mask = DMA_BIT_MASK(32),
1646 .platform_data = &uart2_data,
1648 .resource = uart2_resources,
1649 .num_resources = ARRAY_SIZE(uart2_resources),
1652 static inline void configure_usart2_pins(unsigned pins)
1654 at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD2 */
1655 at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD2 */
1657 if (pins & ATMEL_UART_RTS)
1658 at91_set_B_periph(AT91_PIN_PC9, 0); /* RTS2 */
1659 if (pins & ATMEL_UART_CTS)
1660 at91_set_B_periph(AT91_PIN_PC11, 0); /* CTS2 */
1663 static struct resource uart3_resources[] = {
1665 .start = AT91SAM9G45_BASE_US3,
1666 .end = AT91SAM9G45_BASE_US3 + SZ_16K - 1,
1667 .flags = IORESOURCE_MEM,
1670 .start = AT91SAM9G45_ID_US3,
1671 .end = AT91SAM9G45_ID_US3,
1672 .flags = IORESOURCE_IRQ,
1676 static struct atmel_uart_data uart3_data = {
1681 static u64 uart3_dmamask = DMA_BIT_MASK(32);
1683 static struct platform_device at91sam9g45_uart3_device = {
1684 .name = "atmel_usart",
1687 .dma_mask = &uart3_dmamask,
1688 .coherent_dma_mask = DMA_BIT_MASK(32),
1689 .platform_data = &uart3_data,
1691 .resource = uart3_resources,
1692 .num_resources = ARRAY_SIZE(uart3_resources),
1695 static inline void configure_usart3_pins(unsigned pins)
1697 at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD3 */
1698 at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD3 */
1700 if (pins & ATMEL_UART_RTS)
1701 at91_set_B_periph(AT91_PIN_PA23, 0); /* RTS3 */
1702 if (pins & ATMEL_UART_CTS)
1703 at91_set_B_periph(AT91_PIN_PA24, 0); /* CTS3 */
1706 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1708 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1710 struct platform_device *pdev;
1711 struct atmel_uart_data *pdata;
1715 pdev = &at91sam9g45_dbgu_device;
1716 configure_dbgu_pins();
1718 case AT91SAM9G45_ID_US0:
1719 pdev = &at91sam9g45_uart0_device;
1720 configure_usart0_pins(pins);
1722 case AT91SAM9G45_ID_US1:
1723 pdev = &at91sam9g45_uart1_device;
1724 configure_usart1_pins(pins);
1726 case AT91SAM9G45_ID_US2:
1727 pdev = &at91sam9g45_uart2_device;
1728 configure_usart2_pins(pins);
1730 case AT91SAM9G45_ID_US3:
1731 pdev = &at91sam9g45_uart3_device;
1732 configure_usart3_pins(pins);
1737 pdata = pdev->dev.platform_data;
1738 pdata->num = portnr; /* update to mapped ID */
1740 if (portnr < ATMEL_MAX_UART)
1741 at91_uarts[portnr] = pdev;
1744 void __init at91_set_serial_console(unsigned portnr)
1746 if (portnr < ATMEL_MAX_UART) {
1747 atmel_default_console_device = at91_uarts[portnr];
1748 at91sam9g45_set_console_clock(at91_uarts[portnr]->id);
1752 void __init at91_add_device_serial(void)
1756 for (i = 0; i < ATMEL_MAX_UART; i++) {
1758 platform_device_register(at91_uarts[i]);
1761 if (!atmel_default_console_device)
1762 printk(KERN_INFO "AT91: No default serial console defined.\n");
1765 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1766 void __init at91_set_serial_console(unsigned portnr) {}
1767 void __init at91_add_device_serial(void) {}
1771 /* -------------------------------------------------------------------- */
1773 * These devices are always present and don't need any board-specific
1776 static int __init at91_add_standard_devices(void)
1778 at91_add_device_hdmac();
1779 at91_add_device_rtc();
1780 at91_add_device_rtt();
1781 at91_add_device_trng();
1782 at91_add_device_watchdog();
1783 at91_add_device_tc();
1787 arch_initcall(at91_add_standard_devices);