2 * Chip-specific setup code for the AT91SAM9G45 family
4 * Copyright (C) 2009 Atmel Corporation.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
13 #include <linux/module.h>
15 #include <linux/dma-mapping.h>
18 #include <asm/mach/arch.h>
19 #include <asm/mach/map.h>
20 #include <mach/at91sam9g45.h>
21 #include <mach/at91_pmc.h>
22 #include <mach/at91_rstc.h>
23 #include <mach/at91_shdwc.h>
30 /* --------------------------------------------------------------------
32 * -------------------------------------------------------------------- */
35 * The peripheral clocks.
37 static struct clk pioA_clk = {
39 .pmc_mask = 1 << AT91SAM9G45_ID_PIOA,
40 .type = CLK_TYPE_PERIPHERAL,
42 static struct clk pioB_clk = {
44 .pmc_mask = 1 << AT91SAM9G45_ID_PIOB,
45 .type = CLK_TYPE_PERIPHERAL,
47 static struct clk pioC_clk = {
49 .pmc_mask = 1 << AT91SAM9G45_ID_PIOC,
50 .type = CLK_TYPE_PERIPHERAL,
52 static struct clk pioDE_clk = {
54 .pmc_mask = 1 << AT91SAM9G45_ID_PIODE,
55 .type = CLK_TYPE_PERIPHERAL,
57 static struct clk trng_clk = {
59 .pmc_mask = 1 << AT91SAM9G45_ID_TRNG,
60 .type = CLK_TYPE_PERIPHERAL,
62 static struct clk usart0_clk = {
64 .pmc_mask = 1 << AT91SAM9G45_ID_US0,
65 .type = CLK_TYPE_PERIPHERAL,
67 static struct clk usart1_clk = {
69 .pmc_mask = 1 << AT91SAM9G45_ID_US1,
70 .type = CLK_TYPE_PERIPHERAL,
72 static struct clk usart2_clk = {
74 .pmc_mask = 1 << AT91SAM9G45_ID_US2,
75 .type = CLK_TYPE_PERIPHERAL,
77 static struct clk usart3_clk = {
79 .pmc_mask = 1 << AT91SAM9G45_ID_US3,
80 .type = CLK_TYPE_PERIPHERAL,
82 static struct clk mmc0_clk = {
84 .pmc_mask = 1 << AT91SAM9G45_ID_MCI0,
85 .type = CLK_TYPE_PERIPHERAL,
87 static struct clk twi0_clk = {
89 .pmc_mask = 1 << AT91SAM9G45_ID_TWI0,
90 .type = CLK_TYPE_PERIPHERAL,
92 static struct clk twi1_clk = {
94 .pmc_mask = 1 << AT91SAM9G45_ID_TWI1,
95 .type = CLK_TYPE_PERIPHERAL,
97 static struct clk spi0_clk = {
99 .pmc_mask = 1 << AT91SAM9G45_ID_SPI0,
100 .type = CLK_TYPE_PERIPHERAL,
102 static struct clk spi1_clk = {
104 .pmc_mask = 1 << AT91SAM9G45_ID_SPI1,
105 .type = CLK_TYPE_PERIPHERAL,
107 static struct clk ssc0_clk = {
109 .pmc_mask = 1 << AT91SAM9G45_ID_SSC0,
110 .type = CLK_TYPE_PERIPHERAL,
112 static struct clk ssc1_clk = {
114 .pmc_mask = 1 << AT91SAM9G45_ID_SSC1,
115 .type = CLK_TYPE_PERIPHERAL,
117 static struct clk tcb0_clk = {
119 .pmc_mask = 1 << AT91SAM9G45_ID_TCB,
120 .type = CLK_TYPE_PERIPHERAL,
122 static struct clk pwm_clk = {
124 .pmc_mask = 1 << AT91SAM9G45_ID_PWMC,
125 .type = CLK_TYPE_PERIPHERAL,
127 static struct clk tsc_clk = {
129 .pmc_mask = 1 << AT91SAM9G45_ID_TSC,
130 .type = CLK_TYPE_PERIPHERAL,
132 static struct clk dma_clk = {
134 .pmc_mask = 1 << AT91SAM9G45_ID_DMA,
135 .type = CLK_TYPE_PERIPHERAL,
137 static struct clk uhphs_clk = {
139 .pmc_mask = 1 << AT91SAM9G45_ID_UHPHS,
140 .type = CLK_TYPE_PERIPHERAL,
142 static struct clk lcdc_clk = {
144 .pmc_mask = 1 << AT91SAM9G45_ID_LCDC,
145 .type = CLK_TYPE_PERIPHERAL,
147 static struct clk ac97_clk = {
149 .pmc_mask = 1 << AT91SAM9G45_ID_AC97C,
150 .type = CLK_TYPE_PERIPHERAL,
152 static struct clk macb_clk = {
154 .pmc_mask = 1 << AT91SAM9G45_ID_EMAC,
155 .type = CLK_TYPE_PERIPHERAL,
157 static struct clk isi_clk = {
159 .pmc_mask = 1 << AT91SAM9G45_ID_ISI,
160 .type = CLK_TYPE_PERIPHERAL,
162 static struct clk udphs_clk = {
164 .pmc_mask = 1 << AT91SAM9G45_ID_UDPHS,
165 .type = CLK_TYPE_PERIPHERAL,
167 static struct clk mmc1_clk = {
169 .pmc_mask = 1 << AT91SAM9G45_ID_MCI1,
170 .type = CLK_TYPE_PERIPHERAL,
173 /* Video decoder clock - Only for sam9m10/sam9m11 */
174 static struct clk vdec_clk = {
176 .pmc_mask = 1 << AT91SAM9G45_ID_VDEC,
177 .type = CLK_TYPE_PERIPHERAL,
180 static struct clk *periph_clocks[] __initdata = {
211 static struct clk_lookup periph_clocks_lookups[] = {
212 /* One additional fake clock for ohci */
213 CLKDEV_CON_ID("ohci_clk", &uhphs_clk),
214 CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk),
215 CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
216 CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
217 CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
218 CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
219 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
220 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
221 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk),
222 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk),
223 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
224 CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
225 CLKDEV_CON_DEV_ID(NULL, "atmel-trng", &trng_clk),
226 /* more usart lookup table for DT entries */
227 CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
228 CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
229 CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
230 CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
231 CLKDEV_CON_DEV_ID("usart", "fff98000.serial", &usart3_clk),
232 /* fake hclk clock */
233 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
236 static struct clk_lookup usart_clocks_lookups[] = {
237 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
238 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
239 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
240 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
241 CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
245 * The two programmable clocks.
246 * You must configure pin multiplexing to bring these signals out.
248 static struct clk pck0 = {
250 .pmc_mask = AT91_PMC_PCK0,
251 .type = CLK_TYPE_PROGRAMMABLE,
254 static struct clk pck1 = {
256 .pmc_mask = AT91_PMC_PCK1,
257 .type = CLK_TYPE_PROGRAMMABLE,
261 static void __init at91sam9g45_register_clocks(void)
265 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
266 clk_register(periph_clocks[i]);
268 clkdev_add_table(periph_clocks_lookups,
269 ARRAY_SIZE(periph_clocks_lookups));
270 clkdev_add_table(usart_clocks_lookups,
271 ARRAY_SIZE(usart_clocks_lookups));
273 if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11())
274 clk_register(&vdec_clk);
280 static struct clk_lookup console_clock_lookup;
282 void __init at91sam9g45_set_console_clock(int id)
284 if (id >= ARRAY_SIZE(usart_clocks_lookups))
287 console_clock_lookup.con_id = "usart";
288 console_clock_lookup.clk = usart_clocks_lookups[id].clk;
289 clkdev_add(&console_clock_lookup);
292 /* --------------------------------------------------------------------
294 * -------------------------------------------------------------------- */
296 static struct at91_gpio_bank at91sam9g45_gpio[] = {
298 .id = AT91SAM9G45_ID_PIOA,
302 .id = AT91SAM9G45_ID_PIOB,
306 .id = AT91SAM9G45_ID_PIOC,
310 .id = AT91SAM9G45_ID_PIODE,
314 .id = AT91SAM9G45_ID_PIODE,
320 static void at91sam9g45_reset(void)
322 at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
325 static void at91sam9g45_poweroff(void)
327 at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
331 /* --------------------------------------------------------------------
332 * AT91SAM9G45 processor initialization
333 * -------------------------------------------------------------------- */
335 static void __init at91sam9g45_map_io(void)
337 at91_init_sram(0, AT91SAM9G45_SRAM_BASE, AT91SAM9G45_SRAM_SIZE);
338 init_consistent_dma_size(SZ_4M);
341 static void __init at91sam9g45_initialize(void)
343 at91_arch_reset = at91sam9g45_reset;
344 pm_power_off = at91sam9g45_poweroff;
345 at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);
347 /* Register GPIO subsystem */
348 at91_gpio_init(at91sam9g45_gpio, 5);
351 /* --------------------------------------------------------------------
352 * Interrupt initialization
353 * -------------------------------------------------------------------- */
356 * The default interrupt priority levels (0 = lowest, 7 = highest).
358 static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
359 7, /* Advanced Interrupt Controller (FIQ) */
360 7, /* System Peripherals */
361 1, /* Parallel IO Controller A */
362 1, /* Parallel IO Controller B */
363 1, /* Parallel IO Controller C */
364 1, /* Parallel IO Controller D and E */
370 0, /* Multimedia Card Interface 0 */
371 6, /* Two-Wire Interface 0 */
372 6, /* Two-Wire Interface 1 */
373 5, /* Serial Peripheral Interface 0 */
374 5, /* Serial Peripheral Interface 1 */
375 4, /* Serial Synchronous Controller 0 */
376 4, /* Serial Synchronous Controller 1 */
377 0, /* Timer Counter 0, 1, 2, 3, 4 and 5 */
378 0, /* Pulse Width Modulation Controller */
379 0, /* Touch Screen Controller */
380 0, /* DMA Controller */
381 2, /* USB Host High Speed port */
382 3, /* LDC Controller */
383 5, /* AC97 Controller */
385 0, /* Image Sensor Interface */
386 2, /* USB Device High speed port */
388 0, /* Multimedia Card Interface 1 */
390 0, /* Advanced Interrupt Controller (IRQ0) */
393 struct at91_init_soc __initdata at91sam9g45_soc = {
394 .map_io = at91sam9g45_map_io,
395 .default_irq_priority = at91sam9g45_default_irq_priority,
396 .register_clocks = at91sam9g45_register_clocks,
397 .init = at91sam9g45_initialize,