2 * reset AT91SAM9G20 as per errata
6 * unless the SDRAM is cleanly shutdown before we hit the
7 * reset register it can be left driving the data bus and
8 * killing the chance of a subsequent boot from NAND
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
16 #define CP15_CR_I (1 << 12)
18 #define SYS_VIRT_OFS (-0x01000000)
20 #define SDRAMC_BASE (SYS_VIRT_OFS + 0xffffea00)
21 #define SDRAMC_TR 0x0004
22 #define SDRAMC_LPR 0x0010
23 #define SDRAMC_LPCB_POWER_DOWN 2
25 #define RSTC_BASE (SYS_VIRT_OFS + 0xfffffd00)
26 #define RSTC_CR 0x0000
27 #define RSTC_PROCRST (1 << 0)
28 #define RSTC_PERRST (1 << 2)
29 #define RSTC_KEY (0xa5 << 24)
33 .globl at91sam9g20_reset
35 at91sam9g20_reset: mov r0, #0
36 mcr p15, 0, r0, c7, c5, 0 @ flush I-cache
38 mrc p15, 0, r0, c1, c0, 0
39 orr r0, r0, #CP15_CR_I
40 mcr p15, 0, r0, c1, c0, 0 @ enable I-cache
42 ldr r0, =SDRAMC_BASE @ preload constants
46 mov r3, #SDRAMC_LPCB_POWER_DOWN
47 ldr r4, =RSTC_KEY | RSTC_PERRST | RSTC_PROCRST
49 .balign 32 @ align to cache line
51 str r2, [r0, #SDRAMC_TR] @ disable SDRAM access
52 str r3, [r0, #SDRAMC_LPR] @ power down SDRAM
53 str r4, [r1, #RSTC_CR] @ reset processor