2 * arch/arm/mach-at91/at91sam9263.c
4 * Copyright (C) 2007 Atmel Corporation.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
13 #include <linux/module.h>
17 #include <asm/mach/arch.h>
18 #include <asm/mach/map.h>
19 #include <mach/at91sam9263.h>
20 #include <mach/at91_pmc.h>
21 #include <mach/at91_rstc.h>
22 #include <mach/at91_shdwc.h>
28 /* --------------------------------------------------------------------
30 * -------------------------------------------------------------------- */
33 * The peripheral clocks.
35 static struct clk pioA_clk = {
37 .pmc_mask = 1 << AT91SAM9263_ID_PIOA,
38 .type = CLK_TYPE_PERIPHERAL,
40 static struct clk pioB_clk = {
42 .pmc_mask = 1 << AT91SAM9263_ID_PIOB,
43 .type = CLK_TYPE_PERIPHERAL,
45 static struct clk pioCDE_clk = {
47 .pmc_mask = 1 << AT91SAM9263_ID_PIOCDE,
48 .type = CLK_TYPE_PERIPHERAL,
50 static struct clk usart0_clk = {
52 .pmc_mask = 1 << AT91SAM9263_ID_US0,
53 .type = CLK_TYPE_PERIPHERAL,
55 static struct clk usart1_clk = {
57 .pmc_mask = 1 << AT91SAM9263_ID_US1,
58 .type = CLK_TYPE_PERIPHERAL,
60 static struct clk usart2_clk = {
62 .pmc_mask = 1 << AT91SAM9263_ID_US2,
63 .type = CLK_TYPE_PERIPHERAL,
65 static struct clk mmc0_clk = {
67 .pmc_mask = 1 << AT91SAM9263_ID_MCI0,
68 .type = CLK_TYPE_PERIPHERAL,
70 static struct clk mmc1_clk = {
72 .pmc_mask = 1 << AT91SAM9263_ID_MCI1,
73 .type = CLK_TYPE_PERIPHERAL,
75 static struct clk can_clk = {
77 .pmc_mask = 1 << AT91SAM9263_ID_CAN,
78 .type = CLK_TYPE_PERIPHERAL,
80 static struct clk twi_clk = {
82 .pmc_mask = 1 << AT91SAM9263_ID_TWI,
83 .type = CLK_TYPE_PERIPHERAL,
85 static struct clk spi0_clk = {
87 .pmc_mask = 1 << AT91SAM9263_ID_SPI0,
88 .type = CLK_TYPE_PERIPHERAL,
90 static struct clk spi1_clk = {
92 .pmc_mask = 1 << AT91SAM9263_ID_SPI1,
93 .type = CLK_TYPE_PERIPHERAL,
95 static struct clk ssc0_clk = {
97 .pmc_mask = 1 << AT91SAM9263_ID_SSC0,
98 .type = CLK_TYPE_PERIPHERAL,
100 static struct clk ssc1_clk = {
102 .pmc_mask = 1 << AT91SAM9263_ID_SSC1,
103 .type = CLK_TYPE_PERIPHERAL,
105 static struct clk ac97_clk = {
107 .pmc_mask = 1 << AT91SAM9263_ID_AC97C,
108 .type = CLK_TYPE_PERIPHERAL,
110 static struct clk tcb_clk = {
112 .pmc_mask = 1 << AT91SAM9263_ID_TCB,
113 .type = CLK_TYPE_PERIPHERAL,
115 static struct clk pwm_clk = {
117 .pmc_mask = 1 << AT91SAM9263_ID_PWMC,
118 .type = CLK_TYPE_PERIPHERAL,
120 static struct clk macb_clk = {
122 .pmc_mask = 1 << AT91SAM9263_ID_EMAC,
123 .type = CLK_TYPE_PERIPHERAL,
125 static struct clk dma_clk = {
127 .pmc_mask = 1 << AT91SAM9263_ID_DMA,
128 .type = CLK_TYPE_PERIPHERAL,
130 static struct clk twodge_clk = {
132 .pmc_mask = 1 << AT91SAM9263_ID_2DGE,
133 .type = CLK_TYPE_PERIPHERAL,
135 static struct clk udc_clk = {
137 .pmc_mask = 1 << AT91SAM9263_ID_UDP,
138 .type = CLK_TYPE_PERIPHERAL,
140 static struct clk isi_clk = {
142 .pmc_mask = 1 << AT91SAM9263_ID_ISI,
143 .type = CLK_TYPE_PERIPHERAL,
145 static struct clk lcdc_clk = {
147 .pmc_mask = 1 << AT91SAM9263_ID_LCDC,
148 .type = CLK_TYPE_PERIPHERAL,
150 static struct clk ohci_clk = {
152 .pmc_mask = 1 << AT91SAM9263_ID_UHP,
153 .type = CLK_TYPE_PERIPHERAL,
156 static struct clk *periph_clocks[] __initdata = {
184 static struct clk_lookup periph_clocks_lookups[] = {
185 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
186 CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
187 CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk),
188 CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.1", &mmc1_clk),
189 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
190 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
191 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
194 static struct clk_lookup usart_clocks_lookups[] = {
195 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
196 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
197 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
198 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
202 * The four programmable clocks.
203 * You must configure pin multiplexing to bring these signals out.
205 static struct clk pck0 = {
207 .pmc_mask = AT91_PMC_PCK0,
208 .type = CLK_TYPE_PROGRAMMABLE,
211 static struct clk pck1 = {
213 .pmc_mask = AT91_PMC_PCK1,
214 .type = CLK_TYPE_PROGRAMMABLE,
217 static struct clk pck2 = {
219 .pmc_mask = AT91_PMC_PCK2,
220 .type = CLK_TYPE_PROGRAMMABLE,
223 static struct clk pck3 = {
225 .pmc_mask = AT91_PMC_PCK3,
226 .type = CLK_TYPE_PROGRAMMABLE,
230 static void __init at91sam9263_register_clocks(void)
234 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
235 clk_register(periph_clocks[i]);
237 clkdev_add_table(periph_clocks_lookups,
238 ARRAY_SIZE(periph_clocks_lookups));
239 clkdev_add_table(usart_clocks_lookups,
240 ARRAY_SIZE(usart_clocks_lookups));
248 static struct clk_lookup console_clock_lookup;
250 void __init at91sam9263_set_console_clock(int id)
252 if (id >= ARRAY_SIZE(usart_clocks_lookups))
255 console_clock_lookup.con_id = "usart";
256 console_clock_lookup.clk = usart_clocks_lookups[id].clk;
257 clkdev_add(&console_clock_lookup);
260 /* --------------------------------------------------------------------
262 * -------------------------------------------------------------------- */
264 static struct at91_gpio_bank at91sam9263_gpio[] = {
266 .id = AT91SAM9263_ID_PIOA,
270 .id = AT91SAM9263_ID_PIOB,
274 .id = AT91SAM9263_ID_PIOCDE,
276 .clock = &pioCDE_clk,
278 .id = AT91SAM9263_ID_PIOCDE,
280 .clock = &pioCDE_clk,
282 .id = AT91SAM9263_ID_PIOCDE,
284 .clock = &pioCDE_clk,
288 static void at91sam9263_poweroff(void)
290 at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
294 /* --------------------------------------------------------------------
295 * AT91SAM9263 processor initialization
296 * -------------------------------------------------------------------- */
298 static void __init at91sam9263_map_io(void)
300 at91_init_sram(0, AT91SAM9263_SRAM0_BASE, AT91SAM9263_SRAM0_SIZE);
301 at91_init_sram(1, AT91SAM9263_SRAM1_BASE, AT91SAM9263_SRAM1_SIZE);
304 static void __init at91sam9263_initialize(void)
306 at91_arch_reset = at91sam9_alt_reset;
307 pm_power_off = at91sam9263_poweroff;
308 at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);
310 /* Register GPIO subsystem */
311 at91_gpio_init(at91sam9263_gpio, 5);
314 /* --------------------------------------------------------------------
315 * Interrupt initialization
316 * -------------------------------------------------------------------- */
319 * The default interrupt priority levels (0 = lowest, 7 = highest).
321 static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
322 7, /* Advanced Interrupt Controller (FIQ) */
323 7, /* System Peripherals */
324 1, /* Parallel IO Controller A */
325 1, /* Parallel IO Controller B */
326 1, /* Parallel IO Controller C, D and E */
332 0, /* Multimedia Card Interface 0 */
333 0, /* Multimedia Card Interface 1 */
335 6, /* Two-Wire Interface */
336 5, /* Serial Peripheral Interface 0 */
337 5, /* Serial Peripheral Interface 1 */
338 4, /* Serial Synchronous Controller 0 */
339 4, /* Serial Synchronous Controller 1 */
340 5, /* AC97 Controller */
341 0, /* Timer Counter 0, 1 and 2 */
342 0, /* Pulse Width Modulation Controller */
345 0, /* 2D Graphic Engine */
346 2, /* USB Device Port */
347 0, /* Image Sensor Interface */
348 3, /* LDC Controller */
349 0, /* DMA Controller */
351 2, /* USB Host port */
352 0, /* Advanced Interrupt Controller (IRQ0) */
353 0, /* Advanced Interrupt Controller (IRQ1) */
356 struct at91_init_soc __initdata at91sam9263_soc = {
357 .map_io = at91sam9263_map_io,
358 .default_irq_priority = at91sam9263_default_irq_priority,
359 .register_clocks = at91sam9263_register_clocks,
360 .init = at91sam9263_initialize,