2 * arch/arm/mach-at91/at91sam9261.c
4 * Copyright (C) 2005 SAN People
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
13 #include <linux/module.h>
17 #include <asm/mach/arch.h>
18 #include <asm/mach/map.h>
20 #include <mach/at91sam9261.h>
21 #include <mach/at91_pmc.h>
22 #include <mach/at91_rstc.h>
23 #include <mach/at91_shdwc.h>
29 static struct map_desc at91sam9261_sram_desc[] __initdata = {
31 .virtual = AT91_IO_VIRT_BASE - AT91SAM9261_SRAM_SIZE,
32 .pfn = __phys_to_pfn(AT91SAM9261_SRAM_BASE),
33 .length = AT91SAM9261_SRAM_SIZE,
38 static struct map_desc at91sam9g10_sram_desc[] __initdata = {
40 .virtual = AT91_IO_VIRT_BASE - AT91SAM9G10_SRAM_SIZE,
41 .pfn = __phys_to_pfn(AT91SAM9G10_SRAM_BASE),
42 .length = AT91SAM9G10_SRAM_SIZE,
47 /* --------------------------------------------------------------------
49 * -------------------------------------------------------------------- */
52 * The peripheral clocks.
54 static struct clk pioA_clk = {
56 .pmc_mask = 1 << AT91SAM9261_ID_PIOA,
57 .type = CLK_TYPE_PERIPHERAL,
59 static struct clk pioB_clk = {
61 .pmc_mask = 1 << AT91SAM9261_ID_PIOB,
62 .type = CLK_TYPE_PERIPHERAL,
64 static struct clk pioC_clk = {
66 .pmc_mask = 1 << AT91SAM9261_ID_PIOC,
67 .type = CLK_TYPE_PERIPHERAL,
69 static struct clk usart0_clk = {
71 .pmc_mask = 1 << AT91SAM9261_ID_US0,
72 .type = CLK_TYPE_PERIPHERAL,
74 static struct clk usart1_clk = {
76 .pmc_mask = 1 << AT91SAM9261_ID_US1,
77 .type = CLK_TYPE_PERIPHERAL,
79 static struct clk usart2_clk = {
81 .pmc_mask = 1 << AT91SAM9261_ID_US2,
82 .type = CLK_TYPE_PERIPHERAL,
84 static struct clk mmc_clk = {
86 .pmc_mask = 1 << AT91SAM9261_ID_MCI,
87 .type = CLK_TYPE_PERIPHERAL,
89 static struct clk udc_clk = {
91 .pmc_mask = 1 << AT91SAM9261_ID_UDP,
92 .type = CLK_TYPE_PERIPHERAL,
94 static struct clk twi_clk = {
96 .pmc_mask = 1 << AT91SAM9261_ID_TWI,
97 .type = CLK_TYPE_PERIPHERAL,
99 static struct clk spi0_clk = {
101 .pmc_mask = 1 << AT91SAM9261_ID_SPI0,
102 .type = CLK_TYPE_PERIPHERAL,
104 static struct clk spi1_clk = {
106 .pmc_mask = 1 << AT91SAM9261_ID_SPI1,
107 .type = CLK_TYPE_PERIPHERAL,
109 static struct clk ssc0_clk = {
111 .pmc_mask = 1 << AT91SAM9261_ID_SSC0,
112 .type = CLK_TYPE_PERIPHERAL,
114 static struct clk ssc1_clk = {
116 .pmc_mask = 1 << AT91SAM9261_ID_SSC1,
117 .type = CLK_TYPE_PERIPHERAL,
119 static struct clk ssc2_clk = {
121 .pmc_mask = 1 << AT91SAM9261_ID_SSC2,
122 .type = CLK_TYPE_PERIPHERAL,
124 static struct clk tc0_clk = {
126 .pmc_mask = 1 << AT91SAM9261_ID_TC0,
127 .type = CLK_TYPE_PERIPHERAL,
129 static struct clk tc1_clk = {
131 .pmc_mask = 1 << AT91SAM9261_ID_TC1,
132 .type = CLK_TYPE_PERIPHERAL,
134 static struct clk tc2_clk = {
136 .pmc_mask = 1 << AT91SAM9261_ID_TC2,
137 .type = CLK_TYPE_PERIPHERAL,
139 static struct clk ohci_clk = {
141 .pmc_mask = 1 << AT91SAM9261_ID_UHP,
142 .type = CLK_TYPE_PERIPHERAL,
144 static struct clk lcdc_clk = {
146 .pmc_mask = 1 << AT91SAM9261_ID_LCDC,
147 .type = CLK_TYPE_PERIPHERAL,
150 static struct clk *periph_clocks[] __initdata = {
173 static struct clk_lookup periph_clocks_lookups[] = {
174 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
175 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
176 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
177 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
178 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc1_clk),
179 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
180 CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
181 CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
184 static struct clk_lookup usart_clocks_lookups[] = {
185 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
186 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
187 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
188 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
192 * The four programmable clocks.
193 * You must configure pin multiplexing to bring these signals out.
195 static struct clk pck0 = {
197 .pmc_mask = AT91_PMC_PCK0,
198 .type = CLK_TYPE_PROGRAMMABLE,
201 static struct clk pck1 = {
203 .pmc_mask = AT91_PMC_PCK1,
204 .type = CLK_TYPE_PROGRAMMABLE,
207 static struct clk pck2 = {
209 .pmc_mask = AT91_PMC_PCK2,
210 .type = CLK_TYPE_PROGRAMMABLE,
213 static struct clk pck3 = {
215 .pmc_mask = AT91_PMC_PCK3,
216 .type = CLK_TYPE_PROGRAMMABLE,
221 static struct clk hck0 = {
223 .pmc_mask = AT91_PMC_HCK0,
224 .type = CLK_TYPE_SYSTEM,
227 static struct clk hck1 = {
229 .pmc_mask = AT91_PMC_HCK1,
230 .type = CLK_TYPE_SYSTEM,
234 static void __init at91sam9261_register_clocks(void)
238 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
239 clk_register(periph_clocks[i]);
241 clkdev_add_table(periph_clocks_lookups,
242 ARRAY_SIZE(periph_clocks_lookups));
243 clkdev_add_table(usart_clocks_lookups,
244 ARRAY_SIZE(usart_clocks_lookups));
255 static struct clk_lookup console_clock_lookup;
257 void __init at91sam9261_set_console_clock(int id)
259 if (id >= ARRAY_SIZE(usart_clocks_lookups))
262 console_clock_lookup.con_id = "usart";
263 console_clock_lookup.clk = usart_clocks_lookups[id].clk;
264 clkdev_add(&console_clock_lookup);
267 /* --------------------------------------------------------------------
269 * -------------------------------------------------------------------- */
271 static struct at91_gpio_bank at91sam9261_gpio[] = {
273 .id = AT91SAM9261_ID_PIOA,
277 .id = AT91SAM9261_ID_PIOB,
281 .id = AT91SAM9261_ID_PIOC,
287 static void at91sam9261_poweroff(void)
289 at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
293 /* --------------------------------------------------------------------
294 * AT91SAM9261 processor initialization
295 * -------------------------------------------------------------------- */
297 static void __init at91sam9261_map_io(void)
299 if (cpu_is_at91sam9g10())
300 iotable_init(at91sam9g10_sram_desc, ARRAY_SIZE(at91sam9g10_sram_desc));
302 iotable_init(at91sam9261_sram_desc, ARRAY_SIZE(at91sam9261_sram_desc));
305 static void __init at91sam9261_initialize(unsigned long main_clock)
307 at91_arch_reset = at91sam9_alt_reset;
308 pm_power_off = at91sam9261_poweroff;
309 at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
310 | (1 << AT91SAM9261_ID_IRQ2);
312 /* Init clock subsystem */
313 at91_clock_init(main_clock);
315 /* Register the processor-specific clocks */
316 at91sam9261_register_clocks();
318 /* Register GPIO subsystem */
319 at91_gpio_init(at91sam9261_gpio, 3);
322 /* --------------------------------------------------------------------
323 * Interrupt initialization
324 * -------------------------------------------------------------------- */
327 * The default interrupt priority levels (0 = lowest, 7 = highest).
329 static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
330 7, /* Advanced Interrupt Controller */
331 7, /* System Peripherals */
332 1, /* Parallel IO Controller A */
333 1, /* Parallel IO Controller B */
334 1, /* Parallel IO Controller C */
339 0, /* Multimedia Card Interface */
340 2, /* USB Device Port */
341 6, /* Two-Wire Interface */
342 5, /* Serial Peripheral Interface 0 */
343 5, /* Serial Peripheral Interface 1 */
344 4, /* Serial Synchronous Controller 0 */
345 4, /* Serial Synchronous Controller 1 */
346 4, /* Serial Synchronous Controller 2 */
347 0, /* Timer Counter 0 */
348 0, /* Timer Counter 1 */
349 0, /* Timer Counter 2 */
350 2, /* USB Host port */
351 3, /* LCD Controller */
359 0, /* Advanced Interrupt Controller */
360 0, /* Advanced Interrupt Controller */
361 0, /* Advanced Interrupt Controller */
364 void __init at91sam9261_init_interrupts(unsigned int priority[NR_AIC_IRQS])
367 priority = at91sam9261_default_irq_priority;
369 /* Initialize the AIC interrupt controller */
370 at91_aic_init(priority);
372 /* Enable GPIO interrupts */
373 at91_gpio_irq_setup();
376 struct at91_soc __initdata at91sam9261_soc = {
377 .map_io = at91sam9261_map_io,
378 .init = at91sam9261_initialize,