2 * arch/arm/mach-at91/at91rm9200.c
4 * Copyright (C) 2005 SAN People
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
13 #include <linux/module.h>
16 #include <asm/mach/arch.h>
17 #include <asm/mach/map.h>
18 #include <mach/at91rm9200.h>
19 #include <mach/at91_pmc.h>
20 #include <mach/at91_st.h>
28 static struct map_desc at91rm9200_io_desc[] __initdata = {
30 .virtual = AT91_VA_BASE_EMAC,
31 .pfn = __phys_to_pfn(AT91RM9200_BASE_EMAC),
37 /* --------------------------------------------------------------------
39 * -------------------------------------------------------------------- */
42 * The peripheral clocks.
44 static struct clk udc_clk = {
46 .pmc_mask = 1 << AT91RM9200_ID_UDP,
47 .type = CLK_TYPE_PERIPHERAL,
49 static struct clk ohci_clk = {
51 .pmc_mask = 1 << AT91RM9200_ID_UHP,
52 .type = CLK_TYPE_PERIPHERAL,
54 static struct clk ether_clk = {
56 .pmc_mask = 1 << AT91RM9200_ID_EMAC,
57 .type = CLK_TYPE_PERIPHERAL,
59 static struct clk mmc_clk = {
61 .pmc_mask = 1 << AT91RM9200_ID_MCI,
62 .type = CLK_TYPE_PERIPHERAL,
64 static struct clk twi_clk = {
66 .pmc_mask = 1 << AT91RM9200_ID_TWI,
67 .type = CLK_TYPE_PERIPHERAL,
69 static struct clk usart0_clk = {
71 .pmc_mask = 1 << AT91RM9200_ID_US0,
72 .type = CLK_TYPE_PERIPHERAL,
74 static struct clk usart1_clk = {
76 .pmc_mask = 1 << AT91RM9200_ID_US1,
77 .type = CLK_TYPE_PERIPHERAL,
79 static struct clk usart2_clk = {
81 .pmc_mask = 1 << AT91RM9200_ID_US2,
82 .type = CLK_TYPE_PERIPHERAL,
84 static struct clk usart3_clk = {
86 .pmc_mask = 1 << AT91RM9200_ID_US3,
87 .type = CLK_TYPE_PERIPHERAL,
89 static struct clk spi_clk = {
91 .pmc_mask = 1 << AT91RM9200_ID_SPI,
92 .type = CLK_TYPE_PERIPHERAL,
94 static struct clk pioA_clk = {
96 .pmc_mask = 1 << AT91RM9200_ID_PIOA,
97 .type = CLK_TYPE_PERIPHERAL,
99 static struct clk pioB_clk = {
101 .pmc_mask = 1 << AT91RM9200_ID_PIOB,
102 .type = CLK_TYPE_PERIPHERAL,
104 static struct clk pioC_clk = {
106 .pmc_mask = 1 << AT91RM9200_ID_PIOC,
107 .type = CLK_TYPE_PERIPHERAL,
109 static struct clk pioD_clk = {
111 .pmc_mask = 1 << AT91RM9200_ID_PIOD,
112 .type = CLK_TYPE_PERIPHERAL,
114 static struct clk ssc0_clk = {
116 .pmc_mask = 1 << AT91RM9200_ID_SSC0,
117 .type = CLK_TYPE_PERIPHERAL,
119 static struct clk ssc1_clk = {
121 .pmc_mask = 1 << AT91RM9200_ID_SSC1,
122 .type = CLK_TYPE_PERIPHERAL,
124 static struct clk ssc2_clk = {
126 .pmc_mask = 1 << AT91RM9200_ID_SSC2,
127 .type = CLK_TYPE_PERIPHERAL,
129 static struct clk tc0_clk = {
131 .pmc_mask = 1 << AT91RM9200_ID_TC0,
132 .type = CLK_TYPE_PERIPHERAL,
134 static struct clk tc1_clk = {
136 .pmc_mask = 1 << AT91RM9200_ID_TC1,
137 .type = CLK_TYPE_PERIPHERAL,
139 static struct clk tc2_clk = {
141 .pmc_mask = 1 << AT91RM9200_ID_TC2,
142 .type = CLK_TYPE_PERIPHERAL,
144 static struct clk tc3_clk = {
146 .pmc_mask = 1 << AT91RM9200_ID_TC3,
147 .type = CLK_TYPE_PERIPHERAL,
149 static struct clk tc4_clk = {
151 .pmc_mask = 1 << AT91RM9200_ID_TC4,
152 .type = CLK_TYPE_PERIPHERAL,
154 static struct clk tc5_clk = {
156 .pmc_mask = 1 << AT91RM9200_ID_TC5,
157 .type = CLK_TYPE_PERIPHERAL,
160 static struct clk *periph_clocks[] __initdata = {
187 static struct clk_lookup periph_clocks_lookups[] = {
188 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
189 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
190 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
191 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
192 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
193 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
194 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
195 CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
196 CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
197 /* fake hclk clock */
198 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
199 CLKDEV_CON_ID("pioA", &pioA_clk),
200 CLKDEV_CON_ID("pioB", &pioB_clk),
201 CLKDEV_CON_ID("pioC", &pioC_clk),
202 CLKDEV_CON_ID("pioD", &pioD_clk),
205 static struct clk_lookup usart_clocks_lookups[] = {
206 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
207 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
208 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
209 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
210 CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
214 * The four programmable clocks.
215 * You must configure pin multiplexing to bring these signals out.
217 static struct clk pck0 = {
219 .pmc_mask = AT91_PMC_PCK0,
220 .type = CLK_TYPE_PROGRAMMABLE,
223 static struct clk pck1 = {
225 .pmc_mask = AT91_PMC_PCK1,
226 .type = CLK_TYPE_PROGRAMMABLE,
229 static struct clk pck2 = {
231 .pmc_mask = AT91_PMC_PCK2,
232 .type = CLK_TYPE_PROGRAMMABLE,
235 static struct clk pck3 = {
237 .pmc_mask = AT91_PMC_PCK3,
238 .type = CLK_TYPE_PROGRAMMABLE,
242 static void __init at91rm9200_register_clocks(void)
246 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
247 clk_register(periph_clocks[i]);
249 clkdev_add_table(periph_clocks_lookups,
250 ARRAY_SIZE(periph_clocks_lookups));
251 clkdev_add_table(usart_clocks_lookups,
252 ARRAY_SIZE(usart_clocks_lookups));
260 static struct clk_lookup console_clock_lookup;
262 void __init at91rm9200_set_console_clock(int id)
264 if (id >= ARRAY_SIZE(usart_clocks_lookups))
267 console_clock_lookup.con_id = "usart";
268 console_clock_lookup.clk = usart_clocks_lookups[id].clk;
269 clkdev_add(&console_clock_lookup);
272 /* --------------------------------------------------------------------
274 * -------------------------------------------------------------------- */
276 static struct at91_gpio_bank at91rm9200_gpio[] __initdata = {
278 .id = AT91RM9200_ID_PIOA,
279 .regbase = AT91RM9200_BASE_PIOA,
281 .id = AT91RM9200_ID_PIOB,
282 .regbase = AT91RM9200_BASE_PIOB,
284 .id = AT91RM9200_ID_PIOC,
285 .regbase = AT91RM9200_BASE_PIOC,
287 .id = AT91RM9200_ID_PIOD,
288 .regbase = AT91RM9200_BASE_PIOD,
292 static void at91rm9200_idle(void)
295 * Disable the processor clock. The processor will be automatically
296 * re-enabled by an interrupt or by a reset.
298 at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
301 static void at91rm9200_restart(char mode, const char *cmd)
304 * Perform a hardware reset with the use of the Watchdog timer.
306 at91_st_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
307 at91_st_write(AT91_ST_CR, AT91_ST_WDRST);
310 /* --------------------------------------------------------------------
311 * AT91RM9200 processor initialization
312 * -------------------------------------------------------------------- */
313 static void __init at91rm9200_map_io(void)
315 /* Map peripherals */
316 at91_init_sram(0, AT91RM9200_SRAM_BASE, AT91RM9200_SRAM_SIZE);
317 iotable_init(at91rm9200_io_desc, ARRAY_SIZE(at91rm9200_io_desc));
320 static void __init at91rm9200_ioremap_registers(void)
322 at91rm9200_ioremap_st(AT91RM9200_BASE_ST);
325 static void __init at91rm9200_initialize(void)
327 arm_pm_idle = at91rm9200_idle;
328 arm_pm_restart = at91rm9200_restart;
329 at91_extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1)
330 | (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3)
331 | (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5)
332 | (1 << AT91RM9200_ID_IRQ6);
334 /* Initialize GPIO subsystem */
335 at91_gpio_init(at91rm9200_gpio,
336 cpu_is_at91rm9200_bga() ? AT91RM9200_BGA : AT91RM9200_PQFP);
340 /* --------------------------------------------------------------------
341 * Interrupt initialization
342 * -------------------------------------------------------------------- */
345 * The default interrupt priority levels (0 = lowest, 7 = highest).
347 static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
348 7, /* Advanced Interrupt Controller (FIQ) */
349 7, /* System Peripherals */
350 1, /* Parallel IO Controller A */
351 1, /* Parallel IO Controller B */
352 1, /* Parallel IO Controller C */
353 1, /* Parallel IO Controller D */
358 0, /* Multimedia Card Interface */
359 2, /* USB Device Port */
360 6, /* Two-Wire Interface */
361 5, /* Serial Peripheral Interface */
362 4, /* Serial Synchronous Controller 0 */
363 4, /* Serial Synchronous Controller 1 */
364 4, /* Serial Synchronous Controller 2 */
365 0, /* Timer Counter 0 */
366 0, /* Timer Counter 1 */
367 0, /* Timer Counter 2 */
368 0, /* Timer Counter 3 */
369 0, /* Timer Counter 4 */
370 0, /* Timer Counter 5 */
371 2, /* USB Host port */
372 3, /* Ethernet MAC */
373 0, /* Advanced Interrupt Controller (IRQ0) */
374 0, /* Advanced Interrupt Controller (IRQ1) */
375 0, /* Advanced Interrupt Controller (IRQ2) */
376 0, /* Advanced Interrupt Controller (IRQ3) */
377 0, /* Advanced Interrupt Controller (IRQ4) */
378 0, /* Advanced Interrupt Controller (IRQ5) */
379 0 /* Advanced Interrupt Controller (IRQ6) */
382 struct at91_init_soc __initdata at91rm9200_soc = {
383 .map_io = at91rm9200_map_io,
384 .default_irq_priority = at91rm9200_default_irq_priority,
385 .ioremap_registers = at91rm9200_ioremap_registers,
386 .register_clocks = at91rm9200_register_clocks,
387 .init = at91rm9200_initialize,