arch/arm/mach-at91/at91rm9200.c

   1 /*
   2  * arch/arm/mach-at91/at91rm9200.c
   3  *
   4  *  Copyright (C) 2005 SAN People
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  */
  12
  13 #include <linux/module.h>
  14
  15 #include <asm/irq.h>
  16 #include <asm/mach/arch.h>
  17 #include <asm/mach/map.h>
  18 #include <asm/system_misc.h>
  19 #include <mach/at91rm9200.h>
  20 #include <mach/at91_pmc.h>
  21 #include <mach/at91_st.h>
  22 #include <mach/cpu.h>
  23
  24 #include "soc.h"
  25 #include "generic.h"
  26 #include "clock.h"
  27 #include "sam9_smc.h"
  28
  29 /* --------------------------------------------------------------------
  30  *  Clocks
  31  * -------------------------------------------------------------------- */
  32
  33 /*
  34  * The peripheral clocks.
  35  */
  36 static struct clk udc_clk = {
  37         .name           = "udc_clk",
  38         .pmc_mask       = 1 << AT91RM9200_ID_UDP,
  39         .type           = CLK_TYPE_PERIPHERAL,
  40 };
  41 static struct clk ohci_clk = {
  42         .name           = "ohci_clk",
  43         .pmc_mask       = 1 << AT91RM9200_ID_UHP,
  44         .type           = CLK_TYPE_PERIPHERAL,
  45 };
  46 static struct clk ether_clk = {
  47         .name           = "ether_clk",
  48         .pmc_mask       = 1 << AT91RM9200_ID_EMAC,
  49         .type           = CLK_TYPE_PERIPHERAL,
  50 };
  51 static struct clk mmc_clk = {
  52         .name           = "mci_clk",
  53         .pmc_mask       = 1 << AT91RM9200_ID_MCI,
  54         .type           = CLK_TYPE_PERIPHERAL,
  55 };
  56 static struct clk twi_clk = {
  57         .name           = "twi_clk",
  58         .pmc_mask       = 1 << AT91RM9200_ID_TWI,
  59         .type           = CLK_TYPE_PERIPHERAL,
  60 };
  61 static struct clk usart0_clk = {
  62         .name           = "usart0_clk",
  63         .pmc_mask       = 1 << AT91RM9200_ID_US0,
  64         .type           = CLK_TYPE_PERIPHERAL,
  65 };
  66 static struct clk usart1_clk = {
  67         .name           = "usart1_clk",
  68         .pmc_mask       = 1 << AT91RM9200_ID_US1,
  69         .type           = CLK_TYPE_PERIPHERAL,
  70 };
  71 static struct clk usart2_clk = {
  72         .name           = "usart2_clk",
  73         .pmc_mask       = 1 << AT91RM9200_ID_US2,
  74         .type           = CLK_TYPE_PERIPHERAL,
  75 };
  76 static struct clk usart3_clk = {
  77         .name           = "usart3_clk",
  78         .pmc_mask       = 1 << AT91RM9200_ID_US3,
  79         .type           = CLK_TYPE_PERIPHERAL,
  80 };
  81 static struct clk spi_clk = {
  82         .name           = "spi_clk",
  83         .pmc_mask       = 1 << AT91RM9200_ID_SPI,
  84         .type           = CLK_TYPE_PERIPHERAL,
  85 };
  86 static struct clk pioA_clk = {
  87         .name           = "pioA_clk",
  88         .pmc_mask       = 1 << AT91RM9200_ID_PIOA,
  89         .type           = CLK_TYPE_PERIPHERAL,
  90 };
  91 static struct clk pioB_clk = {
  92         .name           = "pioB_clk",
  93         .pmc_mask       = 1 << AT91RM9200_ID_PIOB,
  94         .type           = CLK_TYPE_PERIPHERAL,
  95 };
  96 static struct clk pioC_clk = {
  97         .name           = "pioC_clk",
  98         .pmc_mask       = 1 << AT91RM9200_ID_PIOC,
  99         .type           = CLK_TYPE_PERIPHERAL,
 100 };
 101 static struct clk pioD_clk = {
 102         .name           = "pioD_clk",
 103         .pmc_mask       = 1 << AT91RM9200_ID_PIOD,
 104         .type           = CLK_TYPE_PERIPHERAL,
 105 };
 106 static struct clk ssc0_clk = {
 107         .name           = "ssc0_clk",
 108         .pmc_mask       = 1 << AT91RM9200_ID_SSC0,
 109         .type           = CLK_TYPE_PERIPHERAL,
 110 };
 111 static struct clk ssc1_clk = {
 112         .name           = "ssc1_clk",
 113         .pmc_mask       = 1 << AT91RM9200_ID_SSC1,
 114         .type           = CLK_TYPE_PERIPHERAL,
 115 };
 116 static struct clk ssc2_clk = {
 117         .name           = "ssc2_clk",
 118         .pmc_mask       = 1 << AT91RM9200_ID_SSC2,
 119         .type           = CLK_TYPE_PERIPHERAL,
 120 };
 121 static struct clk tc0_clk = {
 122         .name           = "tc0_clk",
 123         .pmc_mask       = 1 << AT91RM9200_ID_TC0,
 124         .type           = CLK_TYPE_PERIPHERAL,
 125 };
 126 static struct clk tc1_clk = {
 127         .name           = "tc1_clk",
 128         .pmc_mask       = 1 << AT91RM9200_ID_TC1,
 129         .type           = CLK_TYPE_PERIPHERAL,
 130 };
 131 static struct clk tc2_clk = {
 132         .name           = "tc2_clk",
 133         .pmc_mask       = 1 << AT91RM9200_ID_TC2,
 134         .type           = CLK_TYPE_PERIPHERAL,
 135 };
 136 static struct clk tc3_clk = {
 137         .name           = "tc3_clk",
 138         .pmc_mask       = 1 << AT91RM9200_ID_TC3,
 139         .type           = CLK_TYPE_PERIPHERAL,
 140 };
 141 static struct clk tc4_clk = {
 142         .name           = "tc4_clk",
 143         .pmc_mask       = 1 << AT91RM9200_ID_TC4,
 144         .type           = CLK_TYPE_PERIPHERAL,
 145 };
 146 static struct clk tc5_clk = {
 147         .name           = "tc5_clk",
 148         .pmc_mask       = 1 << AT91RM9200_ID_TC5,
 149         .type           = CLK_TYPE_PERIPHERAL,
 150 };
 151
 152 static struct clk *periph_clocks[] __initdata = {
 153         &pioA_clk,
 154         &pioB_clk,
 155         &pioC_clk,
 156         &pioD_clk,
 157         &usart0_clk,
 158         &usart1_clk,
 159         &usart2_clk,
 160         &usart3_clk,
 161         &mmc_clk,
 162         &udc_clk,
 163         &twi_clk,
 164         &spi_clk,
 165         &ssc0_clk,
 166         &ssc1_clk,
 167         &ssc2_clk,
 168         &tc0_clk,
 169         &tc1_clk,
 170         &tc2_clk,
 171         &tc3_clk,
 172         &tc4_clk,
 173         &tc5_clk,
 174         &ohci_clk,
 175         &ether_clk,
 176         // irq0 .. irq6
 177 };
 178
 179 static struct clk_lookup periph_clocks_lookups[] = {
 180         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
 181         CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
 182         CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
 183         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
 184         CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
 185         CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
 186         CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
 187         CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
 188         CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
 189         /* fake hclk clock */
 190         CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
 191         CLKDEV_CON_ID("pioA", &pioA_clk),
 192         CLKDEV_CON_ID("pioB", &pioB_clk),
 193         CLKDEV_CON_ID("pioC", &pioC_clk),
 194         CLKDEV_CON_ID("pioD", &pioD_clk),
 195 };
 196
 197 static struct clk_lookup usart_clocks_lookups[] = {
 198         CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
 199         CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
 200         CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
 201         CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
 202         CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
 203 };
 204
 205 /*
 206  * The four programmable clocks.
 207  * You must configure pin multiplexing to bring these signals out.
 208  */
 209 static struct clk pck0 = {
 210         .name           = "pck0",
 211         .pmc_mask       = AT91_PMC_PCK0,
 212         .type           = CLK_TYPE_PROGRAMMABLE,
 213         .id             = 0,
 214 };
 215 static struct clk pck1 = {
 216         .name           = "pck1",
 217         .pmc_mask       = AT91_PMC_PCK1,
 218         .type           = CLK_TYPE_PROGRAMMABLE,
 219         .id             = 1,
 220 };
 221 static struct clk pck2 = {
 222         .name           = "pck2",
 223         .pmc_mask       = AT91_PMC_PCK2,
 224         .type           = CLK_TYPE_PROGRAMMABLE,
 225         .id             = 2,
 226 };
 227 static struct clk pck3 = {
 228         .name           = "pck3",
 229         .pmc_mask       = AT91_PMC_PCK3,
 230         .type           = CLK_TYPE_PROGRAMMABLE,
 231         .id             = 3,
 232 };
 233
 234 static void __init at91rm9200_register_clocks(void)
 235 {
 236         int i;
 237
 238         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
 239                 clk_register(periph_clocks[i]);
 240
 241         clkdev_add_table(periph_clocks_lookups,
 242                          ARRAY_SIZE(periph_clocks_lookups));
 243         clkdev_add_table(usart_clocks_lookups,
 244                          ARRAY_SIZE(usart_clocks_lookups));
 245
 246         clk_register(&pck0);
 247         clk_register(&pck1);
 248         clk_register(&pck2);
 249         clk_register(&pck3);
 250 }
 251
 252 /* --------------------------------------------------------------------
 253  *  GPIO
 254  * -------------------------------------------------------------------- */
 255
 256 static struct at91_gpio_bank at91rm9200_gpio[] __initdata = {
 257         {
 258                 .id             = AT91RM9200_ID_PIOA,
 259                 .regbase        = AT91RM9200_BASE_PIOA,
 260         }, {
 261                 .id             = AT91RM9200_ID_PIOB,
 262                 .regbase        = AT91RM9200_BASE_PIOB,
 263         }, {
 264                 .id             = AT91RM9200_ID_PIOC,
 265                 .regbase        = AT91RM9200_BASE_PIOC,
 266         }, {
 267                 .id             = AT91RM9200_ID_PIOD,
 268                 .regbase        = AT91RM9200_BASE_PIOD,
 269         }
 270 };
 271
 272 static void at91rm9200_idle(void)
 273 {
 274         /*
 275          * Disable the processor clock.  The processor will be automatically
 276          * re-enabled by an interrupt or by a reset.
 277          */
 278         at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
 279 }
 280
 281 static void at91rm9200_restart(char mode, const char *cmd)
 282 {
 283         /*
 284          * Perform a hardware reset with the use of the Watchdog timer.
 285          */
 286         at91_st_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
 287         at91_st_write(AT91_ST_CR, AT91_ST_WDRST);
 288 }
 289
 290 /* --------------------------------------------------------------------
 291  *  AT91RM9200 processor initialization
 292  * -------------------------------------------------------------------- */
 293 static void __init at91rm9200_map_io(void)
 294 {
 295         /* Map peripherals */
 296         at91_init_sram(0, AT91RM9200_SRAM_BASE, AT91RM9200_SRAM_SIZE);
 297 }
 298
 299 static void __init at91rm9200_ioremap_registers(void)
 300 {
 301         at91rm9200_ioremap_st(AT91RM9200_BASE_ST);
 302         at91_ioremap_ramc(0, AT91RM9200_BASE_MC, 256);
 303 }
 304
 305 static void __init at91rm9200_initialize(void)
 306 {
 307         arm_pm_idle = at91rm9200_idle;
 308         arm_pm_restart = at91rm9200_restart;
 309         at91_extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1)
 310                         | (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3)
 311                         | (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5)
 312                         | (1 << AT91RM9200_ID_IRQ6);
 313
 314         /* Initialize GPIO subsystem */
 315         at91_gpio_init(at91rm9200_gpio,
 316                 cpu_is_at91rm9200_bga() ? AT91RM9200_BGA : AT91RM9200_PQFP);
 317 }
 318
 319
 320 /* --------------------------------------------------------------------
 321  *  Interrupt initialization
 322  * -------------------------------------------------------------------- */
 323
 324 /*
 325  * The default interrupt priority levels (0 = lowest, 7 = highest).
 326  */
 327 static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
 328         7,      /* Advanced Interrupt Controller (FIQ) */
 329         7,      /* System Peripherals */
 330         1,      /* Parallel IO Controller A */
 331         1,      /* Parallel IO Controller B */
 332         1,      /* Parallel IO Controller C */
 333         1,      /* Parallel IO Controller D */
 334         5,      /* USART 0 */
 335         5,      /* USART 1 */
 336         5,      /* USART 2 */
 337         5,      /* USART 3 */
 338         0,      /* Multimedia Card Interface */
 339         2,      /* USB Device Port */
 340         6,      /* Two-Wire Interface */
 341         5,      /* Serial Peripheral Interface */
 342         4,      /* Serial Synchronous Controller 0 */
 343         4,      /* Serial Synchronous Controller 1 */
 344         4,      /* Serial Synchronous Controller 2 */
 345         0,      /* Timer Counter 0 */
 346         0,      /* Timer Counter 1 */
 347         0,      /* Timer Counter 2 */
 348         0,      /* Timer Counter 3 */
 349         0,      /* Timer Counter 4 */
 350         0,      /* Timer Counter 5 */
 351         2,      /* USB Host port */
 352         3,      /* Ethernet MAC */
 353         0,      /* Advanced Interrupt Controller (IRQ0) */
 354         0,      /* Advanced Interrupt Controller (IRQ1) */
 355         0,      /* Advanced Interrupt Controller (IRQ2) */
 356         0,      /* Advanced Interrupt Controller (IRQ3) */
 357         0,      /* Advanced Interrupt Controller (IRQ4) */
 358         0,      /* Advanced Interrupt Controller (IRQ5) */
 359         0       /* Advanced Interrupt Controller (IRQ6) */
 360 };
 361
 362 struct at91_init_soc __initdata at91rm9200_soc = {
 363         .map_io = at91rm9200_map_io,
 364         .default_irq_priority = at91rm9200_default_irq_priority,
 365         .ioremap_registers = at91rm9200_ioremap_registers,
 366         .register_clocks = at91rm9200_register_clocks,
 367         .init = at91rm9200_initialize,
 368 };