2 * arch/arm/mach-at91/at91cap9.c
4 * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
5 * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
6 * Copyright (C) 2007 Atmel Corporation.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
15 #include <linux/module.h>
19 #include <asm/mach/arch.h>
20 #include <asm/mach/map.h>
23 #include <mach/at91cap9.h>
24 #include <mach/at91_pmc.h>
25 #include <mach/at91_rstc.h>
26 #include <mach/at91_shdwc.h>
32 static struct map_desc at91cap9_sram_desc[] __initdata = {
34 .virtual = AT91_IO_VIRT_BASE - AT91CAP9_SRAM_SIZE,
35 .pfn = __phys_to_pfn(AT91CAP9_SRAM_BASE),
36 .length = AT91CAP9_SRAM_SIZE,
41 /* --------------------------------------------------------------------
43 * -------------------------------------------------------------------- */
46 * The peripheral clocks.
48 static struct clk pioABCD_clk = {
49 .name = "pioABCD_clk",
50 .pmc_mask = 1 << AT91CAP9_ID_PIOABCD,
51 .type = CLK_TYPE_PERIPHERAL,
53 static struct clk mpb0_clk = {
55 .pmc_mask = 1 << AT91CAP9_ID_MPB0,
56 .type = CLK_TYPE_PERIPHERAL,
58 static struct clk mpb1_clk = {
60 .pmc_mask = 1 << AT91CAP9_ID_MPB1,
61 .type = CLK_TYPE_PERIPHERAL,
63 static struct clk mpb2_clk = {
65 .pmc_mask = 1 << AT91CAP9_ID_MPB2,
66 .type = CLK_TYPE_PERIPHERAL,
68 static struct clk mpb3_clk = {
70 .pmc_mask = 1 << AT91CAP9_ID_MPB3,
71 .type = CLK_TYPE_PERIPHERAL,
73 static struct clk mpb4_clk = {
75 .pmc_mask = 1 << AT91CAP9_ID_MPB4,
76 .type = CLK_TYPE_PERIPHERAL,
78 static struct clk usart0_clk = {
80 .pmc_mask = 1 << AT91CAP9_ID_US0,
81 .type = CLK_TYPE_PERIPHERAL,
83 static struct clk usart1_clk = {
85 .pmc_mask = 1 << AT91CAP9_ID_US1,
86 .type = CLK_TYPE_PERIPHERAL,
88 static struct clk usart2_clk = {
90 .pmc_mask = 1 << AT91CAP9_ID_US2,
91 .type = CLK_TYPE_PERIPHERAL,
93 static struct clk mmc0_clk = {
95 .pmc_mask = 1 << AT91CAP9_ID_MCI0,
96 .type = CLK_TYPE_PERIPHERAL,
98 static struct clk mmc1_clk = {
100 .pmc_mask = 1 << AT91CAP9_ID_MCI1,
101 .type = CLK_TYPE_PERIPHERAL,
103 static struct clk can_clk = {
105 .pmc_mask = 1 << AT91CAP9_ID_CAN,
106 .type = CLK_TYPE_PERIPHERAL,
108 static struct clk twi_clk = {
110 .pmc_mask = 1 << AT91CAP9_ID_TWI,
111 .type = CLK_TYPE_PERIPHERAL,
113 static struct clk spi0_clk = {
115 .pmc_mask = 1 << AT91CAP9_ID_SPI0,
116 .type = CLK_TYPE_PERIPHERAL,
118 static struct clk spi1_clk = {
120 .pmc_mask = 1 << AT91CAP9_ID_SPI1,
121 .type = CLK_TYPE_PERIPHERAL,
123 static struct clk ssc0_clk = {
125 .pmc_mask = 1 << AT91CAP9_ID_SSC0,
126 .type = CLK_TYPE_PERIPHERAL,
128 static struct clk ssc1_clk = {
130 .pmc_mask = 1 << AT91CAP9_ID_SSC1,
131 .type = CLK_TYPE_PERIPHERAL,
133 static struct clk ac97_clk = {
135 .pmc_mask = 1 << AT91CAP9_ID_AC97C,
136 .type = CLK_TYPE_PERIPHERAL,
138 static struct clk tcb_clk = {
140 .pmc_mask = 1 << AT91CAP9_ID_TCB,
141 .type = CLK_TYPE_PERIPHERAL,
143 static struct clk pwm_clk = {
145 .pmc_mask = 1 << AT91CAP9_ID_PWMC,
146 .type = CLK_TYPE_PERIPHERAL,
148 static struct clk macb_clk = {
150 .pmc_mask = 1 << AT91CAP9_ID_EMAC,
151 .type = CLK_TYPE_PERIPHERAL,
153 static struct clk aestdes_clk = {
154 .name = "aestdes_clk",
155 .pmc_mask = 1 << AT91CAP9_ID_AESTDES,
156 .type = CLK_TYPE_PERIPHERAL,
158 static struct clk adc_clk = {
160 .pmc_mask = 1 << AT91CAP9_ID_ADC,
161 .type = CLK_TYPE_PERIPHERAL,
163 static struct clk isi_clk = {
165 .pmc_mask = 1 << AT91CAP9_ID_ISI,
166 .type = CLK_TYPE_PERIPHERAL,
168 static struct clk lcdc_clk = {
170 .pmc_mask = 1 << AT91CAP9_ID_LCDC,
171 .type = CLK_TYPE_PERIPHERAL,
173 static struct clk dma_clk = {
175 .pmc_mask = 1 << AT91CAP9_ID_DMA,
176 .type = CLK_TYPE_PERIPHERAL,
178 static struct clk udphs_clk = {
180 .pmc_mask = 1 << AT91CAP9_ID_UDPHS,
181 .type = CLK_TYPE_PERIPHERAL,
183 static struct clk ohci_clk = {
185 .pmc_mask = 1 << AT91CAP9_ID_UHP,
186 .type = CLK_TYPE_PERIPHERAL,
189 static struct clk *periph_clocks[] __initdata = {
221 static struct clk_lookup periph_clocks_lookups[] = {
222 CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
223 CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
224 CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk),
225 CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.1", &mmc1_clk),
226 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
227 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
228 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
229 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
230 CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
233 static struct clk_lookup usart_clocks_lookups[] = {
234 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
235 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
236 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
237 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
241 * The four programmable clocks.
242 * You must configure pin multiplexing to bring these signals out.
244 static struct clk pck0 = {
246 .pmc_mask = AT91_PMC_PCK0,
247 .type = CLK_TYPE_PROGRAMMABLE,
250 static struct clk pck1 = {
252 .pmc_mask = AT91_PMC_PCK1,
253 .type = CLK_TYPE_PROGRAMMABLE,
256 static struct clk pck2 = {
258 .pmc_mask = AT91_PMC_PCK2,
259 .type = CLK_TYPE_PROGRAMMABLE,
262 static struct clk pck3 = {
264 .pmc_mask = AT91_PMC_PCK3,
265 .type = CLK_TYPE_PROGRAMMABLE,
269 static void __init at91cap9_register_clocks(void)
273 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
274 clk_register(periph_clocks[i]);
276 clkdev_add_table(periph_clocks_lookups,
277 ARRAY_SIZE(periph_clocks_lookups));
278 clkdev_add_table(usart_clocks_lookups,
279 ARRAY_SIZE(usart_clocks_lookups));
287 static struct clk_lookup console_clock_lookup;
289 void __init at91cap9_set_console_clock(int id)
291 if (id >= ARRAY_SIZE(usart_clocks_lookups))
294 console_clock_lookup.con_id = "usart";
295 console_clock_lookup.clk = usart_clocks_lookups[id].clk;
296 clkdev_add(&console_clock_lookup);
299 /* --------------------------------------------------------------------
301 * -------------------------------------------------------------------- */
303 static struct at91_gpio_bank at91cap9_gpio[] = {
305 .id = AT91CAP9_ID_PIOABCD,
307 .clock = &pioABCD_clk,
309 .id = AT91CAP9_ID_PIOABCD,
311 .clock = &pioABCD_clk,
313 .id = AT91CAP9_ID_PIOABCD,
315 .clock = &pioABCD_clk,
317 .id = AT91CAP9_ID_PIOABCD,
319 .clock = &pioABCD_clk,
323 static void at91cap9_reset(void)
325 at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
328 static void at91cap9_poweroff(void)
330 at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
334 /* --------------------------------------------------------------------
335 * AT91CAP9 processor initialization
336 * -------------------------------------------------------------------- */
338 static void __init at91cap9_map_io(void)
340 iotable_init(at91cap9_sram_desc, ARRAY_SIZE(at91cap9_sram_desc));
343 static void __init at91cap9_initialize(unsigned long main_clock)
344 at91_arch_reset = at91cap9_reset;
345 pm_power_off = at91cap9_poweroff;
346 at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);
348 /* Init clock subsystem */
349 at91_clock_init(main_clock);
351 /* Register the processor-specific clocks */
352 at91cap9_register_clocks();
354 /* Register GPIO subsystem */
355 at91_gpio_init(at91cap9_gpio, 4);
357 /* Remember the silicon revision */
358 if (cpu_is_at91cap9_revB())
360 else if (cpu_is_at91cap9_revC())
364 /* --------------------------------------------------------------------
365 * Interrupt initialization
366 * -------------------------------------------------------------------- */
369 * The default interrupt priority levels (0 = lowest, 7 = highest).
371 static unsigned int at91cap9_default_irq_priority[NR_AIC_IRQS] __initdata = {
372 7, /* Advanced Interrupt Controller (FIQ) */
373 7, /* System Peripherals */
374 1, /* Parallel IO Controller A, B, C and D */
375 0, /* MP Block Peripheral 0 */
376 0, /* MP Block Peripheral 1 */
377 0, /* MP Block Peripheral 2 */
378 0, /* MP Block Peripheral 3 */
379 0, /* MP Block Peripheral 4 */
383 0, /* Multimedia Card Interface 0 */
384 0, /* Multimedia Card Interface 1 */
386 6, /* Two-Wire Interface */
387 5, /* Serial Peripheral Interface 0 */
388 5, /* Serial Peripheral Interface 1 */
389 4, /* Serial Synchronous Controller 0 */
390 4, /* Serial Synchronous Controller 1 */
391 5, /* AC97 Controller */
392 0, /* Timer Counter 0, 1 and 2 */
393 0, /* Pulse Width Modulation Controller */
395 0, /* Advanced Encryption Standard, Triple DES*/
396 0, /* Analog-to-Digital Converter */
397 0, /* Image Sensor Interface */
398 3, /* LCD Controller */
399 0, /* DMA Controller */
400 2, /* USB Device Port */
401 2, /* USB Host port */
402 0, /* Advanced Interrupt Controller (IRQ0) */
403 0, /* Advanced Interrupt Controller (IRQ1) */
406 struct at91_init_soc __initdata at91cap9_soc = {
407 .map_io = at91cap9_map_io,
408 .default_irq_priority = at91cap9_default_irq_priority,
409 .init = at91cap9_initialize,