2 * arch/arm/mach-at91/at91cap9.c
4 * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
5 * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
6 * Copyright (C) 2007 Atmel Corporation.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
15 #include <linux/module.h>
19 #include <asm/mach/arch.h>
20 #include <asm/mach/map.h>
23 #include <mach/at91cap9.h>
24 #include <mach/at91_pmc.h>
25 #include <mach/at91_rstc.h>
26 #include <mach/at91_shdwc.h>
32 /* --------------------------------------------------------------------
34 * -------------------------------------------------------------------- */
37 * The peripheral clocks.
39 static struct clk pioABCD_clk = {
40 .name = "pioABCD_clk",
41 .pmc_mask = 1 << AT91CAP9_ID_PIOABCD,
42 .type = CLK_TYPE_PERIPHERAL,
44 static struct clk mpb0_clk = {
46 .pmc_mask = 1 << AT91CAP9_ID_MPB0,
47 .type = CLK_TYPE_PERIPHERAL,
49 static struct clk mpb1_clk = {
51 .pmc_mask = 1 << AT91CAP9_ID_MPB1,
52 .type = CLK_TYPE_PERIPHERAL,
54 static struct clk mpb2_clk = {
56 .pmc_mask = 1 << AT91CAP9_ID_MPB2,
57 .type = CLK_TYPE_PERIPHERAL,
59 static struct clk mpb3_clk = {
61 .pmc_mask = 1 << AT91CAP9_ID_MPB3,
62 .type = CLK_TYPE_PERIPHERAL,
64 static struct clk mpb4_clk = {
66 .pmc_mask = 1 << AT91CAP9_ID_MPB4,
67 .type = CLK_TYPE_PERIPHERAL,
69 static struct clk usart0_clk = {
71 .pmc_mask = 1 << AT91CAP9_ID_US0,
72 .type = CLK_TYPE_PERIPHERAL,
74 static struct clk usart1_clk = {
76 .pmc_mask = 1 << AT91CAP9_ID_US1,
77 .type = CLK_TYPE_PERIPHERAL,
79 static struct clk usart2_clk = {
81 .pmc_mask = 1 << AT91CAP9_ID_US2,
82 .type = CLK_TYPE_PERIPHERAL,
84 static struct clk mmc0_clk = {
86 .pmc_mask = 1 << AT91CAP9_ID_MCI0,
87 .type = CLK_TYPE_PERIPHERAL,
89 static struct clk mmc1_clk = {
91 .pmc_mask = 1 << AT91CAP9_ID_MCI1,
92 .type = CLK_TYPE_PERIPHERAL,
94 static struct clk can_clk = {
96 .pmc_mask = 1 << AT91CAP9_ID_CAN,
97 .type = CLK_TYPE_PERIPHERAL,
99 static struct clk twi_clk = {
101 .pmc_mask = 1 << AT91CAP9_ID_TWI,
102 .type = CLK_TYPE_PERIPHERAL,
104 static struct clk spi0_clk = {
106 .pmc_mask = 1 << AT91CAP9_ID_SPI0,
107 .type = CLK_TYPE_PERIPHERAL,
109 static struct clk spi1_clk = {
111 .pmc_mask = 1 << AT91CAP9_ID_SPI1,
112 .type = CLK_TYPE_PERIPHERAL,
114 static struct clk ssc0_clk = {
116 .pmc_mask = 1 << AT91CAP9_ID_SSC0,
117 .type = CLK_TYPE_PERIPHERAL,
119 static struct clk ssc1_clk = {
121 .pmc_mask = 1 << AT91CAP9_ID_SSC1,
122 .type = CLK_TYPE_PERIPHERAL,
124 static struct clk ac97_clk = {
126 .pmc_mask = 1 << AT91CAP9_ID_AC97C,
127 .type = CLK_TYPE_PERIPHERAL,
129 static struct clk tcb_clk = {
131 .pmc_mask = 1 << AT91CAP9_ID_TCB,
132 .type = CLK_TYPE_PERIPHERAL,
134 static struct clk pwm_clk = {
136 .pmc_mask = 1 << AT91CAP9_ID_PWMC,
137 .type = CLK_TYPE_PERIPHERAL,
139 static struct clk macb_clk = {
141 .pmc_mask = 1 << AT91CAP9_ID_EMAC,
142 .type = CLK_TYPE_PERIPHERAL,
144 static struct clk aestdes_clk = {
145 .name = "aestdes_clk",
146 .pmc_mask = 1 << AT91CAP9_ID_AESTDES,
147 .type = CLK_TYPE_PERIPHERAL,
149 static struct clk adc_clk = {
151 .pmc_mask = 1 << AT91CAP9_ID_ADC,
152 .type = CLK_TYPE_PERIPHERAL,
154 static struct clk isi_clk = {
156 .pmc_mask = 1 << AT91CAP9_ID_ISI,
157 .type = CLK_TYPE_PERIPHERAL,
159 static struct clk lcdc_clk = {
161 .pmc_mask = 1 << AT91CAP9_ID_LCDC,
162 .type = CLK_TYPE_PERIPHERAL,
164 static struct clk dma_clk = {
166 .pmc_mask = 1 << AT91CAP9_ID_DMA,
167 .type = CLK_TYPE_PERIPHERAL,
169 static struct clk udphs_clk = {
171 .pmc_mask = 1 << AT91CAP9_ID_UDPHS,
172 .type = CLK_TYPE_PERIPHERAL,
174 static struct clk ohci_clk = {
176 .pmc_mask = 1 << AT91CAP9_ID_UHP,
177 .type = CLK_TYPE_PERIPHERAL,
180 static struct clk *periph_clocks[] __initdata = {
212 static struct clk_lookup periph_clocks_lookups[] = {
213 CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
214 CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
215 CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk),
216 CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.1", &mmc1_clk),
217 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
218 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
219 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
220 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
221 CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
222 /* fake hclk clock */
223 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
226 static struct clk_lookup usart_clocks_lookups[] = {
227 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
228 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
229 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
230 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
234 * The four programmable clocks.
235 * You must configure pin multiplexing to bring these signals out.
237 static struct clk pck0 = {
239 .pmc_mask = AT91_PMC_PCK0,
240 .type = CLK_TYPE_PROGRAMMABLE,
243 static struct clk pck1 = {
245 .pmc_mask = AT91_PMC_PCK1,
246 .type = CLK_TYPE_PROGRAMMABLE,
249 static struct clk pck2 = {
251 .pmc_mask = AT91_PMC_PCK2,
252 .type = CLK_TYPE_PROGRAMMABLE,
255 static struct clk pck3 = {
257 .pmc_mask = AT91_PMC_PCK3,
258 .type = CLK_TYPE_PROGRAMMABLE,
262 static void __init at91cap9_register_clocks(void)
266 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
267 clk_register(periph_clocks[i]);
269 clkdev_add_table(periph_clocks_lookups,
270 ARRAY_SIZE(periph_clocks_lookups));
271 clkdev_add_table(usart_clocks_lookups,
272 ARRAY_SIZE(usart_clocks_lookups));
280 static struct clk_lookup console_clock_lookup;
282 void __init at91cap9_set_console_clock(int id)
284 if (id >= ARRAY_SIZE(usart_clocks_lookups))
287 console_clock_lookup.con_id = "usart";
288 console_clock_lookup.clk = usart_clocks_lookups[id].clk;
289 clkdev_add(&console_clock_lookup);
292 /* --------------------------------------------------------------------
294 * -------------------------------------------------------------------- */
296 static struct at91_gpio_bank at91cap9_gpio[] = {
298 .id = AT91CAP9_ID_PIOABCD,
300 .clock = &pioABCD_clk,
302 .id = AT91CAP9_ID_PIOABCD,
304 .clock = &pioABCD_clk,
306 .id = AT91CAP9_ID_PIOABCD,
308 .clock = &pioABCD_clk,
310 .id = AT91CAP9_ID_PIOABCD,
312 .clock = &pioABCD_clk,
316 static void at91cap9_reset(void)
318 at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
321 static void at91cap9_poweroff(void)
323 at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
327 /* --------------------------------------------------------------------
328 * AT91CAP9 processor initialization
329 * -------------------------------------------------------------------- */
331 static void __init at91cap9_map_io(void)
333 at91_init_sram(0, AT91CAP9_SRAM_BASE, AT91CAP9_SRAM_SIZE);
336 static void __init at91cap9_initialize(void)
338 at91_arch_reset = at91cap9_reset;
339 pm_power_off = at91cap9_poweroff;
340 at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);
342 /* Register GPIO subsystem */
343 at91_gpio_init(at91cap9_gpio, 4);
345 /* Remember the silicon revision */
346 if (cpu_is_at91cap9_revB())
348 else if (cpu_is_at91cap9_revC())
352 /* --------------------------------------------------------------------
353 * Interrupt initialization
354 * -------------------------------------------------------------------- */
357 * The default interrupt priority levels (0 = lowest, 7 = highest).
359 static unsigned int at91cap9_default_irq_priority[NR_AIC_IRQS] __initdata = {
360 7, /* Advanced Interrupt Controller (FIQ) */
361 7, /* System Peripherals */
362 1, /* Parallel IO Controller A, B, C and D */
363 0, /* MP Block Peripheral 0 */
364 0, /* MP Block Peripheral 1 */
365 0, /* MP Block Peripheral 2 */
366 0, /* MP Block Peripheral 3 */
367 0, /* MP Block Peripheral 4 */
371 0, /* Multimedia Card Interface 0 */
372 0, /* Multimedia Card Interface 1 */
374 6, /* Two-Wire Interface */
375 5, /* Serial Peripheral Interface 0 */
376 5, /* Serial Peripheral Interface 1 */
377 4, /* Serial Synchronous Controller 0 */
378 4, /* Serial Synchronous Controller 1 */
379 5, /* AC97 Controller */
380 0, /* Timer Counter 0, 1 and 2 */
381 0, /* Pulse Width Modulation Controller */
383 0, /* Advanced Encryption Standard, Triple DES*/
384 0, /* Analog-to-Digital Converter */
385 0, /* Image Sensor Interface */
386 3, /* LCD Controller */
387 0, /* DMA Controller */
388 2, /* USB Device Port */
389 2, /* USB Host port */
390 0, /* Advanced Interrupt Controller (IRQ0) */
391 0, /* Advanced Interrupt Controller (IRQ1) */
394 struct at91_init_soc __initdata at91cap9_soc = {
395 .map_io = at91cap9_map_io,
396 .default_irq_priority = at91cap9_default_irq_priority,
397 .register_clocks = at91cap9_register_clocks,
398 .init = at91cap9_initialize,