arch/arm/lib/copy_page.S

   1 /*
   2  *  linux/arch/arm/lib/copypage.S
   3  *
   4  *  Copyright (C) 1995-1999 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  *  ASM optimised string functions
  11  */
  12 #include <linux/linkage.h>
  13 #include <asm/assembler.h>
  14 #include <asm/asm-offsets.h>
  15
  16 #define COPY_COUNT (PAGE_SZ/64 PLD( -1 ))
  17
  18                 .text
  19                 .align  5
  20 /*
  21  * StrongARM optimised copy_page routine
  22  * now 1.78bytes/cycle, was 1.60 bytes/cycle (50MHz bus -> 89MB/s)
  23  * Note that we probably achieve closer to the 100MB/s target with
  24  * the core clock switching.
  25  */
  26 ENTRY(copy_page)
  27                 stmfd   sp!, {r4, lr}                   @       2
  28         PLD(    pld     [r1, #0]                )
  29         PLD(    pld     [r1, #32]               )
  30                 mov     r2, #COPY_COUNT                 @       1
  31                 ldmia   r1!, {r3, r4, ip, lr}           @       4+1
  32 1:      PLD(    pld     [r1, #64]               )
  33         PLD(    pld     [r1, #96]               )
  34 2:              stmia   r0!, {r3, r4, ip, lr}           @       4
  35                 ldmia   r1!, {r3, r4, ip, lr}           @       4+1
  36                 stmia   r0!, {r3, r4, ip, lr}           @       4
  37                 ldmia   r1!, {r3, r4, ip, lr}           @       4+1
  38                 stmia   r0!, {r3, r4, ip, lr}           @       4
  39                 ldmia   r1!, {r3, r4, ip, lr}           @       4
  40                 subs    r2, r2, #1                      @       1
  41                 stmia   r0!, {r3, r4, ip, lr}           @       4
  42                 ldmgtia r1!, {r3, r4, ip, lr}           @       4
  43                 bgt     1b                              @       1
  44         PLD(    ldmeqia r1!, {r3, r4, ip, lr}   )
  45         PLD(    beq     2b                      )
  46                 LOADREGS(fd, sp!, {r4, pc})             @       3