1 #include <linux/linkage.h>
2 #include <linux/threads.h>
3 #include <asm/asm-offsets.h>
4 #include <asm/assembler.h>
5 #include <asm/glue-cache.h>
6 #include <asm/glue-proc.h>
7 #include <asm/system.h>
11 * Save CPU state for a suspend
13 * r3 = virtual return function
14 * Note: sp is decremented to allocate space for CPU state on stack
15 * r0-r3,ip,lr corrupted
23 ldr r0, [r10, #CPU_SLEEP_SIZE] @ size of CPU sleep state
24 ldr ip, [r10, #CPU_DO_RESUME] @ virtual resume function
26 ldr r0, =cpu_suspend_size
27 ldr ip, =cpu_do_resume
29 mov r2, sp @ current virtual SP
30 sub sp, sp, r0 @ allocate CPU state on stack
31 mov r0, sp @ save pointer
32 add ip, ip, r1 @ convert resume fn to phys
33 stmfd sp!, {r1, r2, ip} @ save v:p, virt SP, phys resume fn
34 ldr r3, =sleep_save_sp
35 add r2, sp, r1 @ convert SP to phys
37 ALT_SMP(mrc p15, 0, lr, c0, c0, 5)
40 str r2, [r3, lr, lsl #2] @ save phys SP
42 str r2, [r3] @ save phys SP
46 ldr pc, [r10, #CPU_DO_SUSPEND] @ save CPU state
55 ldr pc, [r10, #CACHE_FLUSH_KERN_ALL]
58 b __cpuc_flush_kern_all
64 * r0 = control register value
65 * r1 = v:p offset (preserved by cpu_do_resume)
66 * r2 = phys page table base
67 * r3 = L1 section flags
70 adr r4, cpu_resume_turn_mmu_on
72 orr r3, r3, r4, lsl #20
73 ldr r5, [r2, r4, lsl #2] @ save old mapping
74 str r3, [r2, r4, lsl #2] @ setup 1:1 mapping for mmu code
76 ldr r3, =cpu_resume_after_mmu
77 bic r1, r0, #CR_C @ ensure D-cache is disabled
78 b cpu_resume_turn_mmu_on
79 ENDPROC(cpu_resume_mmu)
82 cpu_resume_turn_mmu_on:
83 mcr p15, 0, r1, c1, c0, 0 @ turn on MMU, I-cache, etc
84 mrc p15, 0, r1, c0, c0, 0 @ read id reg
87 mov pc, r3 @ jump to virtual address
88 ENDPROC(cpu_resume_turn_mmu_on)
90 str r5, [r2, r4, lsl #2] @ restore old mapping
91 mcr p15, 0, r0, c1, c0, 0 @ turn on D-cache
92 ldmfd sp!, {r4 - r11, pc}
93 ENDPROC(cpu_resume_after_mmu)
96 * Note: Yes, part of the following code is located into the .data section.
97 * This is to allow sleep_save_sp to be accessed with a relative load
98 * while we can't rely on any MMU translation. We could have put
99 * sleep_save_sp in the .text section as well, but some setups might
100 * insist on it to be truly read-only.
106 adr r0, sleep_save_sp
107 ALT_SMP(mrc p15, 0, r1, c0, c0, 5)
110 ldr r0, [r0, r1, lsl #2] @ stack phys addr
112 ldr r0, sleep_save_sp @ stack phys addr
114 setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set SVC, irqs off
115 @ load v:p, stack, resume fn
116 ARM( ldmia r0!, {r1, sp, pc} )
117 THUMB( ldmia r0!, {r1, r2, r3} )
124 .long 0 @ preserve stack phys ptr here