4 * ARM performance counter support.
6 * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
7 * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
9 * This code is based on the sparc64 perf event code, which is in turn based
10 * on the x86 code. Callchain code is based on the ARM OProfile backtrace
13 #define pr_fmt(fmt) "hw perfevents: " fmt
15 #include <linux/interrupt.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/perf_event.h>
19 #include <linux/platform_device.h>
20 #include <linux/spinlock.h>
21 #include <linux/uaccess.h>
23 #include <asm/cputype.h>
25 #include <asm/irq_regs.h>
27 #include <asm/stacktrace.h>
30 * ARMv6 supports a maximum of 3 events, starting from index 0. If we add
31 * another platform that supports more, we need to increase this to be the
32 * largest of all platforms.
34 * ARMv7 supports up to 32 events:
35 * cycle counter CCNT + 31 events counters CNT0..30.
36 * Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters.
38 #define ARMPMU_MAX_HWEVENTS 32
40 /* The events for a given CPU. */
41 struct cpu_hw_events {
43 * The events that are active on the CPU for the given index.
45 struct perf_event *events[ARMPMU_MAX_HWEVENTS];
48 * A 1 bit for an index indicates that the counter is being used for
49 * an event. A 0 means that the counter can be used.
51 unsigned long used_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)];
54 * Hardware lock to serialize accesses to PMU registers. Needed for the
55 * read/modify/write sequences.
57 raw_spinlock_t pmu_lock;
59 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
62 enum arm_perf_pmu_ids id;
63 enum arm_pmu_type type;
64 cpumask_t active_irqs;
66 irqreturn_t (*handle_irq)(int irq_num, void *dev);
67 void (*enable)(struct hw_perf_event *evt, int idx);
68 void (*disable)(struct hw_perf_event *evt, int idx);
69 int (*get_event_idx)(struct cpu_hw_events *cpuc,
70 struct hw_perf_event *hwc);
71 int (*set_event_filter)(struct hw_perf_event *evt,
72 struct perf_event_attr *attr);
73 u32 (*read_counter)(int idx);
74 void (*write_counter)(int idx, u32 val);
77 void (*reset)(void *);
78 int (*map_event)(struct perf_event *event);
80 atomic_t active_events;
81 struct mutex reserve_mutex;
83 struct platform_device *plat_device;
84 struct cpu_hw_events *(*get_hw_events)(void);
87 /* Set at runtime when we know what CPU type we are. */
88 static struct arm_pmu *armpmu;
91 armpmu_get_pmu_id(void)
100 EXPORT_SYMBOL_GPL(armpmu_get_pmu_id);
103 armpmu_get_max_events(void)
108 max_events = armpmu->num_events;
112 EXPORT_SYMBOL_GPL(armpmu_get_max_events);
114 int perf_num_counters(void)
116 return armpmu_get_max_events();
118 EXPORT_SYMBOL_GPL(perf_num_counters);
120 #define HW_OP_UNSUPPORTED 0xFFFF
123 PERF_COUNT_HW_CACHE_##_x
125 #define CACHE_OP_UNSUPPORTED 0xFFFF
128 armpmu_map_cache_event(const unsigned (*cache_map)
129 [PERF_COUNT_HW_CACHE_MAX]
130 [PERF_COUNT_HW_CACHE_OP_MAX]
131 [PERF_COUNT_HW_CACHE_RESULT_MAX],
134 unsigned int cache_type, cache_op, cache_result, ret;
136 cache_type = (config >> 0) & 0xff;
137 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
140 cache_op = (config >> 8) & 0xff;
141 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
144 cache_result = (config >> 16) & 0xff;
145 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
148 ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
150 if (ret == CACHE_OP_UNSUPPORTED)
157 armpmu_map_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
159 int mapping = (*event_map)[config];
160 return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
164 armpmu_map_raw_event(u32 raw_event_mask, u64 config)
166 return (int)(config & raw_event_mask);
169 static int map_cpu_event(struct perf_event *event,
170 const unsigned (*event_map)[PERF_COUNT_HW_MAX],
171 const unsigned (*cache_map)
172 [PERF_COUNT_HW_CACHE_MAX]
173 [PERF_COUNT_HW_CACHE_OP_MAX]
174 [PERF_COUNT_HW_CACHE_RESULT_MAX],
177 u64 config = event->attr.config;
179 switch (event->attr.type) {
180 case PERF_TYPE_HARDWARE:
181 return armpmu_map_event(event_map, config);
182 case PERF_TYPE_HW_CACHE:
183 return armpmu_map_cache_event(cache_map, config);
185 return armpmu_map_raw_event(raw_event_mask, config);
192 armpmu_event_set_period(struct perf_event *event,
193 struct hw_perf_event *hwc,
196 s64 left = local64_read(&hwc->period_left);
197 s64 period = hwc->sample_period;
200 if (unlikely(left <= -period)) {
202 local64_set(&hwc->period_left, left);
203 hwc->last_period = period;
207 if (unlikely(left <= 0)) {
209 local64_set(&hwc->period_left, left);
210 hwc->last_period = period;
214 if (left > (s64)armpmu->max_period)
215 left = armpmu->max_period;
217 local64_set(&hwc->prev_count, (u64)-left);
219 armpmu->write_counter(idx, (u64)(-left) & 0xffffffff);
221 perf_event_update_userpage(event);
227 armpmu_event_update(struct perf_event *event,
228 struct hw_perf_event *hwc,
229 int idx, int overflow)
231 u64 delta, prev_raw_count, new_raw_count;
234 prev_raw_count = local64_read(&hwc->prev_count);
235 new_raw_count = armpmu->read_counter(idx);
237 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
238 new_raw_count) != prev_raw_count)
241 new_raw_count &= armpmu->max_period;
242 prev_raw_count &= armpmu->max_period;
245 delta = armpmu->max_period - prev_raw_count + new_raw_count + 1;
247 delta = new_raw_count - prev_raw_count;
249 local64_add(delta, &event->count);
250 local64_sub(delta, &hwc->period_left);
252 return new_raw_count;
256 armpmu_read(struct perf_event *event)
258 struct hw_perf_event *hwc = &event->hw;
260 /* Don't read disabled counters! */
264 armpmu_event_update(event, hwc, hwc->idx, 0);
268 armpmu_stop(struct perf_event *event, int flags)
270 struct hw_perf_event *hwc = &event->hw;
273 * ARM pmu always has to update the counter, so ignore
274 * PERF_EF_UPDATE, see comments in armpmu_start().
276 if (!(hwc->state & PERF_HES_STOPPED)) {
277 armpmu->disable(hwc, hwc->idx);
278 barrier(); /* why? */
279 armpmu_event_update(event, hwc, hwc->idx, 0);
280 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
285 armpmu_start(struct perf_event *event, int flags)
287 struct hw_perf_event *hwc = &event->hw;
290 * ARM pmu always has to reprogram the period, so ignore
291 * PERF_EF_RELOAD, see the comment below.
293 if (flags & PERF_EF_RELOAD)
294 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
298 * Set the period again. Some counters can't be stopped, so when we
299 * were stopped we simply disabled the IRQ source and the counter
300 * may have been left counting. If we don't do this step then we may
301 * get an interrupt too soon or *way* too late if the overflow has
302 * happened since disabling.
304 armpmu_event_set_period(event, hwc, hwc->idx);
305 armpmu->enable(hwc, hwc->idx);
309 armpmu_del(struct perf_event *event, int flags)
311 struct cpu_hw_events *cpuc = armpmu->get_hw_events();
312 struct hw_perf_event *hwc = &event->hw;
317 armpmu_stop(event, PERF_EF_UPDATE);
318 cpuc->events[idx] = NULL;
319 clear_bit(idx, cpuc->used_mask);
321 perf_event_update_userpage(event);
325 armpmu_add(struct perf_event *event, int flags)
327 struct cpu_hw_events *cpuc = armpmu->get_hw_events();
328 struct hw_perf_event *hwc = &event->hw;
332 perf_pmu_disable(event->pmu);
334 /* If we don't have a space for the counter then finish early. */
335 idx = armpmu->get_event_idx(cpuc, hwc);
342 * If there is an event in the counter we are going to use then make
343 * sure it is disabled.
346 armpmu->disable(hwc, idx);
347 cpuc->events[idx] = event;
349 hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
350 if (flags & PERF_EF_START)
351 armpmu_start(event, PERF_EF_RELOAD);
353 /* Propagate our changes to the userspace mapping. */
354 perf_event_update_userpage(event);
357 perf_pmu_enable(event->pmu);
361 static struct pmu pmu;
364 validate_event(struct cpu_hw_events *cpuc,
365 struct perf_event *event)
367 struct hw_perf_event fake_event = event->hw;
368 struct pmu *leader_pmu = event->group_leader->pmu;
370 if (event->pmu != leader_pmu || event->state <= PERF_EVENT_STATE_OFF)
373 return armpmu->get_event_idx(cpuc, &fake_event) >= 0;
377 validate_group(struct perf_event *event)
379 struct perf_event *sibling, *leader = event->group_leader;
380 struct cpu_hw_events fake_pmu;
382 memset(&fake_pmu, 0, sizeof(fake_pmu));
384 if (!validate_event(&fake_pmu, leader))
387 list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
388 if (!validate_event(&fake_pmu, sibling))
392 if (!validate_event(&fake_pmu, event))
398 static irqreturn_t armpmu_platform_irq(int irq, void *dev)
400 struct platform_device *plat_device = armpmu->plat_device;
401 struct arm_pmu_platdata *plat = dev_get_platdata(&plat_device->dev);
403 return plat->handle_irq(irq, dev, armpmu->handle_irq);
407 armpmu_release_hardware(void)
410 struct platform_device *pmu_device = armpmu->plat_device;
412 irqs = min(pmu_device->num_resources, num_possible_cpus());
414 for (i = 0; i < irqs; ++i) {
415 if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs))
417 irq = platform_get_irq(pmu_device, i);
422 release_pmu(armpmu->type);
426 armpmu_reserve_hardware(void)
428 struct arm_pmu_platdata *plat;
429 irq_handler_t handle_irq;
430 int i, err, irq, irqs;
431 struct platform_device *pmu_device = armpmu->plat_device;
433 err = reserve_pmu(armpmu->type);
435 pr_warning("unable to reserve pmu\n");
439 plat = dev_get_platdata(&pmu_device->dev);
440 if (plat && plat->handle_irq)
441 handle_irq = armpmu_platform_irq;
443 handle_irq = armpmu->handle_irq;
445 irqs = min(pmu_device->num_resources, num_possible_cpus());
447 pr_err("no irqs for PMUs defined\n");
451 for (i = 0; i < irqs; ++i) {
453 irq = platform_get_irq(pmu_device, i);
458 * If we have a single PMU interrupt that we can't shift,
459 * assume that we're running on a uniprocessor machine and
460 * continue. Otherwise, continue without this interrupt.
462 if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
463 pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
468 err = request_irq(irq, handle_irq,
469 IRQF_DISABLED | IRQF_NOBALANCING,
472 pr_err("unable to request IRQ%d for ARM PMU counters\n",
474 armpmu_release_hardware();
478 cpumask_set_cpu(i, &armpmu->active_irqs);
485 hw_perf_event_destroy(struct perf_event *event)
487 atomic_t *active_events = &armpmu->active_events;
488 struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex;
490 if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) {
491 armpmu_release_hardware();
492 mutex_unlock(pmu_reserve_mutex);
497 event_requires_mode_exclusion(struct perf_event_attr *attr)
499 return attr->exclude_idle || attr->exclude_user ||
500 attr->exclude_kernel || attr->exclude_hv;
504 __hw_perf_event_init(struct perf_event *event)
506 struct hw_perf_event *hwc = &event->hw;
509 mapping = armpmu->map_event(event);
512 pr_debug("event %x:%llx not supported\n", event->attr.type,
518 * We don't assign an index until we actually place the event onto
519 * hardware. Use -1 to signify that we haven't decided where to put it
520 * yet. For SMP systems, each core has it's own PMU so we can't do any
521 * clever allocation or constraints checking at this point.
524 hwc->config_base = 0;
529 * Check whether we need to exclude the counter from certain modes.
531 if ((!armpmu->set_event_filter ||
532 armpmu->set_event_filter(hwc, &event->attr)) &&
533 event_requires_mode_exclusion(&event->attr)) {
534 pr_debug("ARM performance counters do not support "
540 * Store the event encoding into the config_base field.
542 hwc->config_base |= (unsigned long)mapping;
544 if (!hwc->sample_period) {
545 hwc->sample_period = armpmu->max_period;
546 hwc->last_period = hwc->sample_period;
547 local64_set(&hwc->period_left, hwc->sample_period);
551 if (event->group_leader != event) {
552 err = validate_group(event);
560 static int armpmu_event_init(struct perf_event *event)
563 atomic_t *active_events = &armpmu->active_events;
565 if (armpmu->map_event(event) == -ENOENT)
568 event->destroy = hw_perf_event_destroy;
570 if (!atomic_inc_not_zero(active_events)) {
571 mutex_lock(&armpmu->reserve_mutex);
572 if (atomic_read(active_events) == 0)
573 err = armpmu_reserve_hardware();
576 atomic_inc(active_events);
577 mutex_unlock(&armpmu->reserve_mutex);
583 err = __hw_perf_event_init(event);
585 hw_perf_event_destroy(event);
590 static void armpmu_enable(struct pmu *pmu)
592 /* Enable all of the perf events on hardware. */
593 int idx, enabled = 0;
594 struct cpu_hw_events *cpuc = armpmu->get_hw_events();
596 for (idx = 0; idx < armpmu->num_events; ++idx) {
597 struct perf_event *event = cpuc->events[idx];
602 armpmu->enable(&event->hw, idx);
610 static void armpmu_disable(struct pmu *pmu)
615 static struct pmu pmu = {
616 .pmu_enable = armpmu_enable,
617 .pmu_disable = armpmu_disable,
618 .event_init = armpmu_event_init,
621 .start = armpmu_start,
626 static void __init armpmu_init(struct arm_pmu *armpmu)
628 atomic_set(&armpmu->active_events, 0);
629 mutex_init(&armpmu->reserve_mutex);
632 /* Include the PMU-specific implementations. */
633 #include "perf_event_xscale.c"
634 #include "perf_event_v6.c"
635 #include "perf_event_v7.c"
638 * Ensure the PMU has sane values out of reset.
639 * This requires SMP to be available, so exists as a separate initcall.
644 if (armpmu && armpmu->reset)
645 return on_each_cpu(armpmu->reset, NULL, 1);
648 arch_initcall(armpmu_reset);
651 * PMU platform driver and devicetree bindings.
653 static struct of_device_id armpmu_of_device_ids[] = {
654 {.compatible = "arm,cortex-a9-pmu"},
655 {.compatible = "arm,cortex-a8-pmu"},
656 {.compatible = "arm,arm1136-pmu"},
657 {.compatible = "arm,arm1176-pmu"},
661 static struct platform_device_id armpmu_plat_device_ids[] = {
666 static int __devinit armpmu_device_probe(struct platform_device *pdev)
668 armpmu->plat_device = pdev;
672 static struct platform_driver armpmu_driver = {
675 .of_match_table = armpmu_of_device_ids,
677 .probe = armpmu_device_probe,
678 .id_table = armpmu_plat_device_ids,
681 static int __init register_pmu_driver(void)
683 return platform_driver_register(&armpmu_driver);
685 device_initcall(register_pmu_driver);
687 static struct cpu_hw_events *armpmu_get_cpu_events(void)
689 return &__get_cpu_var(cpu_hw_events);
692 static void __init cpu_pmu_init(struct arm_pmu *armpmu)
695 for_each_possible_cpu(cpu) {
696 struct cpu_hw_events *events = &per_cpu(cpu_hw_events, cpu);
697 raw_spin_lock_init(&events->pmu_lock);
699 armpmu->get_hw_events = armpmu_get_cpu_events;
700 armpmu->type = ARM_PMU_DEVICE_CPU;
704 * CPU PMU identification and registration.
707 init_hw_perf_events(void)
709 unsigned long cpuid = read_cpuid_id();
710 unsigned long implementor = (cpuid & 0xFF000000) >> 24;
711 unsigned long part_number = (cpuid & 0xFFF0);
714 if (0x41 == implementor) {
715 switch (part_number) {
716 case 0xB360: /* ARM1136 */
717 case 0xB560: /* ARM1156 */
718 case 0xB760: /* ARM1176 */
719 armpmu = armv6pmu_init();
721 case 0xB020: /* ARM11mpcore */
722 armpmu = armv6mpcore_pmu_init();
724 case 0xC080: /* Cortex-A8 */
725 armpmu = armv7_a8_pmu_init();
727 case 0xC090: /* Cortex-A9 */
728 armpmu = armv7_a9_pmu_init();
730 case 0xC050: /* Cortex-A5 */
731 armpmu = armv7_a5_pmu_init();
733 case 0xC0F0: /* Cortex-A15 */
734 armpmu = armv7_a15_pmu_init();
737 /* Intel CPUs [xscale]. */
738 } else if (0x69 == implementor) {
739 part_number = (cpuid >> 13) & 0x7;
740 switch (part_number) {
742 armpmu = xscale1pmu_init();
745 armpmu = xscale2pmu_init();
751 pr_info("enabled with %s PMU driver, %d counters available\n",
752 armpmu->name, armpmu->num_events);
753 cpu_pmu_init(armpmu);
755 perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
757 pr_info("no hardware support available\n");
762 early_initcall(init_hw_perf_events);
765 * Callchain handling code.
769 * The registers we're interested in are at the end of the variable
770 * length saved register structure. The fp points at the end of this
771 * structure so the address of this struct is:
772 * (struct frame_tail *)(xxx->fp)-1
774 * This code has been adapted from the ARM OProfile support.
777 struct frame_tail __user *fp;
780 } __attribute__((packed));
783 * Get the return address for a single stackframe and return a pointer to the
786 static struct frame_tail __user *
787 user_backtrace(struct frame_tail __user *tail,
788 struct perf_callchain_entry *entry)
790 struct frame_tail buftail;
792 /* Also check accessibility of one struct frame_tail beyond */
793 if (!access_ok(VERIFY_READ, tail, sizeof(buftail)))
795 if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail)))
798 perf_callchain_store(entry, buftail.lr);
801 * Frame pointers should strictly progress back up the stack
802 * (towards higher addresses).
804 if (tail + 1 >= buftail.fp)
807 return buftail.fp - 1;
811 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
813 struct frame_tail __user *tail;
816 tail = (struct frame_tail __user *)regs->ARM_fp - 1;
818 while ((entry->nr < PERF_MAX_STACK_DEPTH) &&
819 tail && !((unsigned long)tail & 0x3))
820 tail = user_backtrace(tail, entry);
824 * Gets called by walk_stackframe() for every stackframe. This will be called
825 * whist unwinding the stackframe and is like a subroutine return so we use
829 callchain_trace(struct stackframe *fr,
832 struct perf_callchain_entry *entry = data;
833 perf_callchain_store(entry, fr->pc);
838 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
840 struct stackframe fr;
842 fr.fp = regs->ARM_fp;
843 fr.sp = regs->ARM_sp;
844 fr.lr = regs->ARM_lr;
845 fr.pc = regs->ARM_pc;
846 walk_stackframe(&fr, callchain_trace, entry);