arch/arm/kernel/perf_event.c

   1 #undef DEBUG
   2
   3 /*
   4  * ARM performance counter support.
   5  *
   6  * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
   7  * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
   8  *
   9  * This code is based on the sparc64 perf event code, which is in turn based
  10  * on the x86 code. Callchain code is based on the ARM OProfile backtrace
  11  * code.
  12  */
  13 #define pr_fmt(fmt) "hw perfevents: " fmt
  14
  15 #include <linux/bitmap.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/kernel.h>
  18 #include <linux/export.h>
  19 #include <linux/of.h>
  20 #include <linux/perf_event.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/uaccess.h>
  24 #include <linux/pm_runtime.h>
  25
  26 #include <asm/cputype.h>
  27 #include <asm/irq.h>
  28 #include <asm/irq_regs.h>
  29 #include <asm/pmu.h>
  30 #include <asm/stacktrace.h>
  31
  32 /* Set at runtime when we know what CPU type we are. */
  33 static struct arm_pmu *cpu_pmu;
  34
  35 static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events);
  36 static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask);
  37 static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events);
  38
  39 /*
  40  * Despite the names, these two functions are CPU-specific and are used
  41  * by the OProfile/perf code.
  42  */
  43 const char *perf_pmu_name(void)
  44 {
  45         if (!cpu_pmu)
  46                 return NULL;
  47
  48         return cpu_pmu->pmu.name;
  49 }
  50 EXPORT_SYMBOL_GPL(perf_pmu_name);
  51
  52 int perf_num_counters(void)
  53 {
  54         int max_events = 0;
  55
  56         if (cpu_pmu != NULL)
  57                 max_events = cpu_pmu->num_events;
  58
  59         return max_events;
  60 }
  61 EXPORT_SYMBOL_GPL(perf_num_counters);
  62
  63 static int
  64 armpmu_map_cache_event(const unsigned (*cache_map)
  65                                       [PERF_COUNT_HW_CACHE_MAX]
  66                                       [PERF_COUNT_HW_CACHE_OP_MAX]
  67                                       [PERF_COUNT_HW_CACHE_RESULT_MAX],
  68                        u64 config)
  69 {
  70         unsigned int cache_type, cache_op, cache_result, ret;
  71
  72         cache_type = (config >>  0) & 0xff;
  73         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
  74                 return -EINVAL;
  75
  76         cache_op = (config >>  8) & 0xff;
  77         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
  78                 return -EINVAL;
  79
  80         cache_result = (config >> 16) & 0xff;
  81         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
  82                 return -EINVAL;
  83
  84         ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
  85
  86         if (ret == CACHE_OP_UNSUPPORTED)
  87                 return -ENOENT;
  88
  89         return ret;
  90 }
  91
  92 static int
  93 armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
  94 {
  95         int mapping = (*event_map)[config];
  96         return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
  97 }
  98
  99 static int
 100 armpmu_map_raw_event(u32 raw_event_mask, u64 config)
 101 {
 102         return (int)(config & raw_event_mask);
 103 }
 104
 105 int
 106 armpmu_map_event(struct perf_event *event,
 107                  const unsigned (*event_map)[PERF_COUNT_HW_MAX],
 108                  const unsigned (*cache_map)
 109                                 [PERF_COUNT_HW_CACHE_MAX]
 110                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 111                                 [PERF_COUNT_HW_CACHE_RESULT_MAX],
 112                  u32 raw_event_mask)
 113 {
 114         u64 config = event->attr.config;
 115
 116         switch (event->attr.type) {
 117         case PERF_TYPE_HARDWARE:
 118                 return armpmu_map_hw_event(event_map, config);
 119         case PERF_TYPE_HW_CACHE:
 120                 return armpmu_map_cache_event(cache_map, config);
 121         case PERF_TYPE_RAW:
 122                 return armpmu_map_raw_event(raw_event_mask, config);
 123         }
 124
 125         return -ENOENT;
 126 }
 127
 128 int
 129 armpmu_event_set_period(struct perf_event *event,
 130                         struct hw_perf_event *hwc,
 131                         int idx)
 132 {
 133         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 134         s64 left = local64_read(&hwc->period_left);
 135         s64 period = hwc->sample_period;
 136         int ret = 0;
 137
 138         if (unlikely(left <= -period)) {
 139                 left = period;
 140                 local64_set(&hwc->period_left, left);
 141                 hwc->last_period = period;
 142                 ret = 1;
 143         }
 144
 145         if (unlikely(left <= 0)) {
 146                 left += period;
 147                 local64_set(&hwc->period_left, left);
 148                 hwc->last_period = period;
 149                 ret = 1;
 150         }
 151
 152         if (left > (s64)armpmu->max_period)
 153                 left = armpmu->max_period;
 154
 155         local64_set(&hwc->prev_count, (u64)-left);
 156
 157         armpmu->write_counter(idx, (u64)(-left) & 0xffffffff);
 158
 159         perf_event_update_userpage(event);
 160
 161         return ret;
 162 }
 163
 164 u64
 165 armpmu_event_update(struct perf_event *event,
 166                     struct hw_perf_event *hwc,
 167                     int idx)
 168 {
 169         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 170         u64 delta, prev_raw_count, new_raw_count;
 171
 172 again:
 173         prev_raw_count = local64_read(&hwc->prev_count);
 174         new_raw_count = armpmu->read_counter(idx);
 175
 176         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
 177                              new_raw_count) != prev_raw_count)
 178                 goto again;
 179
 180         delta = (new_raw_count - prev_raw_count) & armpmu->max_period;
 181
 182         local64_add(delta, &event->count);
 183         local64_sub(delta, &hwc->period_left);
 184
 185         return new_raw_count;
 186 }
 187
 188 static void
 189 armpmu_read(struct perf_event *event)
 190 {
 191         struct hw_perf_event *hwc = &event->hw;
 192
 193         /* Don't read disabled counters! */
 194         if (hwc->idx < 0)
 195                 return;
 196
 197         armpmu_event_update(event, hwc, hwc->idx);
 198 }
 199
 200 static void
 201 armpmu_stop(struct perf_event *event, int flags)
 202 {
 203         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 204         struct hw_perf_event *hwc = &event->hw;
 205
 206         /*
 207          * ARM pmu always has to update the counter, so ignore
 208          * PERF_EF_UPDATE, see comments in armpmu_start().
 209          */
 210         if (!(hwc->state & PERF_HES_STOPPED)) {
 211                 armpmu->disable(hwc, hwc->idx);
 212                 armpmu_event_update(event, hwc, hwc->idx);
 213                 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
 214         }
 215 }
 216
 217 static void
 218 armpmu_start(struct perf_event *event, int flags)
 219 {
 220         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 221         struct hw_perf_event *hwc = &event->hw;
 222
 223         /*
 224          * ARM pmu always has to reprogram the period, so ignore
 225          * PERF_EF_RELOAD, see the comment below.
 226          */
 227         if (flags & PERF_EF_RELOAD)
 228                 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
 229
 230         hwc->state = 0;
 231         /*
 232          * Set the period again. Some counters can't be stopped, so when we
 233          * were stopped we simply disabled the IRQ source and the counter
 234          * may have been left counting. If we don't do this step then we may
 235          * get an interrupt too soon or *way* too late if the overflow has
 236          * happened since disabling.
 237          */
 238         armpmu_event_set_period(event, hwc, hwc->idx);
 239         armpmu->enable(hwc, hwc->idx);
 240 }
 241
 242 static void
 243 armpmu_del(struct perf_event *event, int flags)
 244 {
 245         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 246         struct pmu_hw_events *hw_events = armpmu->get_hw_events();
 247         struct hw_perf_event *hwc = &event->hw;
 248         int idx = hwc->idx;
 249
 250         WARN_ON(idx < 0);
 251
 252         armpmu_stop(event, PERF_EF_UPDATE);
 253         hw_events->events[idx] = NULL;
 254         clear_bit(idx, hw_events->used_mask);
 255
 256         perf_event_update_userpage(event);
 257 }
 258
 259 static int
 260 armpmu_add(struct perf_event *event, int flags)
 261 {
 262         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 263         struct pmu_hw_events *hw_events = armpmu->get_hw_events();
 264         struct hw_perf_event *hwc = &event->hw;
 265         int idx;
 266         int err = 0;
 267
 268         perf_pmu_disable(event->pmu);
 269
 270         /* If we don't have a space for the counter then finish early. */
 271         idx = armpmu->get_event_idx(hw_events, hwc);
 272         if (idx < 0) {
 273                 err = idx;
 274                 goto out;
 275         }
 276
 277         /*
 278          * If there is an event in the counter we are going to use then make
 279          * sure it is disabled.
 280          */
 281         event->hw.idx = idx;
 282         armpmu->disable(hwc, idx);
 283         hw_events->events[idx] = event;
 284
 285         hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
 286         if (flags & PERF_EF_START)
 287                 armpmu_start(event, PERF_EF_RELOAD);
 288
 289         /* Propagate our changes to the userspace mapping. */
 290         perf_event_update_userpage(event);
 291
 292 out:
 293         perf_pmu_enable(event->pmu);
 294         return err;
 295 }
 296
 297 static int
 298 validate_event(struct pmu_hw_events *hw_events,
 299                struct perf_event *event)
 300 {
 301         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 302         struct hw_perf_event fake_event = event->hw;
 303         struct pmu *leader_pmu = event->group_leader->pmu;
 304
 305         if (event->pmu != leader_pmu || event->state <= PERF_EVENT_STATE_OFF)
 306                 return 1;
 307
 308         return armpmu->get_event_idx(hw_events, &fake_event) >= 0;
 309 }
 310
 311 static int
 312 validate_group(struct perf_event *event)
 313 {
 314         struct perf_event *sibling, *leader = event->group_leader;
 315         struct pmu_hw_events fake_pmu;
 316         DECLARE_BITMAP(fake_used_mask, ARMPMU_MAX_HWEVENTS);
 317
 318         /*
 319          * Initialise the fake PMU. We only need to populate the
 320          * used_mask for the purposes of validation.
 321          */
 322         memset(fake_used_mask, 0, sizeof(fake_used_mask));
 323         fake_pmu.used_mask = fake_used_mask;
 324
 325         if (!validate_event(&fake_pmu, leader))
 326                 return -EINVAL;
 327
 328         list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
 329                 if (!validate_event(&fake_pmu, sibling))
 330                         return -EINVAL;
 331         }
 332
 333         if (!validate_event(&fake_pmu, event))
 334                 return -EINVAL;
 335
 336         return 0;
 337 }
 338
 339 static irqreturn_t armpmu_platform_irq(int irq, void *dev)
 340 {
 341         struct arm_pmu *armpmu = (struct arm_pmu *) dev;
 342         struct platform_device *plat_device = armpmu->plat_device;
 343         struct arm_pmu_platdata *plat = dev_get_platdata(&plat_device->dev);
 344
 345         return plat->handle_irq(irq, dev, armpmu->handle_irq);
 346 }
 347
 348 static void
 349 armpmu_release_hardware(struct arm_pmu *armpmu)
 350 {
 351         int i, irq, irqs;
 352         struct platform_device *pmu_device = armpmu->plat_device;
 353
 354         irqs = min(pmu_device->num_resources, num_possible_cpus());
 355
 356         for (i = 0; i < irqs; ++i) {
 357                 if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs))
 358                         continue;
 359                 irq = platform_get_irq(pmu_device, i);
 360                 if (irq >= 0)
 361                         free_irq(irq, armpmu);
 362         }
 363
 364         pm_runtime_put_sync(&pmu_device->dev);
 365 }
 366
 367 static int
 368 armpmu_reserve_hardware(struct arm_pmu *armpmu)
 369 {
 370         struct arm_pmu_platdata *plat;
 371         irq_handler_t handle_irq;
 372         int i, err, irq, irqs;
 373         struct platform_device *pmu_device = armpmu->plat_device;
 374
 375         if (!pmu_device)
 376                 return -ENODEV;
 377
 378         plat = dev_get_platdata(&pmu_device->dev);
 379         if (plat && plat->handle_irq)
 380                 handle_irq = armpmu_platform_irq;
 381         else
 382                 handle_irq = armpmu->handle_irq;
 383
 384         irqs = min(pmu_device->num_resources, num_possible_cpus());
 385         if (irqs < 1) {
 386                 pr_err("no irqs for PMUs defined\n");
 387                 return -ENODEV;
 388         }
 389
 390         pm_runtime_get_sync(&pmu_device->dev);
 391
 392         for (i = 0; i < irqs; ++i) {
 393                 err = 0;
 394                 irq = platform_get_irq(pmu_device, i);
 395                 if (irq < 0)
 396                         continue;
 397
 398                 /*
 399                  * If we have a single PMU interrupt that we can't shift,
 400                  * assume that we're running on a uniprocessor machine and
 401                  * continue. Otherwise, continue without this interrupt.
 402                  */
 403                 if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
 404                         pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
 405                                     irq, i);
 406                         continue;
 407                 }
 408
 409                 err = request_irq(irq, handle_irq,
 410                                   IRQF_DISABLED | IRQF_NOBALANCING,
 411                                   "arm-pmu", armpmu);
 412                 if (err) {
 413                         pr_err("unable to request IRQ%d for ARM PMU counters\n",
 414                                 irq);
 415                         armpmu_release_hardware(armpmu);
 416                         return err;
 417                 }
 418
 419                 cpumask_set_cpu(i, &armpmu->active_irqs);
 420         }
 421
 422         return 0;
 423 }
 424
 425 static void
 426 hw_perf_event_destroy(struct perf_event *event)
 427 {
 428         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 429         atomic_t *active_events  = &armpmu->active_events;
 430         struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex;
 431
 432         if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) {
 433                 armpmu_release_hardware(armpmu);
 434                 mutex_unlock(pmu_reserve_mutex);
 435         }
 436 }
 437
 438 static int
 439 event_requires_mode_exclusion(struct perf_event_attr *attr)
 440 {
 441         return attr->exclude_idle || attr->exclude_user ||
 442                attr->exclude_kernel || attr->exclude_hv;
 443 }
 444
 445 static int
 446 __hw_perf_event_init(struct perf_event *event)
 447 {
 448         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 449         struct hw_perf_event *hwc = &event->hw;
 450         int mapping, err;
 451
 452         mapping = armpmu->map_event(event);
 453
 454         if (mapping < 0) {
 455                 pr_debug("event %x:%llx not supported\n", event->attr.type,
 456                          event->attr.config);
 457                 return mapping;
 458         }
 459
 460         /*
 461          * We don't assign an index until we actually place the event onto
 462          * hardware. Use -1 to signify that we haven't decided where to put it
 463          * yet. For SMP systems, each core has it's own PMU so we can't do any
 464          * clever allocation or constraints checking at this point.
 465          */
 466         hwc->idx                = -1;
 467         hwc->config_base        = 0;
 468         hwc->config             = 0;
 469         hwc->event_base         = 0;
 470
 471         /*
 472          * Check whether we need to exclude the counter from certain modes.
 473          */
 474         if ((!armpmu->set_event_filter ||
 475              armpmu->set_event_filter(hwc, &event->attr)) &&
 476              event_requires_mode_exclusion(&event->attr)) {
 477                 pr_debug("ARM performance counters do not support "
 478                          "mode exclusion\n");
 479                 return -EOPNOTSUPP;
 480         }
 481
 482         /*
 483          * Store the event encoding into the config_base field.
 484          */
 485         hwc->config_base            |= (unsigned long)mapping;
 486
 487         if (!hwc->sample_period) {
 488                 /*
 489                  * For non-sampling runs, limit the sample_period to half
 490                  * of the counter width. That way, the new counter value
 491                  * is far less likely to overtake the previous one unless
 492                  * you have some serious IRQ latency issues.
 493                  */
 494                 hwc->sample_period  = armpmu->max_period >> 1;
 495                 hwc->last_period    = hwc->sample_period;
 496                 local64_set(&hwc->period_left, hwc->sample_period);
 497         }
 498
 499         err = 0;
 500         if (event->group_leader != event) {
 501                 err = validate_group(event);
 502                 if (err)
 503                         return -EINVAL;
 504         }
 505
 506         return err;
 507 }
 508
 509 static int armpmu_event_init(struct perf_event *event)
 510 {
 511         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 512         int err = 0;
 513         atomic_t *active_events = &armpmu->active_events;
 514
 515         /* does not support taken branch sampling */
 516         if (has_branch_stack(event))
 517                 return -EOPNOTSUPP;
 518
 519         if (armpmu->map_event(event) == -ENOENT)
 520                 return -ENOENT;
 521
 522         event->destroy = hw_perf_event_destroy;
 523
 524         if (!atomic_inc_not_zero(active_events)) {
 525                 mutex_lock(&armpmu->reserve_mutex);
 526                 if (atomic_read(active_events) == 0)
 527                         err = armpmu_reserve_hardware(armpmu);
 528
 529                 if (!err)
 530                         atomic_inc(active_events);
 531                 mutex_unlock(&armpmu->reserve_mutex);
 532         }
 533
 534         if (err)
 535                 return err;
 536
 537         err = __hw_perf_event_init(event);
 538         if (err)
 539                 hw_perf_event_destroy(event);
 540
 541         return err;
 542 }
 543
 544 static void armpmu_enable(struct pmu *pmu)
 545 {
 546         struct arm_pmu *armpmu = to_arm_pmu(pmu);
 547         struct pmu_hw_events *hw_events = armpmu->get_hw_events();
 548         int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
 549
 550         if (enabled)
 551                 armpmu->start();
 552 }
 553
 554 static void armpmu_disable(struct pmu *pmu)
 555 {
 556         struct arm_pmu *armpmu = to_arm_pmu(pmu);
 557         armpmu->stop();
 558 }
 559
 560 #ifdef CONFIG_PM_RUNTIME
 561 static int armpmu_runtime_resume(struct device *dev)
 562 {
 563         struct arm_pmu_platdata *plat = dev_get_platdata(dev);
 564
 565         if (plat && plat->runtime_resume)
 566                 return plat->runtime_resume(dev);
 567
 568         return 0;
 569 }
 570
 571 static int armpmu_runtime_suspend(struct device *dev)
 572 {
 573         struct arm_pmu_platdata *plat = dev_get_platdata(dev);
 574
 575         if (plat && plat->runtime_suspend)
 576                 return plat->runtime_suspend(dev);
 577
 578         return 0;
 579 }
 580 #endif
 581
 582 const struct dev_pm_ops armpmu_dev_pm_ops = {
 583         SET_RUNTIME_PM_OPS(armpmu_runtime_suspend, armpmu_runtime_resume, NULL)
 584 };
 585
 586 static void __init armpmu_init(struct arm_pmu *armpmu)
 587 {
 588         atomic_set(&armpmu->active_events, 0);
 589         mutex_init(&armpmu->reserve_mutex);
 590
 591         armpmu->pmu = (struct pmu) {
 592                 .pmu_enable     = armpmu_enable,
 593                 .pmu_disable    = armpmu_disable,
 594                 .event_init     = armpmu_event_init,
 595                 .add            = armpmu_add,
 596                 .del            = armpmu_del,
 597                 .start          = armpmu_start,
 598                 .stop           = armpmu_stop,
 599                 .read           = armpmu_read,
 600         };
 601 }
 602
 603 int armpmu_register(struct arm_pmu *armpmu, char *name, int type)
 604 {
 605         armpmu_init(armpmu);
 606         pr_info("enabled with %s PMU driver, %d counters available\n",
 607                         armpmu->name, armpmu->num_events);
 608         return perf_pmu_register(&armpmu->pmu, name, type);
 609 }
 610
 611 /* Include the PMU-specific implementations. */
 612 #include "perf_event_xscale.c"
 613 #include "perf_event_v6.c"
 614 #include "perf_event_v7.c"
 615
 616 static struct pmu_hw_events *cpu_pmu_get_cpu_events(void)
 617 {
 618         return &__get_cpu_var(cpu_hw_events);
 619 }
 620
 621 static void __devinit cpu_pmu_init(struct arm_pmu *cpu_pmu)
 622 {
 623         int cpu;
 624         for_each_possible_cpu(cpu) {
 625                 struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu);
 626                 events->events = per_cpu(hw_events, cpu);
 627                 events->used_mask = per_cpu(used_mask, cpu);
 628                 raw_spin_lock_init(&events->pmu_lock);
 629         }
 630         cpu_pmu->get_hw_events = cpu_pmu_get_cpu_events;
 631
 632         /* Ensure the PMU has sane values out of reset. */
 633         if (cpu_pmu && cpu_pmu->reset)
 634                 on_each_cpu(cpu_pmu->reset, NULL, 1);
 635 }
 636
 637 /*
 638  * PMU hardware loses all context when a CPU goes offline.
 639  * When a CPU is hotplugged back in, since some hardware registers are
 640  * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
 641  * junk values out of them.
 642  */
 643 static int __cpuinit cpu_pmu_notify(struct notifier_block *b,
 644                                     unsigned long action, void *hcpu)
 645 {
 646         if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING)
 647                 return NOTIFY_DONE;
 648
 649         if (cpu_pmu && cpu_pmu->reset)
 650                 cpu_pmu->reset(NULL);
 651
 652         return NOTIFY_OK;
 653 }
 654
 655 static struct notifier_block __cpuinitdata cpu_pmu_hotplug_notifier = {
 656         .notifier_call = cpu_pmu_notify,
 657 };
 658
 659 /*
 660  * PMU platform driver and devicetree bindings.
 661  */
 662 static struct of_device_id __devinitdata cpu_pmu_of_device_ids[] = {
 663         {.compatible = "arm,cortex-a15-pmu",    .data = armv7_a15_pmu_init},
 664         {.compatible = "arm,cortex-a9-pmu",     .data = armv7_a9_pmu_init},
 665         {.compatible = "arm,cortex-a8-pmu",     .data = armv7_a8_pmu_init},
 666         {.compatible = "arm,cortex-a7-pmu",     .data = armv7_a7_pmu_init},
 667         {.compatible = "arm,cortex-a5-pmu",     .data = armv7_a5_pmu_init},
 668         {.compatible = "arm,arm11mpcore-pmu",   .data = armv6mpcore_pmu_init},
 669         {.compatible = "arm,arm1176-pmu",       .data = armv6pmu_init},
 670         {.compatible = "arm,arm1136-pmu",       .data = armv6pmu_init},
 671         {},
 672 };
 673
 674 static struct platform_device_id __devinitdata cpu_pmu_plat_device_ids[] = {
 675         {.name = "arm-pmu"},
 676         {},
 677 };
 678
 679 /*
 680  * CPU PMU identification and probing.
 681  */
 682 static struct arm_pmu *__devinit probe_current_pmu(void)
 683 {
 684         struct arm_pmu *pmu = NULL;
 685         int cpu = get_cpu();
 686         unsigned long cpuid = read_cpuid_id();
 687         unsigned long implementor = (cpuid & 0xFF000000) >> 24;
 688         unsigned long part_number = (cpuid & 0xFFF0);
 689
 690         pr_info("probing PMU on CPU %d\n", cpu);
 691
 692         /* ARM Ltd CPUs. */
 693         if (0x41 == implementor) {
 694                 switch (part_number) {
 695                 case 0xB360:    /* ARM1136 */
 696                 case 0xB560:    /* ARM1156 */
 697                 case 0xB760:    /* ARM1176 */
 698                         pmu = armv6pmu_init();
 699                         break;
 700                 case 0xB020:    /* ARM11mpcore */
 701                         pmu = armv6mpcore_pmu_init();
 702                         break;
 703                 case 0xC080:    /* Cortex-A8 */
 704                         pmu = armv7_a8_pmu_init();
 705                         break;
 706                 case 0xC090:    /* Cortex-A9 */
 707                         pmu = armv7_a9_pmu_init();
 708                         break;
 709                 case 0xC050:    /* Cortex-A5 */
 710                         pmu = armv7_a5_pmu_init();
 711                         break;
 712                 case 0xC0F0:    /* Cortex-A15 */
 713                         pmu = armv7_a15_pmu_init();
 714                         break;
 715                 case 0xC070:    /* Cortex-A7 */
 716                         pmu = armv7_a7_pmu_init();
 717                         break;
 718                 }
 719         /* Intel CPUs [xscale]. */
 720         } else if (0x69 == implementor) {
 721                 part_number = (cpuid >> 13) & 0x7;
 722                 switch (part_number) {
 723                 case 1:
 724                         pmu = xscale1pmu_init();
 725                         break;
 726                 case 2:
 727                         pmu = xscale2pmu_init();
 728                         break;
 729                 }
 730         }
 731
 732         put_cpu();
 733         return pmu;
 734 }
 735
 736 static int __devinit cpu_pmu_device_probe(struct platform_device *pdev)
 737 {
 738         const struct of_device_id *of_id;
 739         struct arm_pmu *(*init_fn)(void);
 740         struct device_node *node = pdev->dev.of_node;
 741
 742         if (cpu_pmu) {
 743                 pr_info("attempt to register multiple PMU devices!");
 744                 return -ENOSPC;
 745         }
 746
 747         if (node && (of_id = of_match_node(cpu_pmu_of_device_ids, pdev->dev.of_node))) {
 748                 init_fn = of_id->data;
 749                 cpu_pmu = init_fn();
 750         } else {
 751                 cpu_pmu = probe_current_pmu();
 752         }
 753
 754         if (!cpu_pmu)
 755                 return -ENODEV;
 756
 757         cpu_pmu->plat_device = pdev;
 758         cpu_pmu_init(cpu_pmu);
 759         register_cpu_notifier(&cpu_pmu_hotplug_notifier);
 760         armpmu_register(cpu_pmu, cpu_pmu->name, PERF_TYPE_RAW);
 761
 762         return 0;
 763 }
 764
 765 static struct platform_driver cpu_pmu_driver = {
 766         .driver         = {
 767                 .name   = "arm-pmu",
 768                 .pm     = &armpmu_dev_pm_ops,
 769                 .of_match_table = cpu_pmu_of_device_ids,
 770         },
 771         .probe          = cpu_pmu_device_probe,
 772         .id_table       = cpu_pmu_plat_device_ids,
 773 };
 774
 775 static int __init register_pmu_driver(void)
 776 {
 777         return platform_driver_register(&cpu_pmu_driver);
 778 }
 779 device_initcall(register_pmu_driver);
 780
 781 /*
 782  * Callchain handling code.
 783  */
 784
 785 /*
 786  * The registers we're interested in are at the end of the variable
 787  * length saved register structure. The fp points at the end of this
 788  * structure so the address of this struct is:
 789  * (struct frame_tail *)(xxx->fp)-1
 790  *
 791  * This code has been adapted from the ARM OProfile support.
 792  */
 793 struct frame_tail {
 794         struct frame_tail __user *fp;
 795         unsigned long sp;
 796         unsigned long lr;
 797 } __attribute__((packed));
 798
 799 /*
 800  * Get the return address for a single stackframe and return a pointer to the
 801  * next frame tail.
 802  */
 803 static struct frame_tail __user *
 804 user_backtrace(struct frame_tail __user *tail,
 805                struct perf_callchain_entry *entry)
 806 {
 807         struct frame_tail buftail;
 808
 809         /* Also check accessibility of one struct frame_tail beyond */
 810         if (!access_ok(VERIFY_READ, tail, sizeof(buftail)))
 811                 return NULL;
 812         if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail)))
 813                 return NULL;
 814
 815         perf_callchain_store(entry, buftail.lr);
 816
 817         /*
 818          * Frame pointers should strictly progress back up the stack
 819          * (towards higher addresses).
 820          */
 821         if (tail + 1 >= buftail.fp)
 822                 return NULL;
 823
 824         return buftail.fp - 1;
 825 }
 826
 827 void
 828 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
 829 {
 830         struct frame_tail __user *tail;
 831
 832
 833         tail = (struct frame_tail __user *)regs->ARM_fp - 1;
 834
 835         while ((entry->nr < PERF_MAX_STACK_DEPTH) &&
 836                tail && !((unsigned long)tail & 0x3))
 837                 tail = user_backtrace(tail, entry);
 838 }
 839
 840 /*
 841  * Gets called by walk_stackframe() for every stackframe. This will be called
 842  * whist unwinding the stackframe and is like a subroutine return so we use
 843  * the PC.
 844  */
 845 static int
 846 callchain_trace(struct stackframe *fr,
 847                 void *data)
 848 {
 849         struct perf_callchain_entry *entry = data;
 850         perf_callchain_store(entry, fr->pc);
 851         return 0;
 852 }
 853
 854 void
 855 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
 856 {
 857         struct stackframe fr;
 858
 859         fr.fp = regs->ARM_fp;
 860         fr.sp = regs->ARM_sp;
 861         fr.lr = regs->ARM_lr;
 862         fr.pc = regs->ARM_pc;
 863         walk_stackframe(&fr, callchain_trace, entry);
 864 }