2 * arch/arm/kernel/kprobes-decode.c
4 * Copyright (C) 2006, 2007 Motorola Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
17 * We do not have hardware single-stepping on ARM, This
18 * effort is further complicated by the ARM not having a
19 * "next PC" register. Instructions that change the PC
20 * can't be safely single-stepped in a MP environment, so
21 * we have a lot of work to do:
23 * In the prepare phase:
24 * *) If it is an instruction that does anything
25 * with the CPU mode, we reject it for a kprobe.
26 * (This is out of laziness rather than need. The
27 * instructions could be simulated.)
29 * *) Otherwise, decode the instruction rewriting its
30 * registers to take fixed, ordered registers and
31 * setting a handler for it to run the instruction.
33 * In the execution phase by an instruction's handler:
35 * *) If the PC is written to by the instruction, the
36 * instruction must be fully simulated in software.
37 * If it is a conditional instruction, the handler
38 * will use insn[0] to copy its condition code to
39 * set r0 to 1 and insn[1] to "mov pc, lr" to return.
41 * *) Otherwise, a modified form of the instruction is
42 * directly executed. Its handler calls the
43 * instruction in insn[0]. In insn[1] is a
44 * "mov pc, lr" to return.
46 * Before calling, load up the reordered registers
47 * from the original instruction's registers. If one
48 * of the original input registers is the PC, compute
49 * and adjust the appropriate input register.
51 * After call completes, copy the output registers to
52 * the original instruction's original registers.
54 * We don't use a real breakpoint instruction since that
55 * would have us in the kernel go from SVC mode to SVC
56 * mode losing the link register. Instead we use an
57 * undefined instruction. To simplify processing, the
58 * undefined instruction used for kprobes must be reserved
59 * exclusively for kprobes use.
61 * TODO: ifdef out some instruction decoding based on architecture.
64 #include <linux/kernel.h>
65 #include <linux/kprobes.h>
67 #define sign_extend(x, signbit) ((x) | (0 - ((x) & (1 << (signbit)))))
69 #define branch_displacement(insn) sign_extend(((insn) & 0xffffff) << 2, 25)
71 #define PSR_fs (PSR_f|PSR_s)
73 #define KPROBE_RETURN_INSTRUCTION 0xe1a0f00e /* mov pc, lr */
75 typedef long (insn_0arg_fn_t)(void);
76 typedef long (insn_1arg_fn_t)(long);
77 typedef long (insn_2arg_fn_t)(long, long);
78 typedef long (insn_3arg_fn_t)(long, long, long);
79 typedef long (insn_4arg_fn_t)(long, long, long, long);
80 typedef long long (insn_llret_0arg_fn_t)(void);
81 typedef long long (insn_llret_3arg_fn_t)(long, long, long);
82 typedef long long (insn_llret_4arg_fn_t)(long, long, long, long);
86 #ifdef __LITTLE_ENDIAN
87 struct { long r0, r1; };
89 struct { long r1, r0; };
94 * For STR and STM instructions, an ARM core may choose to use either
95 * a +8 or a +12 displacement from the current instruction's address.
96 * Whichever value is chosen for a given core, it must be the same for
97 * both instructions and may not change. This function measures it.
100 static int str_pc_offset;
102 static void __init find_str_pc_offset(void)
104 int addr, scratch, ret;
107 "sub %[ret], pc, #4 \n\t"
108 "str pc, %[addr] \n\t"
109 "ldr %[scr], %[addr] \n\t"
110 "sub %[ret], %[scr], %[ret] \n\t"
111 : [ret] "=r" (ret), [scr] "=r" (scratch), [addr] "+m" (addr));
117 * The insnslot_?arg_r[w]flags() functions below are to keep the
118 * msr -> *fn -> mrs instruction sequences indivisible so that
119 * the state of the CPSR flags aren't inadvertently modified
120 * just before or just after the call.
123 static inline long __kprobes
124 insnslot_0arg_rflags(long cpsr, insn_0arg_fn_t *fn)
126 register long ret asm("r0");
128 __asm__ __volatile__ (
129 "msr cpsr_fs, %[cpsr] \n\t"
133 : [cpsr] "r" (cpsr), [fn] "r" (fn)
139 static inline long long __kprobes
140 insnslot_llret_0arg_rflags(long cpsr, insn_llret_0arg_fn_t *fn)
142 register long ret0 asm("r0");
143 register long ret1 asm("r1");
146 __asm__ __volatile__ (
147 "msr cpsr_fs, %[cpsr] \n\t"
150 : "=r" (ret0), "=r" (ret1)
151 : [cpsr] "r" (cpsr), [fn] "r" (fn)
159 static inline long __kprobes
160 insnslot_1arg_rflags(long r0, long cpsr, insn_1arg_fn_t *fn)
162 register long rr0 asm("r0") = r0;
163 register long ret asm("r0");
165 __asm__ __volatile__ (
166 "msr cpsr_fs, %[cpsr] \n\t"
170 : "0" (rr0), [cpsr] "r" (cpsr), [fn] "r" (fn)
176 static inline long __kprobes
177 insnslot_2arg_rflags(long r0, long r1, long cpsr, insn_2arg_fn_t *fn)
179 register long rr0 asm("r0") = r0;
180 register long rr1 asm("r1") = r1;
181 register long ret asm("r0");
183 __asm__ __volatile__ (
184 "msr cpsr_fs, %[cpsr] \n\t"
188 : "0" (rr0), "r" (rr1),
189 [cpsr] "r" (cpsr), [fn] "r" (fn)
195 static inline long __kprobes
196 insnslot_3arg_rflags(long r0, long r1, long r2, long cpsr, insn_3arg_fn_t *fn)
198 register long rr0 asm("r0") = r0;
199 register long rr1 asm("r1") = r1;
200 register long rr2 asm("r2") = r2;
201 register long ret asm("r0");
203 __asm__ __volatile__ (
204 "msr cpsr_fs, %[cpsr] \n\t"
208 : "0" (rr0), "r" (rr1), "r" (rr2),
209 [cpsr] "r" (cpsr), [fn] "r" (fn)
215 static inline long long __kprobes
216 insnslot_llret_3arg_rflags(long r0, long r1, long r2, long cpsr,
217 insn_llret_3arg_fn_t *fn)
219 register long rr0 asm("r0") = r0;
220 register long rr1 asm("r1") = r1;
221 register long rr2 asm("r2") = r2;
222 register long ret0 asm("r0");
223 register long ret1 asm("r1");
226 __asm__ __volatile__ (
227 "msr cpsr_fs, %[cpsr] \n\t"
230 : "=r" (ret0), "=r" (ret1)
231 : "0" (rr0), "r" (rr1), "r" (rr2),
232 [cpsr] "r" (cpsr), [fn] "r" (fn)
240 static inline long __kprobes
241 insnslot_4arg_rflags(long r0, long r1, long r2, long r3, long cpsr,
244 register long rr0 asm("r0") = r0;
245 register long rr1 asm("r1") = r1;
246 register long rr2 asm("r2") = r2;
247 register long rr3 asm("r3") = r3;
248 register long ret asm("r0");
250 __asm__ __volatile__ (
251 "msr cpsr_fs, %[cpsr] \n\t"
255 : "0" (rr0), "r" (rr1), "r" (rr2), "r" (rr3),
256 [cpsr] "r" (cpsr), [fn] "r" (fn)
262 static inline long __kprobes
263 insnslot_1arg_rwflags(long r0, long *cpsr, insn_1arg_fn_t *fn)
265 register long rr0 asm("r0") = r0;
266 register long ret asm("r0");
267 long oldcpsr = *cpsr;
270 __asm__ __volatile__ (
271 "msr cpsr_fs, %[oldcpsr] \n\t"
274 "mrs %[newcpsr], cpsr \n\t"
275 : "=r" (ret), [newcpsr] "=r" (newcpsr)
276 : "0" (rr0), [oldcpsr] "r" (oldcpsr), [fn] "r" (fn)
279 *cpsr = (oldcpsr & ~PSR_fs) | (newcpsr & PSR_fs);
283 static inline long __kprobes
284 insnslot_2arg_rwflags(long r0, long r1, long *cpsr, insn_2arg_fn_t *fn)
286 register long rr0 asm("r0") = r0;
287 register long rr1 asm("r1") = r1;
288 register long ret asm("r0");
289 long oldcpsr = *cpsr;
292 __asm__ __volatile__ (
293 "msr cpsr_fs, %[oldcpsr] \n\t"
296 "mrs %[newcpsr], cpsr \n\t"
297 : "=r" (ret), [newcpsr] "=r" (newcpsr)
298 : "0" (rr0), "r" (rr1), [oldcpsr] "r" (oldcpsr), [fn] "r" (fn)
301 *cpsr = (oldcpsr & ~PSR_fs) | (newcpsr & PSR_fs);
305 static inline long __kprobes
306 insnslot_3arg_rwflags(long r0, long r1, long r2, long *cpsr,
309 register long rr0 asm("r0") = r0;
310 register long rr1 asm("r1") = r1;
311 register long rr2 asm("r2") = r2;
312 register long ret asm("r0");
313 long oldcpsr = *cpsr;
316 __asm__ __volatile__ (
317 "msr cpsr_fs, %[oldcpsr] \n\t"
320 "mrs %[newcpsr], cpsr \n\t"
321 : "=r" (ret), [newcpsr] "=r" (newcpsr)
322 : "0" (rr0), "r" (rr1), "r" (rr2),
323 [oldcpsr] "r" (oldcpsr), [fn] "r" (fn)
326 *cpsr = (oldcpsr & ~PSR_fs) | (newcpsr & PSR_fs);
330 static inline long __kprobes
331 insnslot_4arg_rwflags(long r0, long r1, long r2, long r3, long *cpsr,
334 register long rr0 asm("r0") = r0;
335 register long rr1 asm("r1") = r1;
336 register long rr2 asm("r2") = r2;
337 register long rr3 asm("r3") = r3;
338 register long ret asm("r0");
339 long oldcpsr = *cpsr;
342 __asm__ __volatile__ (
343 "msr cpsr_fs, %[oldcpsr] \n\t"
346 "mrs %[newcpsr], cpsr \n\t"
347 : "=r" (ret), [newcpsr] "=r" (newcpsr)
348 : "0" (rr0), "r" (rr1), "r" (rr2), "r" (rr3),
349 [oldcpsr] "r" (oldcpsr), [fn] "r" (fn)
352 *cpsr = (oldcpsr & ~PSR_fs) | (newcpsr & PSR_fs);
356 static inline long long __kprobes
357 insnslot_llret_4arg_rwflags(long r0, long r1, long r2, long r3, long *cpsr,
358 insn_llret_4arg_fn_t *fn)
360 register long rr0 asm("r0") = r0;
361 register long rr1 asm("r1") = r1;
362 register long rr2 asm("r2") = r2;
363 register long rr3 asm("r3") = r3;
364 register long ret0 asm("r0");
365 register long ret1 asm("r1");
366 long oldcpsr = *cpsr;
370 __asm__ __volatile__ (
371 "msr cpsr_fs, %[oldcpsr] \n\t"
374 "mrs %[newcpsr], cpsr \n\t"
375 : "=r" (ret0), "=r" (ret1), [newcpsr] "=r" (newcpsr)
376 : "0" (rr0), "r" (rr1), "r" (rr2), "r" (rr3),
377 [oldcpsr] "r" (oldcpsr), [fn] "r" (fn)
380 *cpsr = (oldcpsr & ~PSR_fs) | (newcpsr & PSR_fs);
387 * To avoid the complications of mimicing single-stepping on a
388 * processor without a Next-PC or a single-step mode, and to
389 * avoid having to deal with the side-effects of boosting, we
390 * simulate or emulate (almost) all ARM instructions.
392 * "Simulation" is where the instruction's behavior is duplicated in
393 * C code. "Emulation" is where the original instruction is rewritten
394 * and executed, often by altering its registers.
396 * By having all behavior of the kprobe'd instruction completed before
397 * returning from the kprobe_handler(), all locks (scheduler and
398 * interrupt) can safely be released. There is no need for secondary
399 * breakpoints, no race with MP or preemptable kernels, nor having to
400 * clean up resources counts at a later time impacting overall system
401 * performance. By rewriting the instruction, only the minimum registers
402 * need to be loaded and saved back optimizing performance.
404 * Calling the insnslot_*_rwflags version of a function doesn't hurt
405 * anything even when the CPSR flags aren't updated by the
406 * instruction. It's just a little slower in return for saving
407 * a little space by not having a duplicate function that doesn't
408 * update the flags. (The same optimization can be said for
409 * instructions that do or don't perform register writeback)
410 * Also, instructions can either read the flags, only write the
411 * flags, or read and write the flags. To save combinations
412 * rather than for sheer performance, flag functions just assume
413 * read and write of flags.
416 static void __kprobes simulate_bbl(struct kprobe *p, struct pt_regs *regs)
418 kprobe_opcode_t insn = p->opcode;
419 long iaddr = (long)p->addr;
420 int disp = branch_displacement(insn);
422 if (insn & (1 << 24))
423 regs->ARM_lr = iaddr + 4;
425 regs->ARM_pc = iaddr + 8 + disp;
428 static void __kprobes simulate_blx1(struct kprobe *p, struct pt_regs *regs)
430 kprobe_opcode_t insn = p->opcode;
431 long iaddr = (long)p->addr;
432 int disp = branch_displacement(insn);
434 regs->ARM_lr = iaddr + 4;
435 regs->ARM_pc = iaddr + 8 + disp + ((insn >> 23) & 0x2);
436 regs->ARM_cpsr |= PSR_T_BIT;
439 static void __kprobes simulate_blx2bx(struct kprobe *p, struct pt_regs *regs)
441 kprobe_opcode_t insn = p->opcode;
443 long rmv = regs->uregs[rm];
446 regs->ARM_lr = (long)p->addr + 4;
448 regs->ARM_pc = rmv & ~0x1;
449 regs->ARM_cpsr &= ~PSR_T_BIT;
451 regs->ARM_cpsr |= PSR_T_BIT;
454 static void __kprobes simulate_mrs(struct kprobe *p, struct pt_regs *regs)
456 kprobe_opcode_t insn = p->opcode;
457 int rd = (insn >> 12) & 0xf;
458 unsigned long mask = 0xf8ff03df; /* Mask out execution state */
459 regs->uregs[rd] = regs->ARM_cpsr & mask;
462 static void __kprobes simulate_ldm1stm1(struct kprobe *p, struct pt_regs *regs)
464 kprobe_opcode_t insn = p->opcode;
465 int rn = (insn >> 16) & 0xf;
466 int lbit = insn & (1 << 20);
467 int wbit = insn & (1 << 21);
468 int ubit = insn & (1 << 23);
469 int pbit = insn & (1 << 24);
470 long *addr = (long *)regs->uregs[rn];
475 reg_bit_vector = insn & 0xffff;
476 while (reg_bit_vector) {
477 reg_bit_vector &= (reg_bit_vector - 1);
483 addr += (!pbit == !ubit);
485 reg_bit_vector = insn & 0xffff;
486 while (reg_bit_vector) {
487 int reg = __ffs(reg_bit_vector);
488 reg_bit_vector &= (reg_bit_vector - 1);
490 regs->uregs[reg] = *addr++;
492 *addr++ = regs->uregs[reg];
498 addr -= (!pbit == !ubit);
499 regs->uregs[rn] = (long)addr;
503 static void __kprobes simulate_stm1_pc(struct kprobe *p, struct pt_regs *regs)
505 regs->ARM_pc = (long)p->addr + str_pc_offset;
506 simulate_ldm1stm1(p, regs);
507 regs->ARM_pc = (long)p->addr + 4;
510 static void __kprobes simulate_mov_ipsp(struct kprobe *p, struct pt_regs *regs)
512 regs->uregs[12] = regs->uregs[13];
515 static void __kprobes emulate_ldcstc(struct kprobe *p, struct pt_regs *regs)
517 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
518 kprobe_opcode_t insn = p->opcode;
519 int rn = (insn >> 16) & 0xf;
520 long rnv = regs->uregs[rn];
522 /* Save Rn in case of writeback. */
523 regs->uregs[rn] = insnslot_1arg_rflags(rnv, regs->ARM_cpsr, i_fn);
526 static void __kprobes emulate_ldrd(struct kprobe *p, struct pt_regs *regs)
528 insn_2arg_fn_t *i_fn = (insn_2arg_fn_t *)&p->ainsn.insn[0];
529 kprobe_opcode_t insn = p->opcode;
530 long ppc = (long)p->addr + 8;
531 int rd = (insn >> 12) & 0xf;
532 int rn = (insn >> 16) & 0xf;
533 int rm = insn & 0xf; /* rm may be invalid, don't care. */
534 long rmv = (rm == 15) ? ppc : regs->uregs[rm];
535 long rnv = (rn == 15) ? ppc : regs->uregs[rn];
537 /* Not following the C calling convention here, so need asm(). */
538 __asm__ __volatile__ (
541 "msr cpsr_fs, %[cpsr]\n\t"
543 "mov pc, %[i_fn] \n\t"
544 "str r0, %[rn] \n\t" /* in case of writeback */
545 "str r2, %[rd0] \n\t"
546 "str r3, %[rd1] \n\t"
548 [rd0] "=m" (regs->uregs[rd]),
549 [rd1] "=m" (regs->uregs[rd+1])
551 [cpsr] "r" (regs->ARM_cpsr),
553 : "r0", "r1", "r2", "r3", "lr", "cc"
556 regs->uregs[rn] = rnv; /* Save Rn in case of writeback. */
559 static void __kprobes emulate_strd(struct kprobe *p, struct pt_regs *regs)
561 insn_4arg_fn_t *i_fn = (insn_4arg_fn_t *)&p->ainsn.insn[0];
562 kprobe_opcode_t insn = p->opcode;
563 long ppc = (long)p->addr + 8;
564 int rd = (insn >> 12) & 0xf;
565 int rn = (insn >> 16) & 0xf;
567 long rnv = (rn == 15) ? ppc : regs->uregs[rn];
568 /* rm/rmv may be invalid, don't care. */
569 long rmv = (rm == 15) ? ppc : regs->uregs[rm];
572 rnv_wb = insnslot_4arg_rflags(rnv, rmv, regs->uregs[rd],
574 regs->ARM_cpsr, i_fn);
576 regs->uregs[rn] = rnv_wb; /* Save Rn in case of writeback. */
579 static void __kprobes emulate_ldr(struct kprobe *p, struct pt_regs *regs)
581 insn_llret_3arg_fn_t *i_fn = (insn_llret_3arg_fn_t *)&p->ainsn.insn[0];
582 kprobe_opcode_t insn = p->opcode;
583 long ppc = (long)p->addr + 8;
585 int rd = (insn >> 12) & 0xf;
586 int rn = (insn >> 16) & 0xf;
589 long rnv = (rn == 15) ? ppc : regs->uregs[rn];
590 long rmv = (rm == 15) ? ppc : regs->uregs[rm];
591 long cpsr = regs->ARM_cpsr;
593 fnr.dr = insnslot_llret_3arg_rflags(rnv, 0, rmv, cpsr, i_fn);
595 regs->uregs[rn] = fnr.r0; /* Save Rn in case of writeback. */
599 #if __LINUX_ARM_ARCH__ >= 5
603 regs->ARM_cpsr = cpsr;
609 regs->uregs[rd] = rdv;
612 static void __kprobes emulate_str(struct kprobe *p, struct pt_regs *regs)
614 insn_3arg_fn_t *i_fn = (insn_3arg_fn_t *)&p->ainsn.insn[0];
615 kprobe_opcode_t insn = p->opcode;
616 long iaddr = (long)p->addr;
617 int rd = (insn >> 12) & 0xf;
618 int rn = (insn >> 16) & 0xf;
620 long rdv = (rd == 15) ? iaddr + str_pc_offset : regs->uregs[rd];
621 long rnv = (rn == 15) ? iaddr + 8 : regs->uregs[rn];
622 long rmv = regs->uregs[rm]; /* rm/rmv may be invalid, don't care. */
625 rnv_wb = insnslot_3arg_rflags(rnv, rdv, rmv, regs->ARM_cpsr, i_fn);
627 regs->uregs[rn] = rnv_wb; /* Save Rn in case of writeback. */
630 static void __kprobes emulate_mrrc(struct kprobe *p, struct pt_regs *regs)
632 insn_llret_0arg_fn_t *i_fn = (insn_llret_0arg_fn_t *)&p->ainsn.insn[0];
633 kprobe_opcode_t insn = p->opcode;
635 int rd = (insn >> 12) & 0xf;
636 int rn = (insn >> 16) & 0xf;
638 fnr.dr = insnslot_llret_0arg_rflags(regs->ARM_cpsr, i_fn);
639 regs->uregs[rn] = fnr.r0;
640 regs->uregs[rd] = fnr.r1;
643 static void __kprobes emulate_mcrr(struct kprobe *p, struct pt_regs *regs)
645 insn_2arg_fn_t *i_fn = (insn_2arg_fn_t *)&p->ainsn.insn[0];
646 kprobe_opcode_t insn = p->opcode;
647 int rd = (insn >> 12) & 0xf;
648 int rn = (insn >> 16) & 0xf;
649 long rnv = regs->uregs[rn];
650 long rdv = regs->uregs[rd];
652 insnslot_2arg_rflags(rnv, rdv, regs->ARM_cpsr, i_fn);
655 static void __kprobes emulate_sat(struct kprobe *p, struct pt_regs *regs)
657 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
658 kprobe_opcode_t insn = p->opcode;
659 int rd = (insn >> 12) & 0xf;
661 long rmv = regs->uregs[rm];
664 regs->uregs[rd] = insnslot_1arg_rwflags(rmv, ®s->ARM_cpsr, i_fn);
667 static void __kprobes emulate_sel(struct kprobe *p, struct pt_regs *regs)
669 insn_2arg_fn_t *i_fn = (insn_2arg_fn_t *)&p->ainsn.insn[0];
670 kprobe_opcode_t insn = p->opcode;
671 int rd = (insn >> 12) & 0xf;
672 int rn = (insn >> 16) & 0xf;
674 long rnv = regs->uregs[rn];
675 long rmv = regs->uregs[rm];
678 regs->uregs[rd] = insnslot_2arg_rflags(rnv, rmv, regs->ARM_cpsr, i_fn);
681 static void __kprobes emulate_none(struct kprobe *p, struct pt_regs *regs)
683 insn_0arg_fn_t *i_fn = (insn_0arg_fn_t *)&p->ainsn.insn[0];
685 insnslot_0arg_rflags(regs->ARM_cpsr, i_fn);
688 static void __kprobes emulate_rd12(struct kprobe *p, struct pt_regs *regs)
690 insn_0arg_fn_t *i_fn = (insn_0arg_fn_t *)&p->ainsn.insn[0];
691 kprobe_opcode_t insn = p->opcode;
692 int rd = (insn >> 12) & 0xf;
694 regs->uregs[rd] = insnslot_0arg_rflags(regs->ARM_cpsr, i_fn);
697 static void __kprobes emulate_ird12(struct kprobe *p, struct pt_regs *regs)
699 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
700 kprobe_opcode_t insn = p->opcode;
701 int ird = (insn >> 12) & 0xf;
703 insnslot_1arg_rflags(regs->uregs[ird], regs->ARM_cpsr, i_fn);
706 static void __kprobes emulate_rn16(struct kprobe *p, struct pt_regs *regs)
708 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
709 kprobe_opcode_t insn = p->opcode;
710 int rn = (insn >> 16) & 0xf;
711 long rnv = regs->uregs[rn];
713 insnslot_1arg_rflags(rnv, regs->ARM_cpsr, i_fn);
716 static void __kprobes emulate_rd12rm0(struct kprobe *p, struct pt_regs *regs)
718 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
719 kprobe_opcode_t insn = p->opcode;
720 int rd = (insn >> 12) & 0xf;
722 long rmv = regs->uregs[rm];
724 regs->uregs[rd] = insnslot_1arg_rflags(rmv, regs->ARM_cpsr, i_fn);
727 static void __kprobes
728 emulate_rd12rn16rm0_rwflags(struct kprobe *p, struct pt_regs *regs)
730 insn_2arg_fn_t *i_fn = (insn_2arg_fn_t *)&p->ainsn.insn[0];
731 kprobe_opcode_t insn = p->opcode;
732 int rd = (insn >> 12) & 0xf;
733 int rn = (insn >> 16) & 0xf;
735 long rnv = regs->uregs[rn];
736 long rmv = regs->uregs[rm];
739 insnslot_2arg_rwflags(rnv, rmv, ®s->ARM_cpsr, i_fn);
742 static void __kprobes
743 emulate_rd16rn12rs8rm0_rwflags(struct kprobe *p, struct pt_regs *regs)
745 insn_3arg_fn_t *i_fn = (insn_3arg_fn_t *)&p->ainsn.insn[0];
746 kprobe_opcode_t insn = p->opcode;
747 int rd = (insn >> 16) & 0xf;
748 int rn = (insn >> 12) & 0xf;
749 int rs = (insn >> 8) & 0xf;
751 long rnv = regs->uregs[rn];
752 long rsv = regs->uregs[rs];
753 long rmv = regs->uregs[rm];
756 insnslot_3arg_rwflags(rnv, rsv, rmv, ®s->ARM_cpsr, i_fn);
759 static void __kprobes
760 emulate_rd16rs8rm0_rwflags(struct kprobe *p, struct pt_regs *regs)
762 insn_2arg_fn_t *i_fn = (insn_2arg_fn_t *)&p->ainsn.insn[0];
763 kprobe_opcode_t insn = p->opcode;
764 int rd = (insn >> 16) & 0xf;
765 int rs = (insn >> 8) & 0xf;
767 long rsv = regs->uregs[rs];
768 long rmv = regs->uregs[rm];
771 insnslot_2arg_rwflags(rsv, rmv, ®s->ARM_cpsr, i_fn);
774 static void __kprobes
775 emulate_rdhi16rdlo12rs8rm0_rwflags(struct kprobe *p, struct pt_regs *regs)
777 insn_llret_4arg_fn_t *i_fn = (insn_llret_4arg_fn_t *)&p->ainsn.insn[0];
778 kprobe_opcode_t insn = p->opcode;
780 int rdhi = (insn >> 16) & 0xf;
781 int rdlo = (insn >> 12) & 0xf;
782 int rs = (insn >> 8) & 0xf;
784 long rsv = regs->uregs[rs];
785 long rmv = regs->uregs[rm];
787 fnr.dr = insnslot_llret_4arg_rwflags(regs->uregs[rdhi],
788 regs->uregs[rdlo], rsv, rmv,
789 ®s->ARM_cpsr, i_fn);
790 regs->uregs[rdhi] = fnr.r0;
791 regs->uregs[rdlo] = fnr.r1;
794 static void __kprobes
795 emulate_alu_imm_rflags(struct kprobe *p, struct pt_regs *regs)
797 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
798 kprobe_opcode_t insn = p->opcode;
799 int rd = (insn >> 12) & 0xf;
800 int rn = (insn >> 16) & 0xf;
801 long rnv = (rn == 15) ? (long)p->addr + 8 : regs->uregs[rn];
803 regs->uregs[rd] = insnslot_1arg_rflags(rnv, regs->ARM_cpsr, i_fn);
806 static void __kprobes
807 emulate_alu_imm_rwflags(struct kprobe *p, struct pt_regs *regs)
809 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
810 kprobe_opcode_t insn = p->opcode;
811 int rd = (insn >> 12) & 0xf;
812 int rn = (insn >> 16) & 0xf;
813 long rnv = (rn == 15) ? (long)p->addr + 8 : regs->uregs[rn];
815 regs->uregs[rd] = insnslot_1arg_rwflags(rnv, ®s->ARM_cpsr, i_fn);
818 static void __kprobes
819 emulate_alu_tests_imm(struct kprobe *p, struct pt_regs *regs)
821 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
822 kprobe_opcode_t insn = p->opcode;
823 int rn = (insn >> 16) & 0xf;
824 long rnv = (rn == 15) ? (long)p->addr + 8 : regs->uregs[rn];
826 insnslot_1arg_rwflags(rnv, ®s->ARM_cpsr, i_fn);
829 static void __kprobes
830 emulate_alu_rflags(struct kprobe *p, struct pt_regs *regs)
832 insn_3arg_fn_t *i_fn = (insn_3arg_fn_t *)&p->ainsn.insn[0];
833 kprobe_opcode_t insn = p->opcode;
834 long ppc = (long)p->addr + 8;
835 int rd = (insn >> 12) & 0xf;
836 int rn = (insn >> 16) & 0xf; /* rn/rnv/rs/rsv may be */
837 int rs = (insn >> 8) & 0xf; /* invalid, don't care. */
839 long rnv = (rn == 15) ? ppc : regs->uregs[rn];
840 long rmv = (rm == 15) ? ppc : regs->uregs[rm];
841 long rsv = regs->uregs[rs];
844 insnslot_3arg_rflags(rnv, rmv, rsv, regs->ARM_cpsr, i_fn);
847 static void __kprobes
848 emulate_alu_rwflags(struct kprobe *p, struct pt_regs *regs)
850 insn_3arg_fn_t *i_fn = (insn_3arg_fn_t *)&p->ainsn.insn[0];
851 kprobe_opcode_t insn = p->opcode;
852 long ppc = (long)p->addr + 8;
853 int rd = (insn >> 12) & 0xf;
854 int rn = (insn >> 16) & 0xf; /* rn/rnv/rs/rsv may be */
855 int rs = (insn >> 8) & 0xf; /* invalid, don't care. */
857 long rnv = (rn == 15) ? ppc : regs->uregs[rn];
858 long rmv = (rm == 15) ? ppc : regs->uregs[rm];
859 long rsv = regs->uregs[rs];
862 insnslot_3arg_rwflags(rnv, rmv, rsv, ®s->ARM_cpsr, i_fn);
865 static void __kprobes
866 emulate_alu_tests(struct kprobe *p, struct pt_regs *regs)
868 insn_3arg_fn_t *i_fn = (insn_3arg_fn_t *)&p->ainsn.insn[0];
869 kprobe_opcode_t insn = p->opcode;
870 long ppc = (long)p->addr + 8;
871 int rn = (insn >> 16) & 0xf;
872 int rs = (insn >> 8) & 0xf; /* rs/rsv may be invalid, don't care. */
874 long rnv = (rn == 15) ? ppc : regs->uregs[rn];
875 long rmv = (rm == 15) ? ppc : regs->uregs[rm];
876 long rsv = regs->uregs[rs];
878 insnslot_3arg_rwflags(rnv, rmv, rsv, ®s->ARM_cpsr, i_fn);
881 static enum kprobe_insn __kprobes
882 prep_emulate_ldr_str(kprobe_opcode_t insn, struct arch_specific_insn *asi)
884 int ibit = (insn & (1 << 26)) ? 25 : 22;
887 insn |= 0x00001000; /* Rn = r0, Rd = r1 */
888 if (insn & (1 << ibit)) {
890 insn |= 2; /* Rm = r2 */
893 asi->insn_handler = (insn & (1 << 20)) ? emulate_ldr : emulate_str;
897 static enum kprobe_insn __kprobes
898 prep_emulate_rd12rm0(kprobe_opcode_t insn, struct arch_specific_insn *asi)
900 insn &= 0xffff0ff0; /* Rd = r0, Rm = r0 */
902 asi->insn_handler = emulate_rd12rm0;
906 static enum kprobe_insn __kprobes
907 prep_emulate_rd12rn16rm0_wflags(kprobe_opcode_t insn,
908 struct arch_specific_insn *asi)
910 insn &= 0xfff00ff0; /* Rd = r0, Rn = r0 */
911 insn |= 0x00000001; /* Rm = r1 */
913 asi->insn_handler = emulate_rd12rn16rm0_rwflags;
917 static enum kprobe_insn __kprobes
918 prep_emulate_rd16rs8rm0_wflags(kprobe_opcode_t insn,
919 struct arch_specific_insn *asi)
921 insn &= 0xfff0f0f0; /* Rd = r0, Rs = r0 */
922 insn |= 0x00000001; /* Rm = r1 */
924 asi->insn_handler = emulate_rd16rs8rm0_rwflags;
928 static enum kprobe_insn __kprobes
929 prep_emulate_rd16rn12rs8rm0_wflags(kprobe_opcode_t insn,
930 struct arch_specific_insn *asi)
932 insn &= 0xfff000f0; /* Rd = r0, Rn = r0 */
933 insn |= 0x00000102; /* Rs = r1, Rm = r2 */
935 asi->insn_handler = emulate_rd16rn12rs8rm0_rwflags;
939 static enum kprobe_insn __kprobes
940 prep_emulate_rdhi16rdlo12rs8rm0_wflags(kprobe_opcode_t insn,
941 struct arch_specific_insn *asi)
943 insn &= 0xfff000f0; /* RdHi = r0, RdLo = r1 */
944 insn |= 0x00001203; /* Rs = r2, Rm = r3 */
946 asi->insn_handler = emulate_rdhi16rdlo12rs8rm0_rwflags;
951 * For the instruction masking and comparisons in all the "space_*"
952 * functions below, Do _not_ rearrange the order of tests unless
953 * you're very, very sure of what you are doing. For the sake of
954 * efficiency, the masks for some tests sometimes assume other test
955 * have been done prior to them so the number of patterns to test
956 * for an instruction set can be as broad as possible to reduce the
957 * number of tests needed.
960 static enum kprobe_insn __kprobes
961 space_1111(kprobe_opcode_t insn, struct arch_specific_insn *asi)
963 /* CPS mmod == 1 : 1111 0001 0000 xx10 xxxx xxxx xx0x xxxx */
964 /* RFE : 1111 100x x0x1 xxxx xxxx 1010 xxxx xxxx */
965 /* SRS : 1111 100x x1x0 1101 xxxx 0101 xxxx xxxx */
966 if ((insn & 0xfff30020) == 0xf1020000 ||
967 (insn & 0xfe500f00) == 0xf8100a00 ||
968 (insn & 0xfe5f0f00) == 0xf84d0500)
969 return INSN_REJECTED;
971 /* PLD : 1111 01x1 x101 xxxx xxxx xxxx xxxx xxxx : */
972 if ((insn & 0xfd700000) == 0xf4500000) {
973 insn &= 0xfff0ffff; /* Rn = r0 */
975 asi->insn_handler = emulate_rn16;
979 /* BLX(1) : 1111 101x xxxx xxxx xxxx xxxx xxxx xxxx : */
980 if ((insn & 0xfe000000) == 0xfa000000) {
981 asi->insn_handler = simulate_blx1;
982 return INSN_GOOD_NO_SLOT;
985 /* SETEND : 1111 0001 0000 0001 xxxx xxxx 0000 xxxx */
986 /* CDP2 : 1111 1110 xxxx xxxx xxxx xxxx xxx0 xxxx */
987 if ((insn & 0xffff00f0) == 0xf1010000 ||
988 (insn & 0xff000010) == 0xfe000000) {
990 asi->insn_handler = emulate_none;
994 /* MCRR2 : 1111 1100 0100 xxxx xxxx xxxx xxxx xxxx : (Rd != Rn) */
995 /* MRRC2 : 1111 1100 0101 xxxx xxxx xxxx xxxx xxxx : (Rd != Rn) */
996 if ((insn & 0xffe00000) == 0xfc400000) {
997 insn &= 0xfff00fff; /* Rn = r0 */
998 insn |= 0x00001000; /* Rd = r1 */
1001 (insn & (1 << 20)) ? emulate_mrrc : emulate_mcrr;
1005 /* LDC2 : 1111 110x xxx1 xxxx xxxx xxxx xxxx xxxx */
1006 /* STC2 : 1111 110x xxx0 xxxx xxxx xxxx xxxx xxxx */
1007 if ((insn & 0xfe000000) == 0xfc000000) {
1008 insn &= 0xfff0ffff; /* Rn = r0 */
1009 asi->insn[0] = insn;
1010 asi->insn_handler = emulate_ldcstc;
1014 /* MCR2 : 1111 1110 xxx0 xxxx xxxx xxxx xxx1 xxxx */
1015 /* MRC2 : 1111 1110 xxx1 xxxx xxxx xxxx xxx1 xxxx */
1016 insn &= 0xffff0fff; /* Rd = r0 */
1017 asi->insn[0] = insn;
1018 asi->insn_handler = (insn & (1 << 20)) ? emulate_rd12 : emulate_ird12;
1022 static enum kprobe_insn __kprobes
1023 space_cccc_000x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1025 /* cccc 0001 0xx0 xxxx xxxx xxxx xxxx xxx0 xxxx */
1026 if ((insn & 0x0f900010) == 0x01000000) {
1028 /* BXJ : cccc 0001 0010 xxxx xxxx xxxx 0010 xxxx */
1029 /* MSR : cccc 0001 0x10 xxxx xxxx xxxx 0000 xxxx */
1030 /* MRS spsr : cccc 0001 0100 xxxx xxxx xxxx 0000 xxxx */
1031 if ((insn & 0x0ff000f0) == 0x01200020 ||
1032 (insn & 0x0fb000f0) == 0x01200000 ||
1033 (insn & 0x0ff000f0) == 0x01400000)
1034 return INSN_REJECTED;
1036 /* MRS cpsr : cccc 0001 0000 xxxx xxxx xxxx 0000 xxxx */
1037 if ((insn & 0x0ff000f0) == 0x01000000) {
1038 asi->insn_handler = simulate_mrs;
1039 return INSN_GOOD_NO_SLOT;
1042 /* SMLALxy : cccc 0001 0100 xxxx xxxx xxxx 1xx0 xxxx */
1043 if ((insn & 0x0ff00090) == 0x01400080)
1044 return prep_emulate_rdhi16rdlo12rs8rm0_wflags(insn, asi);
1046 /* SMULWy : cccc 0001 0010 xxxx xxxx xxxx 1x10 xxxx */
1047 /* SMULxy : cccc 0001 0110 xxxx xxxx xxxx 1xx0 xxxx */
1048 if ((insn & 0x0ff000b0) == 0x012000a0 ||
1049 (insn & 0x0ff00090) == 0x01600080)
1050 return prep_emulate_rd16rs8rm0_wflags(insn, asi);
1052 /* SMLAxy : cccc 0001 0000 xxxx xxxx xxxx 1xx0 xxxx : Q */
1053 /* SMLAWy : cccc 0001 0010 xxxx xxxx xxxx 0x00 xxxx : Q */
1054 return prep_emulate_rd16rn12rs8rm0_wflags(insn, asi);
1058 /* cccc 0001 0xx0 xxxx xxxx xxxx xxxx 0xx1 xxxx */
1059 else if ((insn & 0x0f900090) == 0x01000010) {
1061 /* BKPT : 1110 0001 0010 xxxx xxxx xxxx 0111 xxxx */
1062 if ((insn & 0xfff000f0) == 0xe1200070)
1063 return INSN_REJECTED;
1065 /* BLX(2) : cccc 0001 0010 xxxx xxxx xxxx 0011 xxxx */
1066 /* BX : cccc 0001 0010 xxxx xxxx xxxx 0001 xxxx */
1067 if ((insn & 0x0ff000d0) == 0x01200010) {
1068 asi->insn_handler = simulate_blx2bx;
1069 return INSN_GOOD_NO_SLOT;
1072 /* CLZ : cccc 0001 0110 xxxx xxxx xxxx 0001 xxxx */
1073 if ((insn & 0x0ff000f0) == 0x01600010)
1074 return prep_emulate_rd12rm0(insn, asi);
1076 /* QADD : cccc 0001 0000 xxxx xxxx xxxx 0101 xxxx :Q */
1077 /* QSUB : cccc 0001 0010 xxxx xxxx xxxx 0101 xxxx :Q */
1078 /* QDADD : cccc 0001 0100 xxxx xxxx xxxx 0101 xxxx :Q */
1079 /* QDSUB : cccc 0001 0110 xxxx xxxx xxxx 0101 xxxx :Q */
1080 return prep_emulate_rd12rn16rm0_wflags(insn, asi);
1083 /* cccc 0000 xxxx xxxx xxxx xxxx xxxx 1001 xxxx */
1084 else if ((insn & 0x0f000090) == 0x00000090) {
1086 /* MUL : cccc 0000 0000 xxxx xxxx xxxx 1001 xxxx : */
1087 /* MULS : cccc 0000 0001 xxxx xxxx xxxx 1001 xxxx :cc */
1088 /* MLA : cccc 0000 0010 xxxx xxxx xxxx 1001 xxxx : */
1089 /* MLAS : cccc 0000 0011 xxxx xxxx xxxx 1001 xxxx :cc */
1090 /* UMAAL : cccc 0000 0100 xxxx xxxx xxxx 1001 xxxx : */
1091 /* UMULL : cccc 0000 1000 xxxx xxxx xxxx 1001 xxxx : */
1092 /* UMULLS : cccc 0000 1001 xxxx xxxx xxxx 1001 xxxx :cc */
1093 /* UMLAL : cccc 0000 1010 xxxx xxxx xxxx 1001 xxxx : */
1094 /* UMLALS : cccc 0000 1011 xxxx xxxx xxxx 1001 xxxx :cc */
1095 /* SMULL : cccc 0000 1100 xxxx xxxx xxxx 1001 xxxx : */
1096 /* SMULLS : cccc 0000 1101 xxxx xxxx xxxx 1001 xxxx :cc */
1097 /* SMLAL : cccc 0000 1110 xxxx xxxx xxxx 1001 xxxx : */
1098 /* SMLALS : cccc 0000 1111 xxxx xxxx xxxx 1001 xxxx :cc */
1099 if ((insn & 0x0fe000f0) == 0x00000090) {
1100 return prep_emulate_rd16rs8rm0_wflags(insn, asi);
1101 } else if ((insn & 0x0fe000f0) == 0x00200090) {
1102 return prep_emulate_rd16rn12rs8rm0_wflags(insn, asi);
1104 return prep_emulate_rdhi16rdlo12rs8rm0_wflags(insn, asi);
1108 /* cccc 000x xxxx xxxx xxxx xxxx xxxx 1xx1 xxxx */
1109 else if ((insn & 0x0e000090) == 0x00000090) {
1111 /* SWP : cccc 0001 0000 xxxx xxxx xxxx 1001 xxxx */
1112 /* SWPB : cccc 0001 0100 xxxx xxxx xxxx 1001 xxxx */
1113 /* LDRD : cccc 000x xxx0 xxxx xxxx xxxx 1101 xxxx */
1114 /* STRD : cccc 000x xxx0 xxxx xxxx xxxx 1111 xxxx */
1115 /* STREX : cccc 0001 1000 xxxx xxxx xxxx 1001 xxxx */
1116 /* LDREX : cccc 0001 1001 xxxx xxxx xxxx 1001 xxxx */
1117 /* LDRH : cccc 000x xxx1 xxxx xxxx xxxx 1011 xxxx */
1118 /* STRH : cccc 000x xxx0 xxxx xxxx xxxx 1011 xxxx */
1119 /* LDRSB : cccc 000x xxx1 xxxx xxxx xxxx 1101 xxxx */
1120 /* LDRSH : cccc 000x xxx1 xxxx xxxx xxxx 1111 xxxx */
1121 if ((insn & 0x0fb000f0) == 0x01000090) {
1123 return prep_emulate_rd12rn16rm0_wflags(insn, asi);
1124 } else if ((insn & 0x0e1000d0) == 0x00000d0) {
1127 insn |= 0x00002000; /* Rn = r0, Rd = r2 */
1128 if (insn & (1 << 22)) {
1131 insn |= 1; /* Rm = r1 */
1133 asi->insn[0] = insn;
1135 (insn & (1 << 5)) ? emulate_strd : emulate_ldrd;
1139 return prep_emulate_ldr_str(insn, asi);
1142 /* cccc 000x xxxx xxxx xxxx xxxx xxxx xxxx xxxx */
1145 * ALU op with S bit and Rd == 15 :
1146 * cccc 000x xxx1 xxxx 1111 xxxx xxxx xxxx
1148 if ((insn & 0x0e10f000) == 0x0010f000)
1149 return INSN_REJECTED;
1152 * "mov ip, sp" is the most common kprobe'd instruction by far.
1153 * Check and optimize for it explicitly.
1155 if (insn == 0xe1a0c00d) {
1156 asi->insn_handler = simulate_mov_ipsp;
1157 return INSN_GOOD_NO_SLOT;
1161 * Data processing: Immediate-shift / Register-shift
1162 * ALU op : cccc 000x xxxx xxxx xxxx xxxx xxxx xxxx
1163 * CPY : cccc 0001 1010 xxxx xxxx 0000 0000 xxxx
1164 * MOV : cccc 0001 101x xxxx xxxx xxxx xxxx xxxx
1165 * *S (bit 20) updates condition codes
1166 * ADC/SBC/RSC reads the C flag
1168 insn &= 0xfff00ff0; /* Rn = r0, Rd = r0 */
1169 insn |= 0x00000001; /* Rm = r1 */
1171 insn &= 0xfffff0ff; /* register shift */
1172 insn |= 0x00000200; /* Rs = r2 */
1174 asi->insn[0] = insn;
1176 if ((insn & 0x0f900000) == 0x01100000) {
1178 * TST : cccc 0001 0001 xxxx xxxx xxxx xxxx xxxx
1179 * TEQ : cccc 0001 0011 xxxx xxxx xxxx xxxx xxxx
1180 * CMP : cccc 0001 0101 xxxx xxxx xxxx xxxx xxxx
1181 * CMN : cccc 0001 0111 xxxx xxxx xxxx xxxx xxxx
1183 asi->insn_handler = emulate_alu_tests;
1185 /* ALU ops which write to Rd */
1186 asi->insn_handler = (insn & (1 << 20)) ? /* S-bit */
1187 emulate_alu_rwflags : emulate_alu_rflags;
1192 static enum kprobe_insn __kprobes
1193 space_cccc_001x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1196 * MSR : cccc 0011 0x10 xxxx xxxx xxxx xxxx xxxx
1197 * Undef : cccc 0011 0100 xxxx xxxx xxxx xxxx xxxx
1198 * ALU op with S bit and Rd == 15 :
1199 * cccc 001x xxx1 xxxx 1111 xxxx xxxx xxxx
1201 if ((insn & 0x0fb00000) == 0x03200000 || /* MSR */
1202 (insn & 0x0ff00000) == 0x03400000 || /* Undef */
1203 (insn & 0x0e10f000) == 0x0210f000) /* ALU s-bit, R15 */
1204 return INSN_REJECTED;
1207 * Data processing: 32-bit Immediate
1208 * ALU op : cccc 001x xxxx xxxx xxxx xxxx xxxx xxxx
1209 * MOV : cccc 0011 101x xxxx xxxx xxxx xxxx xxxx
1210 * *S (bit 20) updates condition codes
1211 * ADC/SBC/RSC reads the C flag
1213 insn &= 0xfff00fff; /* Rn = r0 and Rd = r0 */
1214 asi->insn[0] = insn;
1216 if ((insn & 0x0f900000) == 0x03100000) {
1218 * TST : cccc 0011 0001 xxxx xxxx xxxx xxxx xxxx
1219 * TEQ : cccc 0011 0011 xxxx xxxx xxxx xxxx xxxx
1220 * CMP : cccc 0011 0101 xxxx xxxx xxxx xxxx xxxx
1221 * CMN : cccc 0011 0111 xxxx xxxx xxxx xxxx xxxx
1223 asi->insn_handler = emulate_alu_tests_imm;
1225 /* ALU ops which write to Rd */
1226 asi->insn_handler = (insn & (1 << 20)) ? /* S-bit */
1227 emulate_alu_imm_rwflags : emulate_alu_imm_rflags;
1232 static enum kprobe_insn __kprobes
1233 space_cccc_0110__1(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1235 /* SEL : cccc 0110 1000 xxxx xxxx xxxx 1011 xxxx GE: !!! */
1236 if ((insn & 0x0ff000f0) == 0x068000b0) {
1237 insn &= 0xfff00ff0; /* Rd = r0, Rn = r0 */
1238 insn |= 0x00000001; /* Rm = r1 */
1239 asi->insn[0] = insn;
1240 asi->insn_handler = emulate_sel;
1244 /* SSAT : cccc 0110 101x xxxx xxxx xxxx xx01 xxxx :Q */
1245 /* USAT : cccc 0110 111x xxxx xxxx xxxx xx01 xxxx :Q */
1246 /* SSAT16 : cccc 0110 1010 xxxx xxxx xxxx 0011 xxxx :Q */
1247 /* USAT16 : cccc 0110 1110 xxxx xxxx xxxx 0011 xxxx :Q */
1248 if ((insn & 0x0fa00030) == 0x06a00010 ||
1249 (insn & 0x0fb000f0) == 0x06a00030) {
1250 insn &= 0xffff0ff0; /* Rd = r0, Rm = r0 */
1251 asi->insn[0] = insn;
1252 asi->insn_handler = emulate_sat;
1256 /* REV : cccc 0110 1011 xxxx xxxx xxxx 0011 xxxx */
1257 /* REV16 : cccc 0110 1011 xxxx xxxx xxxx 1011 xxxx */
1258 /* REVSH : cccc 0110 1111 xxxx xxxx xxxx 1011 xxxx */
1259 if ((insn & 0x0ff00070) == 0x06b00030 ||
1260 (insn & 0x0ff000f0) == 0x06f000b0)
1261 return prep_emulate_rd12rm0(insn, asi);
1263 /* SADD16 : cccc 0110 0001 xxxx xxxx xxxx 0001 xxxx :GE */
1264 /* SADDSUBX : cccc 0110 0001 xxxx xxxx xxxx 0011 xxxx :GE */
1265 /* SSUBADDX : cccc 0110 0001 xxxx xxxx xxxx 0101 xxxx :GE */
1266 /* SSUB16 : cccc 0110 0001 xxxx xxxx xxxx 0111 xxxx :GE */
1267 /* SADD8 : cccc 0110 0001 xxxx xxxx xxxx 1001 xxxx :GE */
1268 /* SSUB8 : cccc 0110 0001 xxxx xxxx xxxx 1111 xxxx :GE */
1269 /* QADD16 : cccc 0110 0010 xxxx xxxx xxxx 0001 xxxx : */
1270 /* QADDSUBX : cccc 0110 0010 xxxx xxxx xxxx 0011 xxxx : */
1271 /* QSUBADDX : cccc 0110 0010 xxxx xxxx xxxx 0101 xxxx : */
1272 /* QSUB16 : cccc 0110 0010 xxxx xxxx xxxx 0111 xxxx : */
1273 /* QADD8 : cccc 0110 0010 xxxx xxxx xxxx 1001 xxxx : */
1274 /* QSUB8 : cccc 0110 0010 xxxx xxxx xxxx 1111 xxxx : */
1275 /* SHADD16 : cccc 0110 0011 xxxx xxxx xxxx 0001 xxxx : */
1276 /* SHADDSUBX : cccc 0110 0011 xxxx xxxx xxxx 0011 xxxx : */
1277 /* SHSUBADDX : cccc 0110 0011 xxxx xxxx xxxx 0101 xxxx : */
1278 /* SHSUB16 : cccc 0110 0011 xxxx xxxx xxxx 0111 xxxx : */
1279 /* SHADD8 : cccc 0110 0011 xxxx xxxx xxxx 1001 xxxx : */
1280 /* SHSUB8 : cccc 0110 0011 xxxx xxxx xxxx 1111 xxxx : */
1281 /* UADD16 : cccc 0110 0101 xxxx xxxx xxxx 0001 xxxx :GE */
1282 /* UADDSUBX : cccc 0110 0101 xxxx xxxx xxxx 0011 xxxx :GE */
1283 /* USUBADDX : cccc 0110 0101 xxxx xxxx xxxx 0101 xxxx :GE */
1284 /* USUB16 : cccc 0110 0101 xxxx xxxx xxxx 0111 xxxx :GE */
1285 /* UADD8 : cccc 0110 0101 xxxx xxxx xxxx 1001 xxxx :GE */
1286 /* USUB8 : cccc 0110 0101 xxxx xxxx xxxx 1111 xxxx :GE */
1287 /* UQADD16 : cccc 0110 0110 xxxx xxxx xxxx 0001 xxxx : */
1288 /* UQADDSUBX : cccc 0110 0110 xxxx xxxx xxxx 0011 xxxx : */
1289 /* UQSUBADDX : cccc 0110 0110 xxxx xxxx xxxx 0101 xxxx : */
1290 /* UQSUB16 : cccc 0110 0110 xxxx xxxx xxxx 0111 xxxx : */
1291 /* UQADD8 : cccc 0110 0110 xxxx xxxx xxxx 1001 xxxx : */
1292 /* UQSUB8 : cccc 0110 0110 xxxx xxxx xxxx 1111 xxxx : */
1293 /* UHADD16 : cccc 0110 0111 xxxx xxxx xxxx 0001 xxxx : */
1294 /* UHADDSUBX : cccc 0110 0111 xxxx xxxx xxxx 0011 xxxx : */
1295 /* UHSUBADDX : cccc 0110 0111 xxxx xxxx xxxx 0101 xxxx : */
1296 /* UHSUB16 : cccc 0110 0111 xxxx xxxx xxxx 0111 xxxx : */
1297 /* UHADD8 : cccc 0110 0111 xxxx xxxx xxxx 1001 xxxx : */
1298 /* UHSUB8 : cccc 0110 0111 xxxx xxxx xxxx 1111 xxxx : */
1299 /* PKHBT : cccc 0110 1000 xxxx xxxx xxxx x001 xxxx : */
1300 /* PKHTB : cccc 0110 1000 xxxx xxxx xxxx x101 xxxx : */
1301 /* SXTAB16 : cccc 0110 1000 xxxx xxxx xxxx 0111 xxxx : */
1302 /* SXTB : cccc 0110 1010 xxxx xxxx xxxx 0111 xxxx : */
1303 /* SXTAB : cccc 0110 1010 xxxx xxxx xxxx 0111 xxxx : */
1304 /* SXTAH : cccc 0110 1011 xxxx xxxx xxxx 0111 xxxx : */
1305 /* UXTAB16 : cccc 0110 1100 xxxx xxxx xxxx 0111 xxxx : */
1306 /* UXTAB : cccc 0110 1110 xxxx xxxx xxxx 0111 xxxx : */
1307 /* UXTAH : cccc 0110 1111 xxxx xxxx xxxx 0111 xxxx : */
1308 return prep_emulate_rd12rn16rm0_wflags(insn, asi);
1311 static enum kprobe_insn __kprobes
1312 space_cccc_0111__1(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1314 /* Undef : cccc 0111 1111 xxxx xxxx xxxx 1111 xxxx */
1315 if ((insn & 0x0ff000f0) == 0x03f000f0)
1316 return INSN_REJECTED;
1318 /* USADA8 : cccc 0111 1000 xxxx xxxx xxxx 0001 xxxx */
1319 /* USAD8 : cccc 0111 1000 xxxx 1111 xxxx 0001 xxxx */
1320 if ((insn & 0x0ff000f0) == 0x07800010)
1321 return prep_emulate_rd16rn12rs8rm0_wflags(insn, asi);
1323 /* SMLALD : cccc 0111 0100 xxxx xxxx xxxx 00x1 xxxx */
1324 /* SMLSLD : cccc 0111 0100 xxxx xxxx xxxx 01x1 xxxx */
1325 if ((insn & 0x0ff00090) == 0x07400010)
1326 return prep_emulate_rdhi16rdlo12rs8rm0_wflags(insn, asi);
1328 /* SMLAD : cccc 0111 0000 xxxx xxxx xxxx 00x1 xxxx :Q */
1329 /* SMLSD : cccc 0111 0000 xxxx xxxx xxxx 01x1 xxxx :Q */
1330 /* SMMLA : cccc 0111 0101 xxxx xxxx xxxx 00x1 xxxx : */
1331 /* SMMLS : cccc 0111 0101 xxxx xxxx xxxx 11x1 xxxx : */
1332 if ((insn & 0x0ff00090) == 0x07000010 ||
1333 (insn & 0x0ff000d0) == 0x07500010 ||
1334 (insn & 0x0ff000d0) == 0x075000d0)
1335 return prep_emulate_rd16rn12rs8rm0_wflags(insn, asi);
1337 /* SMUSD : cccc 0111 0000 xxxx xxxx xxxx 01x1 xxxx : */
1338 /* SMUAD : cccc 0111 0000 xxxx 1111 xxxx 00x1 xxxx :Q */
1339 /* SMMUL : cccc 0111 0101 xxxx 1111 xxxx 00x1 xxxx : */
1340 return prep_emulate_rd16rs8rm0_wflags(insn, asi);
1343 static enum kprobe_insn __kprobes
1344 space_cccc_01xx(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1346 /* LDR : cccc 01xx x0x1 xxxx xxxx xxxx xxxx xxxx */
1347 /* LDRB : cccc 01xx x1x1 xxxx xxxx xxxx xxxx xxxx */
1348 /* LDRBT : cccc 01x0 x111 xxxx xxxx xxxx xxxx xxxx */
1349 /* LDRT : cccc 01x0 x011 xxxx xxxx xxxx xxxx xxxx */
1350 /* STR : cccc 01xx x0x0 xxxx xxxx xxxx xxxx xxxx */
1351 /* STRB : cccc 01xx x1x0 xxxx xxxx xxxx xxxx xxxx */
1352 /* STRBT : cccc 01x0 x110 xxxx xxxx xxxx xxxx xxxx */
1353 /* STRT : cccc 01x0 x010 xxxx xxxx xxxx xxxx xxxx */
1354 return prep_emulate_ldr_str(insn, asi);
1357 static enum kprobe_insn __kprobes
1358 space_cccc_100x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1360 /* LDM(2) : cccc 100x x101 xxxx 0xxx xxxx xxxx xxxx */
1361 /* LDM(3) : cccc 100x x1x1 xxxx 1xxx xxxx xxxx xxxx */
1362 if ((insn & 0x0e708000) == 0x85000000 ||
1363 (insn & 0x0e508000) == 0x85010000)
1364 return INSN_REJECTED;
1366 /* LDM(1) : cccc 100x x0x1 xxxx xxxx xxxx xxxx xxxx */
1367 /* STM(1) : cccc 100x x0x0 xxxx xxxx xxxx xxxx xxxx */
1368 asi->insn_handler = ((insn & 0x108000) == 0x008000) ? /* STM & R15 */
1369 simulate_stm1_pc : simulate_ldm1stm1;
1370 return INSN_GOOD_NO_SLOT;
1373 static enum kprobe_insn __kprobes
1374 space_cccc_101x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1376 /* B : cccc 1010 xxxx xxxx xxxx xxxx xxxx xxxx */
1377 /* BL : cccc 1011 xxxx xxxx xxxx xxxx xxxx xxxx */
1378 asi->insn_handler = simulate_bbl;
1379 return INSN_GOOD_NO_SLOT;
1382 static enum kprobe_insn __kprobes
1383 space_cccc_1100_010x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1385 /* MCRR : cccc 1100 0100 xxxx xxxx xxxx xxxx xxxx : (Rd!=Rn) */
1386 /* MRRC : cccc 1100 0101 xxxx xxxx xxxx xxxx xxxx : (Rd!=Rn) */
1388 insn |= 0x00001000; /* Rn = r0, Rd = r1 */
1389 asi->insn[0] = insn;
1390 asi->insn_handler = (insn & (1 << 20)) ? emulate_mrrc : emulate_mcrr;
1394 static enum kprobe_insn __kprobes
1395 space_cccc_110x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1397 /* LDC : cccc 110x xxx1 xxxx xxxx xxxx xxxx xxxx */
1398 /* STC : cccc 110x xxx0 xxxx xxxx xxxx xxxx xxxx */
1399 insn &= 0xfff0ffff; /* Rn = r0 */
1400 asi->insn[0] = insn;
1401 asi->insn_handler = emulate_ldcstc;
1405 static enum kprobe_insn __kprobes
1406 space_cccc_111x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1408 /* BKPT : 1110 0001 0010 xxxx xxxx xxxx 0111 xxxx */
1409 /* SWI : cccc 1111 xxxx xxxx xxxx xxxx xxxx xxxx */
1410 if ((insn & 0xfff000f0) == 0xe1200070 ||
1411 (insn & 0x0f000000) == 0x0f000000)
1412 return INSN_REJECTED;
1414 /* CDP : cccc 1110 xxxx xxxx xxxx xxxx xxx0 xxxx */
1415 if ((insn & 0x0f000010) == 0x0e000000) {
1416 asi->insn[0] = insn;
1417 asi->insn_handler = emulate_none;
1421 /* MCR : cccc 1110 xxx0 xxxx xxxx xxxx xxx1 xxxx */
1422 /* MRC : cccc 1110 xxx1 xxxx xxxx xxxx xxx1 xxxx */
1423 insn &= 0xffff0fff; /* Rd = r0 */
1424 asi->insn[0] = insn;
1425 asi->insn_handler = (insn & (1 << 20)) ? emulate_rd12 : emulate_ird12;
1429 static unsigned long __kprobes __check_eq(unsigned long cpsr)
1431 return cpsr & PSR_Z_BIT;
1434 static unsigned long __kprobes __check_ne(unsigned long cpsr)
1436 return (~cpsr) & PSR_Z_BIT;
1439 static unsigned long __kprobes __check_cs(unsigned long cpsr)
1441 return cpsr & PSR_C_BIT;
1444 static unsigned long __kprobes __check_cc(unsigned long cpsr)
1446 return (~cpsr) & PSR_C_BIT;
1449 static unsigned long __kprobes __check_mi(unsigned long cpsr)
1451 return cpsr & PSR_N_BIT;
1454 static unsigned long __kprobes __check_pl(unsigned long cpsr)
1456 return (~cpsr) & PSR_N_BIT;
1459 static unsigned long __kprobes __check_vs(unsigned long cpsr)
1461 return cpsr & PSR_V_BIT;
1464 static unsigned long __kprobes __check_vc(unsigned long cpsr)
1466 return (~cpsr) & PSR_V_BIT;
1469 static unsigned long __kprobes __check_hi(unsigned long cpsr)
1471 cpsr &= ~(cpsr >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */
1472 return cpsr & PSR_C_BIT;
1475 static unsigned long __kprobes __check_ls(unsigned long cpsr)
1477 cpsr &= ~(cpsr >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */
1478 return (~cpsr) & PSR_C_BIT;
1481 static unsigned long __kprobes __check_ge(unsigned long cpsr)
1483 cpsr ^= (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
1484 return (~cpsr) & PSR_N_BIT;
1487 static unsigned long __kprobes __check_lt(unsigned long cpsr)
1489 cpsr ^= (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
1490 return cpsr & PSR_N_BIT;
1493 static unsigned long __kprobes __check_gt(unsigned long cpsr)
1495 unsigned long temp = cpsr ^ (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
1496 temp |= (cpsr << 1); /* PSR_N_BIT |= PSR_Z_BIT */
1497 return (~temp) & PSR_N_BIT;
1500 static unsigned long __kprobes __check_le(unsigned long cpsr)
1502 unsigned long temp = cpsr ^ (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
1503 temp |= (cpsr << 1); /* PSR_N_BIT |= PSR_Z_BIT */
1504 return temp & PSR_N_BIT;
1507 static unsigned long __kprobes __check_al(unsigned long cpsr)
1512 static kprobe_check_cc * const condition_checks[16] = {
1513 &__check_eq, &__check_ne, &__check_cs, &__check_cc,
1514 &__check_mi, &__check_pl, &__check_vs, &__check_vc,
1515 &__check_hi, &__check_ls, &__check_ge, &__check_lt,
1516 &__check_gt, &__check_le, &__check_al, &__check_al
1520 * INSN_REJECTED If instruction is one not allowed to kprobe,
1521 * INSN_GOOD If instruction is supported and uses instruction slot,
1522 * INSN_GOOD_NO_SLOT If instruction is supported but doesn't use its slot.
1524 * For instructions we don't want to kprobe (INSN_REJECTED return result):
1525 * These are generally ones that modify the processor state making
1526 * them "hard" to simulate such as switches processor modes or
1527 * make accesses in alternate modes. Any of these could be simulated
1528 * if the work was put into it, but low return considering they
1529 * should also be very rare.
1531 enum kprobe_insn __kprobes
1532 arm_kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1534 asi->insn_check_cc = condition_checks[insn>>28];
1535 asi->insn[1] = KPROBE_RETURN_INSTRUCTION;
1537 if ((insn & 0xf0000000) == 0xf0000000) {
1539 return space_1111(insn, asi);
1541 } else if ((insn & 0x0e000000) == 0x00000000) {
1543 return space_cccc_000x(insn, asi);
1545 } else if ((insn & 0x0e000000) == 0x02000000) {
1547 return space_cccc_001x(insn, asi);
1549 } else if ((insn & 0x0f000010) == 0x06000010) {
1551 return space_cccc_0110__1(insn, asi);
1553 } else if ((insn & 0x0f000010) == 0x07000010) {
1555 return space_cccc_0111__1(insn, asi);
1557 } else if ((insn & 0x0c000000) == 0x04000000) {
1559 return space_cccc_01xx(insn, asi);
1561 } else if ((insn & 0x0e000000) == 0x08000000) {
1563 return space_cccc_100x(insn, asi);
1565 } else if ((insn & 0x0e000000) == 0x0a000000) {
1567 return space_cccc_101x(insn, asi);
1569 } else if ((insn & 0x0fe00000) == 0x0c400000) {
1571 return space_cccc_1100_010x(insn, asi);
1573 } else if ((insn & 0x0e000000) == 0x0c000000) {
1575 return space_cccc_110x(insn, asi);
1579 return space_cccc_111x(insn, asi);
1582 void __init arm_kprobe_decode_init(void)
1584 find_str_pc_offset();
1589 * All ARM instructions listed below.
1591 * Instructions and their general purpose registers are given.
1592 * If a particular register may not use R15, it is prefixed with a "!".
1593 * If marked with a "*" means the value returned by reading R15
1594 * is implementation defined.
1596 * ADC/ADD/AND/BIC/CMN/CMP/EOR/MOV/MVN/ORR/RSB/RSC/SBC/SUB/TEQ
1597 * TST: Rd, Rn, Rm, !Rs
1600 * BX: Rm (R15 legal, but discouraged)
1604 * LDC/2,STC/2 immediate offset & unindex: Rn
1605 * LDC/2,STC/2 immediate pre/post-indexed: !Rn
1606 * LDM(1/3): !Rn, register_list
1607 * LDM(2): !Rn, !register_list
1608 * LDR,STR,PLD immediate offset: Rd, Rn
1609 * LDR,STR,PLD register offset: Rd, Rn, !Rm
1610 * LDR,STR,PLD scaled register offset: Rd, !Rn, !Rm
1611 * LDR,STR immediate pre/post-indexed: Rd, !Rn
1612 * LDR,STR register pre/post-indexed: Rd, !Rn, !Rm
1613 * LDR,STR scaled register pre/post-indexed: Rd, !Rn, !Rm
1614 * LDRB,STRB immediate offset: !Rd, Rn
1615 * LDRB,STRB register offset: !Rd, Rn, !Rm
1616 * LDRB,STRB scaled register offset: !Rd, !Rn, !Rm
1617 * LDRB,STRB immediate pre/post-indexed: !Rd, !Rn
1618 * LDRB,STRB register pre/post-indexed: !Rd, !Rn, !Rm
1619 * LDRB,STRB scaled register pre/post-indexed: !Rd, !Rn, !Rm
1620 * LDRT,LDRBT,STRBT immediate pre/post-indexed: !Rd, !Rn
1621 * LDRT,LDRBT,STRBT register pre/post-indexed: !Rd, !Rn, !Rm
1622 * LDRT,LDRBT,STRBT scaled register pre/post-indexed: !Rd, !Rn, !Rm
1623 * LDRH/SH/SB/D,STRH/SH/SB/D immediate offset: !Rd, Rn
1624 * LDRH/SH/SB/D,STRH/SH/SB/D register offset: !Rd, Rn, !Rm
1625 * LDRH/SH/SB/D,STRH/SH/SB/D immediate pre/post-indexed: !Rd, !Rn
1626 * LDRH/SH/SB/D,STRH/SH/SB/D register pre/post-indexed: !Rd, !Rn, !Rm
1629 * MCRR/2,MRRC/2: !Rd, !Rn
1630 * MLA: !Rd, !Rn, !Rm, !Rs
1632 * MRC/2: !Rd (if Rd==15, only changes cond codes, not the register)
1634 * MUL: !Rd, !Rm, !Rs
1635 * PKH{BT,TB}: !Rd, !Rn, !Rm
1636 * QDADD,[U]QADD/16/8/SUBX: !Rd, !Rm, !Rn
1637 * QDSUB,[U]QSUB/16/8/ADDX: !Rd, !Rm, !Rn
1638 * REV/16/SH: !Rd, !Rm
1640 * {S,U}[H]ADD{16,8,SUBX},{S,U}[H]SUB{16,8,ADDX}: !Rd, !Rn, !Rm
1641 * SEL: !Rd, !Rn, !Rm
1642 * SMLA<x><y>,SMLA{D,W<y>},SMLSD,SMML{A,S}: !Rd, !Rn, !Rm, !Rs
1643 * SMLAL<x><y>,SMLA{D,LD},SMLSLD,SMMULL,SMULW<y>: !RdHi, !RdLo, !Rm, !Rs
1644 * SMMUL,SMUAD,SMUL<x><y>,SMUSD: !Rd, !Rm, !Rs
1646 * STM(1/2): !Rn, register_list* (R15 in reg list not recommended)
1647 * STRT immediate pre/post-indexed: Rd*, !Rn
1648 * STRT register pre/post-indexed: Rd*, !Rn, !Rm
1649 * STRT scaled register pre/post-indexed: Rd*, !Rn, !Rm
1650 * STREX: !Rd, !Rn, !Rm
1651 * SWP/B: !Rd, !Rn, !Rm
1652 * {S,U}XTA{B,B16,H}: !Rd, !Rn, !Rm
1653 * {S,U}XT{B,B16,H}: !Rd, !Rm
1654 * UM{AA,LA,UL}L: !RdHi, !RdLo, !Rm, !Rs
1655 * USA{D8,A8,T,T16}: !Rd, !Rm, !Rs
1657 * May transfer control by writing R15 (possible mode changes or alternate
1658 * mode accesses marked by "*"):
1659 * ALU op (* with s-bit), B, BL, BKPT, BLX(1/2), BX, BXJ, CPS*, CPY,
1660 * LDM(1), LDM(2/3)*, LDR, MOV, RFE*, SWI*
1662 * Instructions that do not take general registers, nor transfer control:
1663 * CDP/2, SETEND, SRS*