2 * arch/arm/kernel/kprobes-decode.c
4 * Copyright (C) 2006, 2007 Motorola Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
17 * We do not have hardware single-stepping on ARM, This
18 * effort is further complicated by the ARM not having a
19 * "next PC" register. Instructions that change the PC
20 * can't be safely single-stepped in a MP environment, so
21 * we have a lot of work to do:
23 * In the prepare phase:
24 * *) If it is an instruction that does anything
25 * with the CPU mode, we reject it for a kprobe.
26 * (This is out of laziness rather than need. The
27 * instructions could be simulated.)
29 * *) Otherwise, decode the instruction rewriting its
30 * registers to take fixed, ordered registers and
31 * setting a handler for it to run the instruction.
33 * In the execution phase by an instruction's handler:
35 * *) If the PC is written to by the instruction, the
36 * instruction must be fully simulated in software.
37 * If it is a conditional instruction, the handler
38 * will use insn[0] to copy its condition code to
39 * set r0 to 1 and insn[1] to "mov pc, lr" to return.
41 * *) Otherwise, a modified form of the instruction is
42 * directly executed. Its handler calls the
43 * instruction in insn[0]. In insn[1] is a
44 * "mov pc, lr" to return.
46 * Before calling, load up the reordered registers
47 * from the original instruction's registers. If one
48 * of the original input registers is the PC, compute
49 * and adjust the appropriate input register.
51 * After call completes, copy the output registers to
52 * the original instruction's original registers.
54 * We don't use a real breakpoint instruction since that
55 * would have us in the kernel go from SVC mode to SVC
56 * mode losing the link register. Instead we use an
57 * undefined instruction. To simplify processing, the
58 * undefined instruction used for kprobes must be reserved
59 * exclusively for kprobes use.
61 * TODO: ifdef out some instruction decoding based on architecture.
64 #include <linux/kernel.h>
65 #include <linux/kprobes.h>
67 #define sign_extend(x, signbit) ((x) | (0 - ((x) & (1 << (signbit)))))
69 #define branch_displacement(insn) sign_extend(((insn) & 0xffffff) << 2, 25)
71 #define PSR_fs (PSR_f|PSR_s)
73 #define KPROBE_RETURN_INSTRUCTION 0xe1a0f00e /* mov pc, lr */
75 typedef long (insn_0arg_fn_t)(void);
76 typedef long (insn_1arg_fn_t)(long);
77 typedef long (insn_2arg_fn_t)(long, long);
78 typedef long (insn_3arg_fn_t)(long, long, long);
79 typedef long (insn_4arg_fn_t)(long, long, long, long);
80 typedef long long (insn_llret_0arg_fn_t)(void);
81 typedef long long (insn_llret_3arg_fn_t)(long, long, long);
82 typedef long long (insn_llret_4arg_fn_t)(long, long, long, long);
86 #ifdef __LITTLE_ENDIAN
87 struct { long r0, r1; };
89 struct { long r1, r0; };
94 * For STR and STM instructions, an ARM core may choose to use either
95 * a +8 or a +12 displacement from the current instruction's address.
96 * Whichever value is chosen for a given core, it must be the same for
97 * both instructions and may not change. This function measures it.
100 static int str_pc_offset;
102 static void __init find_str_pc_offset(void)
104 int addr, scratch, ret;
107 "sub %[ret], pc, #4 \n\t"
108 "str pc, %[addr] \n\t"
109 "ldr %[scr], %[addr] \n\t"
110 "sub %[ret], %[scr], %[ret] \n\t"
111 : [ret] "=r" (ret), [scr] "=r" (scratch), [addr] "+m" (addr));
117 * The insnslot_?arg_r[w]flags() functions below are to keep the
118 * msr -> *fn -> mrs instruction sequences indivisible so that
119 * the state of the CPSR flags aren't inadvertently modified
120 * just before or just after the call.
123 static inline long __kprobes
124 insnslot_0arg_rflags(long cpsr, insn_0arg_fn_t *fn)
126 register long ret asm("r0");
128 __asm__ __volatile__ (
129 "msr cpsr_fs, %[cpsr] \n\t"
133 : [cpsr] "r" (cpsr), [fn] "r" (fn)
139 static inline long long __kprobes
140 insnslot_llret_0arg_rflags(long cpsr, insn_llret_0arg_fn_t *fn)
142 register long ret0 asm("r0");
143 register long ret1 asm("r1");
146 __asm__ __volatile__ (
147 "msr cpsr_fs, %[cpsr] \n\t"
150 : "=r" (ret0), "=r" (ret1)
151 : [cpsr] "r" (cpsr), [fn] "r" (fn)
159 static inline long __kprobes
160 insnslot_1arg_rflags(long r0, long cpsr, insn_1arg_fn_t *fn)
162 register long rr0 asm("r0") = r0;
163 register long ret asm("r0");
165 __asm__ __volatile__ (
166 "msr cpsr_fs, %[cpsr] \n\t"
170 : "0" (rr0), [cpsr] "r" (cpsr), [fn] "r" (fn)
176 static inline long __kprobes
177 insnslot_2arg_rflags(long r0, long r1, long cpsr, insn_2arg_fn_t *fn)
179 register long rr0 asm("r0") = r0;
180 register long rr1 asm("r1") = r1;
181 register long ret asm("r0");
183 __asm__ __volatile__ (
184 "msr cpsr_fs, %[cpsr] \n\t"
188 : "0" (rr0), "r" (rr1),
189 [cpsr] "r" (cpsr), [fn] "r" (fn)
195 static inline long __kprobes
196 insnslot_3arg_rflags(long r0, long r1, long r2, long cpsr, insn_3arg_fn_t *fn)
198 register long rr0 asm("r0") = r0;
199 register long rr1 asm("r1") = r1;
200 register long rr2 asm("r2") = r2;
201 register long ret asm("r0");
203 __asm__ __volatile__ (
204 "msr cpsr_fs, %[cpsr] \n\t"
208 : "0" (rr0), "r" (rr1), "r" (rr2),
209 [cpsr] "r" (cpsr), [fn] "r" (fn)
215 static inline long long __kprobes
216 insnslot_llret_3arg_rflags(long r0, long r1, long r2, long cpsr,
217 insn_llret_3arg_fn_t *fn)
219 register long rr0 asm("r0") = r0;
220 register long rr1 asm("r1") = r1;
221 register long rr2 asm("r2") = r2;
222 register long ret0 asm("r0");
223 register long ret1 asm("r1");
226 __asm__ __volatile__ (
227 "msr cpsr_fs, %[cpsr] \n\t"
230 : "=r" (ret0), "=r" (ret1)
231 : "0" (rr0), "r" (rr1), "r" (rr2),
232 [cpsr] "r" (cpsr), [fn] "r" (fn)
240 static inline long __kprobes
241 insnslot_4arg_rflags(long r0, long r1, long r2, long r3, long cpsr,
244 register long rr0 asm("r0") = r0;
245 register long rr1 asm("r1") = r1;
246 register long rr2 asm("r2") = r2;
247 register long rr3 asm("r3") = r3;
248 register long ret asm("r0");
250 __asm__ __volatile__ (
251 "msr cpsr_fs, %[cpsr] \n\t"
255 : "0" (rr0), "r" (rr1), "r" (rr2), "r" (rr3),
256 [cpsr] "r" (cpsr), [fn] "r" (fn)
262 static inline long __kprobes
263 insnslot_1arg_rwflags(long r0, long *cpsr, insn_1arg_fn_t *fn)
265 register long rr0 asm("r0") = r0;
266 register long ret asm("r0");
267 long oldcpsr = *cpsr;
270 __asm__ __volatile__ (
271 "msr cpsr_fs, %[oldcpsr] \n\t"
274 "mrs %[newcpsr], cpsr \n\t"
275 : "=r" (ret), [newcpsr] "=r" (newcpsr)
276 : "0" (rr0), [oldcpsr] "r" (oldcpsr), [fn] "r" (fn)
279 *cpsr = (oldcpsr & ~PSR_fs) | (newcpsr & PSR_fs);
283 static inline long __kprobes
284 insnslot_2arg_rwflags(long r0, long r1, long *cpsr, insn_2arg_fn_t *fn)
286 register long rr0 asm("r0") = r0;
287 register long rr1 asm("r1") = r1;
288 register long ret asm("r0");
289 long oldcpsr = *cpsr;
292 __asm__ __volatile__ (
293 "msr cpsr_fs, %[oldcpsr] \n\t"
296 "mrs %[newcpsr], cpsr \n\t"
297 : "=r" (ret), [newcpsr] "=r" (newcpsr)
298 : "0" (rr0), "r" (rr1), [oldcpsr] "r" (oldcpsr), [fn] "r" (fn)
301 *cpsr = (oldcpsr & ~PSR_fs) | (newcpsr & PSR_fs);
305 static inline long __kprobes
306 insnslot_3arg_rwflags(long r0, long r1, long r2, long *cpsr,
309 register long rr0 asm("r0") = r0;
310 register long rr1 asm("r1") = r1;
311 register long rr2 asm("r2") = r2;
312 register long ret asm("r0");
313 long oldcpsr = *cpsr;
316 __asm__ __volatile__ (
317 "msr cpsr_fs, %[oldcpsr] \n\t"
320 "mrs %[newcpsr], cpsr \n\t"
321 : "=r" (ret), [newcpsr] "=r" (newcpsr)
322 : "0" (rr0), "r" (rr1), "r" (rr2),
323 [oldcpsr] "r" (oldcpsr), [fn] "r" (fn)
326 *cpsr = (oldcpsr & ~PSR_fs) | (newcpsr & PSR_fs);
330 static inline long __kprobes
331 insnslot_4arg_rwflags(long r0, long r1, long r2, long r3, long *cpsr,
334 register long rr0 asm("r0") = r0;
335 register long rr1 asm("r1") = r1;
336 register long rr2 asm("r2") = r2;
337 register long rr3 asm("r3") = r3;
338 register long ret asm("r0");
339 long oldcpsr = *cpsr;
342 __asm__ __volatile__ (
343 "msr cpsr_fs, %[oldcpsr] \n\t"
346 "mrs %[newcpsr], cpsr \n\t"
347 : "=r" (ret), [newcpsr] "=r" (newcpsr)
348 : "0" (rr0), "r" (rr1), "r" (rr2), "r" (rr3),
349 [oldcpsr] "r" (oldcpsr), [fn] "r" (fn)
352 *cpsr = (oldcpsr & ~PSR_fs) | (newcpsr & PSR_fs);
356 static inline long long __kprobes
357 insnslot_llret_4arg_rwflags(long r0, long r1, long r2, long r3, long *cpsr,
358 insn_llret_4arg_fn_t *fn)
360 register long rr0 asm("r0") = r0;
361 register long rr1 asm("r1") = r1;
362 register long rr2 asm("r2") = r2;
363 register long rr3 asm("r3") = r3;
364 register long ret0 asm("r0");
365 register long ret1 asm("r1");
366 long oldcpsr = *cpsr;
370 __asm__ __volatile__ (
371 "msr cpsr_fs, %[oldcpsr] \n\t"
374 "mrs %[newcpsr], cpsr \n\t"
375 : "=r" (ret0), "=r" (ret1), [newcpsr] "=r" (newcpsr)
376 : "0" (rr0), "r" (rr1), "r" (rr2), "r" (rr3),
377 [oldcpsr] "r" (oldcpsr), [fn] "r" (fn)
380 *cpsr = (oldcpsr & ~PSR_fs) | (newcpsr & PSR_fs);
387 * To avoid the complications of mimicing single-stepping on a
388 * processor without a Next-PC or a single-step mode, and to
389 * avoid having to deal with the side-effects of boosting, we
390 * simulate or emulate (almost) all ARM instructions.
392 * "Simulation" is where the instruction's behavior is duplicated in
393 * C code. "Emulation" is where the original instruction is rewritten
394 * and executed, often by altering its registers.
396 * By having all behavior of the kprobe'd instruction completed before
397 * returning from the kprobe_handler(), all locks (scheduler and
398 * interrupt) can safely be released. There is no need for secondary
399 * breakpoints, no race with MP or preemptable kernels, nor having to
400 * clean up resources counts at a later time impacting overall system
401 * performance. By rewriting the instruction, only the minimum registers
402 * need to be loaded and saved back optimizing performance.
404 * Calling the insnslot_*_rwflags version of a function doesn't hurt
405 * anything even when the CPSR flags aren't updated by the
406 * instruction. It's just a little slower in return for saving
407 * a little space by not having a duplicate function that doesn't
408 * update the flags. (The same optimization can be said for
409 * instructions that do or don't perform register writeback)
410 * Also, instructions can either read the flags, only write the
411 * flags, or read and write the flags. To save combinations
412 * rather than for sheer performance, flag functions just assume
413 * read and write of flags.
416 static void __kprobes simulate_bbl(struct kprobe *p, struct pt_regs *regs)
418 kprobe_opcode_t insn = p->opcode;
419 long iaddr = (long)p->addr;
420 int disp = branch_displacement(insn);
422 if (insn & (1 << 24))
423 regs->ARM_lr = iaddr + 4;
425 regs->ARM_pc = iaddr + 8 + disp;
428 static void __kprobes simulate_blx1(struct kprobe *p, struct pt_regs *regs)
430 kprobe_opcode_t insn = p->opcode;
431 long iaddr = (long)p->addr;
432 int disp = branch_displacement(insn);
434 regs->ARM_lr = iaddr + 4;
435 regs->ARM_pc = iaddr + 8 + disp + ((insn >> 23) & 0x2);
436 regs->ARM_cpsr |= PSR_T_BIT;
439 static void __kprobes simulate_blx2bx(struct kprobe *p, struct pt_regs *regs)
441 kprobe_opcode_t insn = p->opcode;
443 long rmv = regs->uregs[rm];
446 regs->ARM_lr = (long)p->addr + 4;
448 regs->ARM_pc = rmv & ~0x1;
449 regs->ARM_cpsr &= ~PSR_T_BIT;
451 regs->ARM_cpsr |= PSR_T_BIT;
454 static void __kprobes simulate_ldm1stm1(struct kprobe *p, struct pt_regs *regs)
456 kprobe_opcode_t insn = p->opcode;
457 int rn = (insn >> 16) & 0xf;
458 int lbit = insn & (1 << 20);
459 int wbit = insn & (1 << 21);
460 int ubit = insn & (1 << 23);
461 int pbit = insn & (1 << 24);
462 long *addr = (long *)regs->uregs[rn];
467 reg_bit_vector = insn & 0xffff;
468 while (reg_bit_vector) {
469 reg_bit_vector &= (reg_bit_vector - 1);
475 addr += (!pbit == !ubit);
477 reg_bit_vector = insn & 0xffff;
478 while (reg_bit_vector) {
479 int reg = __ffs(reg_bit_vector);
480 reg_bit_vector &= (reg_bit_vector - 1);
482 regs->uregs[reg] = *addr++;
484 *addr++ = regs->uregs[reg];
490 addr -= (!pbit == !ubit);
491 regs->uregs[rn] = (long)addr;
495 static void __kprobes simulate_stm1_pc(struct kprobe *p, struct pt_regs *regs)
497 regs->ARM_pc = (long)p->addr + str_pc_offset;
498 simulate_ldm1stm1(p, regs);
499 regs->ARM_pc = (long)p->addr + 4;
502 static void __kprobes simulate_mov_ipsp(struct kprobe *p, struct pt_regs *regs)
504 regs->uregs[12] = regs->uregs[13];
507 static void __kprobes emulate_ldcstc(struct kprobe *p, struct pt_regs *regs)
509 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
510 kprobe_opcode_t insn = p->opcode;
511 int rn = (insn >> 16) & 0xf;
512 long rnv = regs->uregs[rn];
514 /* Save Rn in case of writeback. */
515 regs->uregs[rn] = insnslot_1arg_rflags(rnv, regs->ARM_cpsr, i_fn);
518 static void __kprobes emulate_ldrd(struct kprobe *p, struct pt_regs *regs)
520 insn_2arg_fn_t *i_fn = (insn_2arg_fn_t *)&p->ainsn.insn[0];
521 kprobe_opcode_t insn = p->opcode;
522 long ppc = (long)p->addr + 8;
523 int rd = (insn >> 12) & 0xf;
524 int rn = (insn >> 16) & 0xf;
525 int rm = insn & 0xf; /* rm may be invalid, don't care. */
526 long rmv = (rm == 15) ? ppc : regs->uregs[rm];
527 long rnv = (rn == 15) ? ppc : regs->uregs[rn];
529 /* Not following the C calling convention here, so need asm(). */
530 __asm__ __volatile__ (
533 "msr cpsr_fs, %[cpsr]\n\t"
535 "mov pc, %[i_fn] \n\t"
536 "str r0, %[rn] \n\t" /* in case of writeback */
537 "str r2, %[rd0] \n\t"
538 "str r3, %[rd1] \n\t"
540 [rd0] "=m" (regs->uregs[rd]),
541 [rd1] "=m" (regs->uregs[rd+1])
543 [cpsr] "r" (regs->ARM_cpsr),
545 : "r0", "r1", "r2", "r3", "lr", "cc"
548 regs->uregs[rn] = rnv; /* Save Rn in case of writeback. */
551 static void __kprobes emulate_strd(struct kprobe *p, struct pt_regs *regs)
553 insn_4arg_fn_t *i_fn = (insn_4arg_fn_t *)&p->ainsn.insn[0];
554 kprobe_opcode_t insn = p->opcode;
555 long ppc = (long)p->addr + 8;
556 int rd = (insn >> 12) & 0xf;
557 int rn = (insn >> 16) & 0xf;
559 long rnv = (rn == 15) ? ppc : regs->uregs[rn];
560 /* rm/rmv may be invalid, don't care. */
561 long rmv = (rm == 15) ? ppc : regs->uregs[rm];
564 rnv_wb = insnslot_4arg_rflags(rnv, rmv, regs->uregs[rd],
566 regs->ARM_cpsr, i_fn);
568 regs->uregs[rn] = rnv_wb; /* Save Rn in case of writeback. */
571 static void __kprobes emulate_ldr(struct kprobe *p, struct pt_regs *regs)
573 insn_llret_3arg_fn_t *i_fn = (insn_llret_3arg_fn_t *)&p->ainsn.insn[0];
574 kprobe_opcode_t insn = p->opcode;
575 long ppc = (long)p->addr + 8;
577 int rd = (insn >> 12) & 0xf;
578 int rn = (insn >> 16) & 0xf;
581 long rnv = (rn == 15) ? ppc : regs->uregs[rn];
582 long rmv = (rm == 15) ? ppc : regs->uregs[rm];
583 long cpsr = regs->ARM_cpsr;
585 fnr.dr = insnslot_llret_3arg_rflags(rnv, 0, rmv, cpsr, i_fn);
587 regs->uregs[rn] = fnr.r0; /* Save Rn in case of writeback. */
591 #if __LINUX_ARM_ARCH__ >= 5
595 regs->ARM_cpsr = cpsr;
601 regs->uregs[rd] = rdv;
604 static void __kprobes emulate_str(struct kprobe *p, struct pt_regs *regs)
606 insn_3arg_fn_t *i_fn = (insn_3arg_fn_t *)&p->ainsn.insn[0];
607 kprobe_opcode_t insn = p->opcode;
608 long iaddr = (long)p->addr;
609 int rd = (insn >> 12) & 0xf;
610 int rn = (insn >> 16) & 0xf;
612 long rdv = (rd == 15) ? iaddr + str_pc_offset : regs->uregs[rd];
613 long rnv = (rn == 15) ? iaddr + 8 : regs->uregs[rn];
614 long rmv = regs->uregs[rm]; /* rm/rmv may be invalid, don't care. */
617 rnv_wb = insnslot_3arg_rflags(rnv, rdv, rmv, regs->ARM_cpsr, i_fn);
619 regs->uregs[rn] = rnv_wb; /* Save Rn in case of writeback. */
622 static void __kprobes emulate_mrrc(struct kprobe *p, struct pt_regs *regs)
624 insn_llret_0arg_fn_t *i_fn = (insn_llret_0arg_fn_t *)&p->ainsn.insn[0];
625 kprobe_opcode_t insn = p->opcode;
627 int rd = (insn >> 12) & 0xf;
628 int rn = (insn >> 16) & 0xf;
630 fnr.dr = insnslot_llret_0arg_rflags(regs->ARM_cpsr, i_fn);
631 regs->uregs[rn] = fnr.r0;
632 regs->uregs[rd] = fnr.r1;
635 static void __kprobes emulate_mcrr(struct kprobe *p, struct pt_regs *regs)
637 insn_2arg_fn_t *i_fn = (insn_2arg_fn_t *)&p->ainsn.insn[0];
638 kprobe_opcode_t insn = p->opcode;
639 int rd = (insn >> 12) & 0xf;
640 int rn = (insn >> 16) & 0xf;
641 long rnv = regs->uregs[rn];
642 long rdv = regs->uregs[rd];
644 insnslot_2arg_rflags(rnv, rdv, regs->ARM_cpsr, i_fn);
647 static void __kprobes emulate_sat(struct kprobe *p, struct pt_regs *regs)
649 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
650 kprobe_opcode_t insn = p->opcode;
651 int rd = (insn >> 12) & 0xf;
653 long rmv = regs->uregs[rm];
656 regs->uregs[rd] = insnslot_1arg_rwflags(rmv, ®s->ARM_cpsr, i_fn);
659 static void __kprobes emulate_sel(struct kprobe *p, struct pt_regs *regs)
661 insn_2arg_fn_t *i_fn = (insn_2arg_fn_t *)&p->ainsn.insn[0];
662 kprobe_opcode_t insn = p->opcode;
663 int rd = (insn >> 12) & 0xf;
664 int rn = (insn >> 16) & 0xf;
666 long rnv = regs->uregs[rn];
667 long rmv = regs->uregs[rm];
670 regs->uregs[rd] = insnslot_2arg_rflags(rnv, rmv, regs->ARM_cpsr, i_fn);
673 static void __kprobes emulate_none(struct kprobe *p, struct pt_regs *regs)
675 insn_0arg_fn_t *i_fn = (insn_0arg_fn_t *)&p->ainsn.insn[0];
677 insnslot_0arg_rflags(regs->ARM_cpsr, i_fn);
680 static void __kprobes emulate_rd12(struct kprobe *p, struct pt_regs *regs)
682 insn_0arg_fn_t *i_fn = (insn_0arg_fn_t *)&p->ainsn.insn[0];
683 kprobe_opcode_t insn = p->opcode;
684 int rd = (insn >> 12) & 0xf;
686 regs->uregs[rd] = insnslot_0arg_rflags(regs->ARM_cpsr, i_fn);
689 static void __kprobes emulate_ird12(struct kprobe *p, struct pt_regs *regs)
691 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
692 kprobe_opcode_t insn = p->opcode;
693 int ird = (insn >> 12) & 0xf;
695 insnslot_1arg_rflags(regs->uregs[ird], regs->ARM_cpsr, i_fn);
698 static void __kprobes emulate_rn16(struct kprobe *p, struct pt_regs *regs)
700 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
701 kprobe_opcode_t insn = p->opcode;
702 int rn = (insn >> 16) & 0xf;
703 long rnv = regs->uregs[rn];
705 insnslot_1arg_rflags(rnv, regs->ARM_cpsr, i_fn);
708 static void __kprobes emulate_rd12rm0(struct kprobe *p, struct pt_regs *regs)
710 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
711 kprobe_opcode_t insn = p->opcode;
712 int rd = (insn >> 12) & 0xf;
714 long rmv = regs->uregs[rm];
716 regs->uregs[rd] = insnslot_1arg_rflags(rmv, regs->ARM_cpsr, i_fn);
719 static void __kprobes
720 emulate_rd12rn16rm0_rwflags(struct kprobe *p, struct pt_regs *regs)
722 insn_2arg_fn_t *i_fn = (insn_2arg_fn_t *)&p->ainsn.insn[0];
723 kprobe_opcode_t insn = p->opcode;
724 int rd = (insn >> 12) & 0xf;
725 int rn = (insn >> 16) & 0xf;
727 long rnv = regs->uregs[rn];
728 long rmv = regs->uregs[rm];
731 insnslot_2arg_rwflags(rnv, rmv, ®s->ARM_cpsr, i_fn);
734 static void __kprobes
735 emulate_rd16rn12rs8rm0_rwflags(struct kprobe *p, struct pt_regs *regs)
737 insn_3arg_fn_t *i_fn = (insn_3arg_fn_t *)&p->ainsn.insn[0];
738 kprobe_opcode_t insn = p->opcode;
739 int rd = (insn >> 16) & 0xf;
740 int rn = (insn >> 12) & 0xf;
741 int rs = (insn >> 8) & 0xf;
743 long rnv = regs->uregs[rn];
744 long rsv = regs->uregs[rs];
745 long rmv = regs->uregs[rm];
748 insnslot_3arg_rwflags(rnv, rsv, rmv, ®s->ARM_cpsr, i_fn);
751 static void __kprobes
752 emulate_rd16rs8rm0_rwflags(struct kprobe *p, struct pt_regs *regs)
754 insn_2arg_fn_t *i_fn = (insn_2arg_fn_t *)&p->ainsn.insn[0];
755 kprobe_opcode_t insn = p->opcode;
756 int rd = (insn >> 16) & 0xf;
757 int rs = (insn >> 8) & 0xf;
759 long rsv = regs->uregs[rs];
760 long rmv = regs->uregs[rm];
763 insnslot_2arg_rwflags(rsv, rmv, ®s->ARM_cpsr, i_fn);
766 static void __kprobes
767 emulate_rdhi16rdlo12rs8rm0_rwflags(struct kprobe *p, struct pt_regs *regs)
769 insn_llret_4arg_fn_t *i_fn = (insn_llret_4arg_fn_t *)&p->ainsn.insn[0];
770 kprobe_opcode_t insn = p->opcode;
772 int rdhi = (insn >> 16) & 0xf;
773 int rdlo = (insn >> 12) & 0xf;
774 int rs = (insn >> 8) & 0xf;
776 long rsv = regs->uregs[rs];
777 long rmv = regs->uregs[rm];
779 fnr.dr = insnslot_llret_4arg_rwflags(regs->uregs[rdhi],
780 regs->uregs[rdlo], rsv, rmv,
781 ®s->ARM_cpsr, i_fn);
782 regs->uregs[rdhi] = fnr.r0;
783 regs->uregs[rdlo] = fnr.r1;
786 static void __kprobes
787 emulate_alu_imm_rflags(struct kprobe *p, struct pt_regs *regs)
789 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
790 kprobe_opcode_t insn = p->opcode;
791 int rd = (insn >> 12) & 0xf;
792 int rn = (insn >> 16) & 0xf;
793 long rnv = (rn == 15) ? (long)p->addr + 8 : regs->uregs[rn];
795 regs->uregs[rd] = insnslot_1arg_rflags(rnv, regs->ARM_cpsr, i_fn);
798 static void __kprobes
799 emulate_alu_imm_rwflags(struct kprobe *p, struct pt_regs *regs)
801 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
802 kprobe_opcode_t insn = p->opcode;
803 int rd = (insn >> 12) & 0xf;
804 int rn = (insn >> 16) & 0xf;
805 long rnv = (rn == 15) ? (long)p->addr + 8 : regs->uregs[rn];
807 regs->uregs[rd] = insnslot_1arg_rwflags(rnv, ®s->ARM_cpsr, i_fn);
810 static void __kprobes
811 emulate_alu_tests_imm(struct kprobe *p, struct pt_regs *regs)
813 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
814 kprobe_opcode_t insn = p->opcode;
815 int rn = (insn >> 16) & 0xf;
816 long rnv = (rn == 15) ? (long)p->addr + 8 : regs->uregs[rn];
818 insnslot_1arg_rwflags(rnv, ®s->ARM_cpsr, i_fn);
821 static void __kprobes
822 emulate_alu_rflags(struct kprobe *p, struct pt_regs *regs)
824 insn_3arg_fn_t *i_fn = (insn_3arg_fn_t *)&p->ainsn.insn[0];
825 kprobe_opcode_t insn = p->opcode;
826 long ppc = (long)p->addr + 8;
827 int rd = (insn >> 12) & 0xf;
828 int rn = (insn >> 16) & 0xf; /* rn/rnv/rs/rsv may be */
829 int rs = (insn >> 8) & 0xf; /* invalid, don't care. */
831 long rnv = (rn == 15) ? ppc : regs->uregs[rn];
832 long rmv = (rm == 15) ? ppc : regs->uregs[rm];
833 long rsv = regs->uregs[rs];
836 insnslot_3arg_rflags(rnv, rmv, rsv, regs->ARM_cpsr, i_fn);
839 static void __kprobes
840 emulate_alu_rwflags(struct kprobe *p, struct pt_regs *regs)
842 insn_3arg_fn_t *i_fn = (insn_3arg_fn_t *)&p->ainsn.insn[0];
843 kprobe_opcode_t insn = p->opcode;
844 long ppc = (long)p->addr + 8;
845 int rd = (insn >> 12) & 0xf;
846 int rn = (insn >> 16) & 0xf; /* rn/rnv/rs/rsv may be */
847 int rs = (insn >> 8) & 0xf; /* invalid, don't care. */
849 long rnv = (rn == 15) ? ppc : regs->uregs[rn];
850 long rmv = (rm == 15) ? ppc : regs->uregs[rm];
851 long rsv = regs->uregs[rs];
854 insnslot_3arg_rwflags(rnv, rmv, rsv, ®s->ARM_cpsr, i_fn);
857 static void __kprobes
858 emulate_alu_tests(struct kprobe *p, struct pt_regs *regs)
860 insn_3arg_fn_t *i_fn = (insn_3arg_fn_t *)&p->ainsn.insn[0];
861 kprobe_opcode_t insn = p->opcode;
862 long ppc = (long)p->addr + 8;
863 int rn = (insn >> 16) & 0xf;
864 int rs = (insn >> 8) & 0xf; /* rs/rsv may be invalid, don't care. */
866 long rnv = (rn == 15) ? ppc : regs->uregs[rn];
867 long rmv = (rm == 15) ? ppc : regs->uregs[rm];
868 long rsv = regs->uregs[rs];
870 insnslot_3arg_rwflags(rnv, rmv, rsv, ®s->ARM_cpsr, i_fn);
873 static enum kprobe_insn __kprobes
874 prep_emulate_ldr_str(kprobe_opcode_t insn, struct arch_specific_insn *asi)
876 int ibit = (insn & (1 << 26)) ? 25 : 22;
879 insn |= 0x00001000; /* Rn = r0, Rd = r1 */
880 if (insn & (1 << ibit)) {
882 insn |= 2; /* Rm = r2 */
885 asi->insn_handler = (insn & (1 << 20)) ? emulate_ldr : emulate_str;
889 static enum kprobe_insn __kprobes
890 prep_emulate_rd12rm0(kprobe_opcode_t insn, struct arch_specific_insn *asi)
892 insn &= 0xffff0ff0; /* Rd = r0, Rm = r0 */
894 asi->insn_handler = emulate_rd12rm0;
898 static enum kprobe_insn __kprobes
899 prep_emulate_rd12(kprobe_opcode_t insn, struct arch_specific_insn *asi)
901 insn &= 0xffff0fff; /* Rd = r0 */
903 asi->insn_handler = emulate_rd12;
907 static enum kprobe_insn __kprobes
908 prep_emulate_rd12rn16rm0_wflags(kprobe_opcode_t insn,
909 struct arch_specific_insn *asi)
911 insn &= 0xfff00ff0; /* Rd = r0, Rn = r0 */
912 insn |= 0x00000001; /* Rm = r1 */
914 asi->insn_handler = emulate_rd12rn16rm0_rwflags;
918 static enum kprobe_insn __kprobes
919 prep_emulate_rd16rs8rm0_wflags(kprobe_opcode_t insn,
920 struct arch_specific_insn *asi)
922 insn &= 0xfff0f0f0; /* Rd = r0, Rs = r0 */
923 insn |= 0x00000001; /* Rm = r1 */
925 asi->insn_handler = emulate_rd16rs8rm0_rwflags;
929 static enum kprobe_insn __kprobes
930 prep_emulate_rd16rn12rs8rm0_wflags(kprobe_opcode_t insn,
931 struct arch_specific_insn *asi)
933 insn &= 0xfff000f0; /* Rd = r0, Rn = r0 */
934 insn |= 0x00000102; /* Rs = r1, Rm = r2 */
936 asi->insn_handler = emulate_rd16rn12rs8rm0_rwflags;
940 static enum kprobe_insn __kprobes
941 prep_emulate_rdhi16rdlo12rs8rm0_wflags(kprobe_opcode_t insn,
942 struct arch_specific_insn *asi)
944 insn &= 0xfff000f0; /* RdHi = r0, RdLo = r1 */
945 insn |= 0x00001203; /* Rs = r2, Rm = r3 */
947 asi->insn_handler = emulate_rdhi16rdlo12rs8rm0_rwflags;
952 * For the instruction masking and comparisons in all the "space_*"
953 * functions below, Do _not_ rearrange the order of tests unless
954 * you're very, very sure of what you are doing. For the sake of
955 * efficiency, the masks for some tests sometimes assume other test
956 * have been done prior to them so the number of patterns to test
957 * for an instruction set can be as broad as possible to reduce the
958 * number of tests needed.
961 static enum kprobe_insn __kprobes
962 space_1111(kprobe_opcode_t insn, struct arch_specific_insn *asi)
964 /* CPS mmod == 1 : 1111 0001 0000 xx10 xxxx xxxx xx0x xxxx */
965 /* RFE : 1111 100x x0x1 xxxx xxxx 1010 xxxx xxxx */
966 /* SRS : 1111 100x x1x0 1101 xxxx 0101 xxxx xxxx */
967 if ((insn & 0xfff30020) == 0xf1020000 ||
968 (insn & 0xfe500f00) == 0xf8100a00 ||
969 (insn & 0xfe5f0f00) == 0xf84d0500)
970 return INSN_REJECTED;
972 /* PLD : 1111 01x1 x101 xxxx xxxx xxxx xxxx xxxx : */
973 if ((insn & 0xfd700000) == 0xf4500000) {
974 insn &= 0xfff0ffff; /* Rn = r0 */
976 asi->insn_handler = emulate_rn16;
980 /* BLX(1) : 1111 101x xxxx xxxx xxxx xxxx xxxx xxxx : */
981 if ((insn & 0xfe000000) == 0xfa000000) {
982 asi->insn_handler = simulate_blx1;
983 return INSN_GOOD_NO_SLOT;
986 /* SETEND : 1111 0001 0000 0001 xxxx xxxx 0000 xxxx */
987 /* CDP2 : 1111 1110 xxxx xxxx xxxx xxxx xxx0 xxxx */
988 if ((insn & 0xffff00f0) == 0xf1010000 ||
989 (insn & 0xff000010) == 0xfe000000) {
991 asi->insn_handler = emulate_none;
995 /* MCRR2 : 1111 1100 0100 xxxx xxxx xxxx xxxx xxxx : (Rd != Rn) */
996 /* MRRC2 : 1111 1100 0101 xxxx xxxx xxxx xxxx xxxx : (Rd != Rn) */
997 if ((insn & 0xffe00000) == 0xfc400000) {
998 insn &= 0xfff00fff; /* Rn = r0 */
999 insn |= 0x00001000; /* Rd = r1 */
1000 asi->insn[0] = insn;
1002 (insn & (1 << 20)) ? emulate_mrrc : emulate_mcrr;
1006 /* LDC2 : 1111 110x xxx1 xxxx xxxx xxxx xxxx xxxx */
1007 /* STC2 : 1111 110x xxx0 xxxx xxxx xxxx xxxx xxxx */
1008 if ((insn & 0xfe000000) == 0xfc000000) {
1009 insn &= 0xfff0ffff; /* Rn = r0 */
1010 asi->insn[0] = insn;
1011 asi->insn_handler = emulate_ldcstc;
1015 /* MCR2 : 1111 1110 xxx0 xxxx xxxx xxxx xxx1 xxxx */
1016 /* MRC2 : 1111 1110 xxx1 xxxx xxxx xxxx xxx1 xxxx */
1017 insn &= 0xffff0fff; /* Rd = r0 */
1018 asi->insn[0] = insn;
1019 asi->insn_handler = (insn & (1 << 20)) ? emulate_rd12 : emulate_ird12;
1023 static enum kprobe_insn __kprobes
1024 space_cccc_000x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1026 /* cccc 0001 0xx0 xxxx xxxx xxxx xxxx xxx0 xxxx */
1027 if ((insn & 0x0f900010) == 0x01000000) {
1029 /* BXJ : cccc 0001 0010 xxxx xxxx xxxx 0010 xxxx */
1030 /* MSR : cccc 0001 0x10 xxxx xxxx xxxx 0000 xxxx */
1031 if ((insn & 0x0ff000f0) == 0x01200020 ||
1032 (insn & 0x0fb000f0) == 0x01200000)
1033 return INSN_REJECTED;
1035 /* MRS : cccc 0001 0x00 xxxx xxxx xxxx 0000 xxxx */
1036 if ((insn & 0x0fb00010) == 0x01000000)
1037 return prep_emulate_rd12(insn, asi);
1039 /* SMLALxy : cccc 0001 0100 xxxx xxxx xxxx 1xx0 xxxx */
1040 if ((insn & 0x0ff00090) == 0x01400080)
1041 return prep_emulate_rdhi16rdlo12rs8rm0_wflags(insn, asi);
1043 /* SMULWy : cccc 0001 0010 xxxx xxxx xxxx 1x10 xxxx */
1044 /* SMULxy : cccc 0001 0110 xxxx xxxx xxxx 1xx0 xxxx */
1045 if ((insn & 0x0ff000b0) == 0x012000a0 ||
1046 (insn & 0x0ff00090) == 0x01600080)
1047 return prep_emulate_rd16rs8rm0_wflags(insn, asi);
1049 /* SMLAxy : cccc 0001 0000 xxxx xxxx xxxx 1xx0 xxxx : Q */
1050 /* SMLAWy : cccc 0001 0010 xxxx xxxx xxxx 0x00 xxxx : Q */
1051 return prep_emulate_rd16rn12rs8rm0_wflags(insn, asi);
1055 /* cccc 0001 0xx0 xxxx xxxx xxxx xxxx 0xx1 xxxx */
1056 else if ((insn & 0x0f900090) == 0x01000010) {
1058 /* BKPT : 1110 0001 0010 xxxx xxxx xxxx 0111 xxxx */
1059 if ((insn & 0xfff000f0) == 0xe1200070)
1060 return INSN_REJECTED;
1062 /* BLX(2) : cccc 0001 0010 xxxx xxxx xxxx 0011 xxxx */
1063 /* BX : cccc 0001 0010 xxxx xxxx xxxx 0001 xxxx */
1064 if ((insn & 0x0ff000d0) == 0x01200010) {
1065 asi->insn_handler = simulate_blx2bx;
1066 return INSN_GOOD_NO_SLOT;
1069 /* CLZ : cccc 0001 0110 xxxx xxxx xxxx 0001 xxxx */
1070 if ((insn & 0x0ff000f0) == 0x01600010)
1071 return prep_emulate_rd12rm0(insn, asi);
1073 /* QADD : cccc 0001 0000 xxxx xxxx xxxx 0101 xxxx :Q */
1074 /* QSUB : cccc 0001 0010 xxxx xxxx xxxx 0101 xxxx :Q */
1075 /* QDADD : cccc 0001 0100 xxxx xxxx xxxx 0101 xxxx :Q */
1076 /* QDSUB : cccc 0001 0110 xxxx xxxx xxxx 0101 xxxx :Q */
1077 return prep_emulate_rd12rn16rm0_wflags(insn, asi);
1080 /* cccc 0000 xxxx xxxx xxxx xxxx xxxx 1001 xxxx */
1081 else if ((insn & 0x0f000090) == 0x00000090) {
1083 /* MUL : cccc 0000 0000 xxxx xxxx xxxx 1001 xxxx : */
1084 /* MULS : cccc 0000 0001 xxxx xxxx xxxx 1001 xxxx :cc */
1085 /* MLA : cccc 0000 0010 xxxx xxxx xxxx 1001 xxxx : */
1086 /* MLAS : cccc 0000 0011 xxxx xxxx xxxx 1001 xxxx :cc */
1087 /* UMAAL : cccc 0000 0100 xxxx xxxx xxxx 1001 xxxx : */
1088 /* UMULL : cccc 0000 1000 xxxx xxxx xxxx 1001 xxxx : */
1089 /* UMULLS : cccc 0000 1001 xxxx xxxx xxxx 1001 xxxx :cc */
1090 /* UMLAL : cccc 0000 1010 xxxx xxxx xxxx 1001 xxxx : */
1091 /* UMLALS : cccc 0000 1011 xxxx xxxx xxxx 1001 xxxx :cc */
1092 /* SMULL : cccc 0000 1100 xxxx xxxx xxxx 1001 xxxx : */
1093 /* SMULLS : cccc 0000 1101 xxxx xxxx xxxx 1001 xxxx :cc */
1094 /* SMLAL : cccc 0000 1110 xxxx xxxx xxxx 1001 xxxx : */
1095 /* SMLALS : cccc 0000 1111 xxxx xxxx xxxx 1001 xxxx :cc */
1096 if ((insn & 0x0fe000f0) == 0x00000090) {
1097 return prep_emulate_rd16rs8rm0_wflags(insn, asi);
1098 } else if ((insn & 0x0fe000f0) == 0x00200090) {
1099 return prep_emulate_rd16rn12rs8rm0_wflags(insn, asi);
1101 return prep_emulate_rdhi16rdlo12rs8rm0_wflags(insn, asi);
1105 /* cccc 000x xxxx xxxx xxxx xxxx xxxx 1xx1 xxxx */
1106 else if ((insn & 0x0e000090) == 0x00000090) {
1108 /* SWP : cccc 0001 0000 xxxx xxxx xxxx 1001 xxxx */
1109 /* SWPB : cccc 0001 0100 xxxx xxxx xxxx 1001 xxxx */
1110 /* LDRD : cccc 000x xxx0 xxxx xxxx xxxx 1101 xxxx */
1111 /* STRD : cccc 000x xxx0 xxxx xxxx xxxx 1111 xxxx */
1112 /* STREX : cccc 0001 1000 xxxx xxxx xxxx 1001 xxxx */
1113 /* LDREX : cccc 0001 1001 xxxx xxxx xxxx 1001 xxxx */
1114 /* LDRH : cccc 000x xxx1 xxxx xxxx xxxx 1011 xxxx */
1115 /* STRH : cccc 000x xxx0 xxxx xxxx xxxx 1011 xxxx */
1116 /* LDRSB : cccc 000x xxx1 xxxx xxxx xxxx 1101 xxxx */
1117 /* LDRSH : cccc 000x xxx1 xxxx xxxx xxxx 1111 xxxx */
1118 if ((insn & 0x0fb000f0) == 0x01000090) {
1120 return prep_emulate_rd12rn16rm0_wflags(insn, asi);
1121 } else if ((insn & 0x0e1000d0) == 0x00000d0) {
1124 insn |= 0x00002000; /* Rn = r0, Rd = r2 */
1125 if (insn & (1 << 22)) {
1128 insn |= 1; /* Rm = r1 */
1130 asi->insn[0] = insn;
1132 (insn & (1 << 5)) ? emulate_strd : emulate_ldrd;
1136 return prep_emulate_ldr_str(insn, asi);
1139 /* cccc 000x xxxx xxxx xxxx xxxx xxxx xxxx xxxx */
1142 * ALU op with S bit and Rd == 15 :
1143 * cccc 000x xxx1 xxxx 1111 xxxx xxxx xxxx
1145 if ((insn & 0x0e10f000) == 0x0010f000)
1146 return INSN_REJECTED;
1149 * "mov ip, sp" is the most common kprobe'd instruction by far.
1150 * Check and optimize for it explicitly.
1152 if (insn == 0xe1a0c00d) {
1153 asi->insn_handler = simulate_mov_ipsp;
1154 return INSN_GOOD_NO_SLOT;
1158 * Data processing: Immediate-shift / Register-shift
1159 * ALU op : cccc 000x xxxx xxxx xxxx xxxx xxxx xxxx
1160 * CPY : cccc 0001 1010 xxxx xxxx 0000 0000 xxxx
1161 * MOV : cccc 0001 101x xxxx xxxx xxxx xxxx xxxx
1162 * *S (bit 20) updates condition codes
1163 * ADC/SBC/RSC reads the C flag
1165 insn &= 0xfff00ff0; /* Rn = r0, Rd = r0 */
1166 insn |= 0x00000001; /* Rm = r1 */
1168 insn &= 0xfffff0ff; /* register shift */
1169 insn |= 0x00000200; /* Rs = r2 */
1171 asi->insn[0] = insn;
1173 if ((insn & 0x0f900000) == 0x01100000) {
1175 * TST : cccc 0001 0001 xxxx xxxx xxxx xxxx xxxx
1176 * TEQ : cccc 0001 0011 xxxx xxxx xxxx xxxx xxxx
1177 * CMP : cccc 0001 0101 xxxx xxxx xxxx xxxx xxxx
1178 * CMN : cccc 0001 0111 xxxx xxxx xxxx xxxx xxxx
1180 asi->insn_handler = emulate_alu_tests;
1182 /* ALU ops which write to Rd */
1183 asi->insn_handler = (insn & (1 << 20)) ? /* S-bit */
1184 emulate_alu_rwflags : emulate_alu_rflags;
1189 static enum kprobe_insn __kprobes
1190 space_cccc_001x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1193 * MSR : cccc 0011 0x10 xxxx xxxx xxxx xxxx xxxx
1194 * Undef : cccc 0011 0100 xxxx xxxx xxxx xxxx xxxx
1195 * ALU op with S bit and Rd == 15 :
1196 * cccc 001x xxx1 xxxx 1111 xxxx xxxx xxxx
1198 if ((insn & 0x0fb00000) == 0x03200000 || /* MSR */
1199 (insn & 0x0ff00000) == 0x03400000 || /* Undef */
1200 (insn & 0x0e10f000) == 0x0210f000) /* ALU s-bit, R15 */
1201 return INSN_REJECTED;
1204 * Data processing: 32-bit Immediate
1205 * ALU op : cccc 001x xxxx xxxx xxxx xxxx xxxx xxxx
1206 * MOV : cccc 0011 101x xxxx xxxx xxxx xxxx xxxx
1207 * *S (bit 20) updates condition codes
1208 * ADC/SBC/RSC reads the C flag
1210 insn &= 0xfff00fff; /* Rn = r0 and Rd = r0 */
1211 asi->insn[0] = insn;
1213 if ((insn & 0x0f900000) == 0x03100000) {
1215 * TST : cccc 0011 0001 xxxx xxxx xxxx xxxx xxxx
1216 * TEQ : cccc 0011 0011 xxxx xxxx xxxx xxxx xxxx
1217 * CMP : cccc 0011 0101 xxxx xxxx xxxx xxxx xxxx
1218 * CMN : cccc 0011 0111 xxxx xxxx xxxx xxxx xxxx
1220 asi->insn_handler = emulate_alu_tests_imm;
1222 /* ALU ops which write to Rd */
1223 asi->insn_handler = (insn & (1 << 20)) ? /* S-bit */
1224 emulate_alu_imm_rwflags : emulate_alu_imm_rflags;
1229 static enum kprobe_insn __kprobes
1230 space_cccc_0110__1(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1232 /* SEL : cccc 0110 1000 xxxx xxxx xxxx 1011 xxxx GE: !!! */
1233 if ((insn & 0x0ff000f0) == 0x068000b0) {
1234 insn &= 0xfff00ff0; /* Rd = r0, Rn = r0 */
1235 insn |= 0x00000001; /* Rm = r1 */
1236 asi->insn[0] = insn;
1237 asi->insn_handler = emulate_sel;
1241 /* SSAT : cccc 0110 101x xxxx xxxx xxxx xx01 xxxx :Q */
1242 /* USAT : cccc 0110 111x xxxx xxxx xxxx xx01 xxxx :Q */
1243 /* SSAT16 : cccc 0110 1010 xxxx xxxx xxxx 0011 xxxx :Q */
1244 /* USAT16 : cccc 0110 1110 xxxx xxxx xxxx 0011 xxxx :Q */
1245 if ((insn & 0x0fa00030) == 0x06a00010 ||
1246 (insn & 0x0fb000f0) == 0x06a00030) {
1247 insn &= 0xffff0ff0; /* Rd = r0, Rm = r0 */
1248 asi->insn[0] = insn;
1249 asi->insn_handler = emulate_sat;
1253 /* REV : cccc 0110 1011 xxxx xxxx xxxx 0011 xxxx */
1254 /* REV16 : cccc 0110 1011 xxxx xxxx xxxx 1011 xxxx */
1255 /* REVSH : cccc 0110 1111 xxxx xxxx xxxx 1011 xxxx */
1256 if ((insn & 0x0ff00070) == 0x06b00030 ||
1257 (insn & 0x0ff000f0) == 0x06f000b0)
1258 return prep_emulate_rd12rm0(insn, asi);
1260 /* SADD16 : cccc 0110 0001 xxxx xxxx xxxx 0001 xxxx :GE */
1261 /* SADDSUBX : cccc 0110 0001 xxxx xxxx xxxx 0011 xxxx :GE */
1262 /* SSUBADDX : cccc 0110 0001 xxxx xxxx xxxx 0101 xxxx :GE */
1263 /* SSUB16 : cccc 0110 0001 xxxx xxxx xxxx 0111 xxxx :GE */
1264 /* SADD8 : cccc 0110 0001 xxxx xxxx xxxx 1001 xxxx :GE */
1265 /* SSUB8 : cccc 0110 0001 xxxx xxxx xxxx 1111 xxxx :GE */
1266 /* QADD16 : cccc 0110 0010 xxxx xxxx xxxx 0001 xxxx : */
1267 /* QADDSUBX : cccc 0110 0010 xxxx xxxx xxxx 0011 xxxx : */
1268 /* QSUBADDX : cccc 0110 0010 xxxx xxxx xxxx 0101 xxxx : */
1269 /* QSUB16 : cccc 0110 0010 xxxx xxxx xxxx 0111 xxxx : */
1270 /* QADD8 : cccc 0110 0010 xxxx xxxx xxxx 1001 xxxx : */
1271 /* QSUB8 : cccc 0110 0010 xxxx xxxx xxxx 1111 xxxx : */
1272 /* SHADD16 : cccc 0110 0011 xxxx xxxx xxxx 0001 xxxx : */
1273 /* SHADDSUBX : cccc 0110 0011 xxxx xxxx xxxx 0011 xxxx : */
1274 /* SHSUBADDX : cccc 0110 0011 xxxx xxxx xxxx 0101 xxxx : */
1275 /* SHSUB16 : cccc 0110 0011 xxxx xxxx xxxx 0111 xxxx : */
1276 /* SHADD8 : cccc 0110 0011 xxxx xxxx xxxx 1001 xxxx : */
1277 /* SHSUB8 : cccc 0110 0011 xxxx xxxx xxxx 1111 xxxx : */
1278 /* UADD16 : cccc 0110 0101 xxxx xxxx xxxx 0001 xxxx :GE */
1279 /* UADDSUBX : cccc 0110 0101 xxxx xxxx xxxx 0011 xxxx :GE */
1280 /* USUBADDX : cccc 0110 0101 xxxx xxxx xxxx 0101 xxxx :GE */
1281 /* USUB16 : cccc 0110 0101 xxxx xxxx xxxx 0111 xxxx :GE */
1282 /* UADD8 : cccc 0110 0101 xxxx xxxx xxxx 1001 xxxx :GE */
1283 /* USUB8 : cccc 0110 0101 xxxx xxxx xxxx 1111 xxxx :GE */
1284 /* UQADD16 : cccc 0110 0110 xxxx xxxx xxxx 0001 xxxx : */
1285 /* UQADDSUBX : cccc 0110 0110 xxxx xxxx xxxx 0011 xxxx : */
1286 /* UQSUBADDX : cccc 0110 0110 xxxx xxxx xxxx 0101 xxxx : */
1287 /* UQSUB16 : cccc 0110 0110 xxxx xxxx xxxx 0111 xxxx : */
1288 /* UQADD8 : cccc 0110 0110 xxxx xxxx xxxx 1001 xxxx : */
1289 /* UQSUB8 : cccc 0110 0110 xxxx xxxx xxxx 1111 xxxx : */
1290 /* UHADD16 : cccc 0110 0111 xxxx xxxx xxxx 0001 xxxx : */
1291 /* UHADDSUBX : cccc 0110 0111 xxxx xxxx xxxx 0011 xxxx : */
1292 /* UHSUBADDX : cccc 0110 0111 xxxx xxxx xxxx 0101 xxxx : */
1293 /* UHSUB16 : cccc 0110 0111 xxxx xxxx xxxx 0111 xxxx : */
1294 /* UHADD8 : cccc 0110 0111 xxxx xxxx xxxx 1001 xxxx : */
1295 /* UHSUB8 : cccc 0110 0111 xxxx xxxx xxxx 1111 xxxx : */
1296 /* PKHBT : cccc 0110 1000 xxxx xxxx xxxx x001 xxxx : */
1297 /* PKHTB : cccc 0110 1000 xxxx xxxx xxxx x101 xxxx : */
1298 /* SXTAB16 : cccc 0110 1000 xxxx xxxx xxxx 0111 xxxx : */
1299 /* SXTB : cccc 0110 1010 xxxx xxxx xxxx 0111 xxxx : */
1300 /* SXTAB : cccc 0110 1010 xxxx xxxx xxxx 0111 xxxx : */
1301 /* SXTAH : cccc 0110 1011 xxxx xxxx xxxx 0111 xxxx : */
1302 /* UXTAB16 : cccc 0110 1100 xxxx xxxx xxxx 0111 xxxx : */
1303 /* UXTAB : cccc 0110 1110 xxxx xxxx xxxx 0111 xxxx : */
1304 /* UXTAH : cccc 0110 1111 xxxx xxxx xxxx 0111 xxxx : */
1305 return prep_emulate_rd12rn16rm0_wflags(insn, asi);
1308 static enum kprobe_insn __kprobes
1309 space_cccc_0111__1(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1311 /* Undef : cccc 0111 1111 xxxx xxxx xxxx 1111 xxxx */
1312 if ((insn & 0x0ff000f0) == 0x03f000f0)
1313 return INSN_REJECTED;
1315 /* USADA8 : cccc 0111 1000 xxxx xxxx xxxx 0001 xxxx */
1316 /* USAD8 : cccc 0111 1000 xxxx 1111 xxxx 0001 xxxx */
1317 if ((insn & 0x0ff000f0) == 0x07800010)
1318 return prep_emulate_rd16rn12rs8rm0_wflags(insn, asi);
1320 /* SMLALD : cccc 0111 0100 xxxx xxxx xxxx 00x1 xxxx */
1321 /* SMLSLD : cccc 0111 0100 xxxx xxxx xxxx 01x1 xxxx */
1322 if ((insn & 0x0ff00090) == 0x07400010)
1323 return prep_emulate_rdhi16rdlo12rs8rm0_wflags(insn, asi);
1325 /* SMLAD : cccc 0111 0000 xxxx xxxx xxxx 00x1 xxxx :Q */
1326 /* SMLSD : cccc 0111 0000 xxxx xxxx xxxx 01x1 xxxx :Q */
1327 /* SMMLA : cccc 0111 0101 xxxx xxxx xxxx 00x1 xxxx : */
1328 /* SMMLS : cccc 0111 0101 xxxx xxxx xxxx 11x1 xxxx : */
1329 if ((insn & 0x0ff00090) == 0x07000010 ||
1330 (insn & 0x0ff000d0) == 0x07500010 ||
1331 (insn & 0x0ff000d0) == 0x075000d0)
1332 return prep_emulate_rd16rn12rs8rm0_wflags(insn, asi);
1334 /* SMUSD : cccc 0111 0000 xxxx xxxx xxxx 01x1 xxxx : */
1335 /* SMUAD : cccc 0111 0000 xxxx 1111 xxxx 00x1 xxxx :Q */
1336 /* SMMUL : cccc 0111 0101 xxxx 1111 xxxx 00x1 xxxx : */
1337 return prep_emulate_rd16rs8rm0_wflags(insn, asi);
1340 static enum kprobe_insn __kprobes
1341 space_cccc_01xx(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1343 /* LDR : cccc 01xx x0x1 xxxx xxxx xxxx xxxx xxxx */
1344 /* LDRB : cccc 01xx x1x1 xxxx xxxx xxxx xxxx xxxx */
1345 /* LDRBT : cccc 01x0 x111 xxxx xxxx xxxx xxxx xxxx */
1346 /* LDRT : cccc 01x0 x011 xxxx xxxx xxxx xxxx xxxx */
1347 /* STR : cccc 01xx x0x0 xxxx xxxx xxxx xxxx xxxx */
1348 /* STRB : cccc 01xx x1x0 xxxx xxxx xxxx xxxx xxxx */
1349 /* STRBT : cccc 01x0 x110 xxxx xxxx xxxx xxxx xxxx */
1350 /* STRT : cccc 01x0 x010 xxxx xxxx xxxx xxxx xxxx */
1351 return prep_emulate_ldr_str(insn, asi);
1354 static enum kprobe_insn __kprobes
1355 space_cccc_100x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1357 /* LDM(2) : cccc 100x x101 xxxx 0xxx xxxx xxxx xxxx */
1358 /* LDM(3) : cccc 100x x1x1 xxxx 1xxx xxxx xxxx xxxx */
1359 if ((insn & 0x0e708000) == 0x85000000 ||
1360 (insn & 0x0e508000) == 0x85010000)
1361 return INSN_REJECTED;
1363 /* LDM(1) : cccc 100x x0x1 xxxx xxxx xxxx xxxx xxxx */
1364 /* STM(1) : cccc 100x x0x0 xxxx xxxx xxxx xxxx xxxx */
1365 asi->insn_handler = ((insn & 0x108000) == 0x008000) ? /* STM & R15 */
1366 simulate_stm1_pc : simulate_ldm1stm1;
1367 return INSN_GOOD_NO_SLOT;
1370 static enum kprobe_insn __kprobes
1371 space_cccc_101x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1373 /* B : cccc 1010 xxxx xxxx xxxx xxxx xxxx xxxx */
1374 /* BL : cccc 1011 xxxx xxxx xxxx xxxx xxxx xxxx */
1375 asi->insn_handler = simulate_bbl;
1376 return INSN_GOOD_NO_SLOT;
1379 static enum kprobe_insn __kprobes
1380 space_cccc_1100_010x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1382 /* MCRR : cccc 1100 0100 xxxx xxxx xxxx xxxx xxxx : (Rd!=Rn) */
1383 /* MRRC : cccc 1100 0101 xxxx xxxx xxxx xxxx xxxx : (Rd!=Rn) */
1385 insn |= 0x00001000; /* Rn = r0, Rd = r1 */
1386 asi->insn[0] = insn;
1387 asi->insn_handler = (insn & (1 << 20)) ? emulate_mrrc : emulate_mcrr;
1391 static enum kprobe_insn __kprobes
1392 space_cccc_110x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1394 /* LDC : cccc 110x xxx1 xxxx xxxx xxxx xxxx xxxx */
1395 /* STC : cccc 110x xxx0 xxxx xxxx xxxx xxxx xxxx */
1396 insn &= 0xfff0ffff; /* Rn = r0 */
1397 asi->insn[0] = insn;
1398 asi->insn_handler = emulate_ldcstc;
1402 static enum kprobe_insn __kprobes
1403 space_cccc_111x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1405 /* BKPT : 1110 0001 0010 xxxx xxxx xxxx 0111 xxxx */
1406 /* SWI : cccc 1111 xxxx xxxx xxxx xxxx xxxx xxxx */
1407 if ((insn & 0xfff000f0) == 0xe1200070 ||
1408 (insn & 0x0f000000) == 0x0f000000)
1409 return INSN_REJECTED;
1411 /* CDP : cccc 1110 xxxx xxxx xxxx xxxx xxx0 xxxx */
1412 if ((insn & 0x0f000010) == 0x0e000000) {
1413 asi->insn[0] = insn;
1414 asi->insn_handler = emulate_none;
1418 /* MCR : cccc 1110 xxx0 xxxx xxxx xxxx xxx1 xxxx */
1419 /* MRC : cccc 1110 xxx1 xxxx xxxx xxxx xxx1 xxxx */
1420 insn &= 0xffff0fff; /* Rd = r0 */
1421 asi->insn[0] = insn;
1422 asi->insn_handler = (insn & (1 << 20)) ? emulate_rd12 : emulate_ird12;
1426 static unsigned long __kprobes __check_eq(unsigned long cpsr)
1428 return cpsr & PSR_Z_BIT;
1431 static unsigned long __kprobes __check_ne(unsigned long cpsr)
1433 return (~cpsr) & PSR_Z_BIT;
1436 static unsigned long __kprobes __check_cs(unsigned long cpsr)
1438 return cpsr & PSR_C_BIT;
1441 static unsigned long __kprobes __check_cc(unsigned long cpsr)
1443 return (~cpsr) & PSR_C_BIT;
1446 static unsigned long __kprobes __check_mi(unsigned long cpsr)
1448 return cpsr & PSR_N_BIT;
1451 static unsigned long __kprobes __check_pl(unsigned long cpsr)
1453 return (~cpsr) & PSR_N_BIT;
1456 static unsigned long __kprobes __check_vs(unsigned long cpsr)
1458 return cpsr & PSR_V_BIT;
1461 static unsigned long __kprobes __check_vc(unsigned long cpsr)
1463 return (~cpsr) & PSR_V_BIT;
1466 static unsigned long __kprobes __check_hi(unsigned long cpsr)
1468 cpsr &= ~(cpsr >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */
1469 return cpsr & PSR_C_BIT;
1472 static unsigned long __kprobes __check_ls(unsigned long cpsr)
1474 cpsr &= ~(cpsr >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */
1475 return (~cpsr) & PSR_C_BIT;
1478 static unsigned long __kprobes __check_ge(unsigned long cpsr)
1480 cpsr ^= (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
1481 return (~cpsr) & PSR_N_BIT;
1484 static unsigned long __kprobes __check_lt(unsigned long cpsr)
1486 cpsr ^= (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
1487 return cpsr & PSR_N_BIT;
1490 static unsigned long __kprobes __check_gt(unsigned long cpsr)
1492 unsigned long temp = cpsr ^ (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
1493 temp |= (cpsr << 1); /* PSR_N_BIT |= PSR_Z_BIT */
1494 return (~temp) & PSR_N_BIT;
1497 static unsigned long __kprobes __check_le(unsigned long cpsr)
1499 unsigned long temp = cpsr ^ (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
1500 temp |= (cpsr << 1); /* PSR_N_BIT |= PSR_Z_BIT */
1501 return temp & PSR_N_BIT;
1504 static unsigned long __kprobes __check_al(unsigned long cpsr)
1509 static kprobe_check_cc * const condition_checks[16] = {
1510 &__check_eq, &__check_ne, &__check_cs, &__check_cc,
1511 &__check_mi, &__check_pl, &__check_vs, &__check_vc,
1512 &__check_hi, &__check_ls, &__check_ge, &__check_lt,
1513 &__check_gt, &__check_le, &__check_al, &__check_al
1517 * INSN_REJECTED If instruction is one not allowed to kprobe,
1518 * INSN_GOOD If instruction is supported and uses instruction slot,
1519 * INSN_GOOD_NO_SLOT If instruction is supported but doesn't use its slot.
1521 * For instructions we don't want to kprobe (INSN_REJECTED return result):
1522 * These are generally ones that modify the processor state making
1523 * them "hard" to simulate such as switches processor modes or
1524 * make accesses in alternate modes. Any of these could be simulated
1525 * if the work was put into it, but low return considering they
1526 * should also be very rare.
1528 enum kprobe_insn __kprobes
1529 arm_kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1531 asi->insn_check_cc = condition_checks[insn>>28];
1532 asi->insn[1] = KPROBE_RETURN_INSTRUCTION;
1534 if ((insn & 0xf0000000) == 0xf0000000) {
1536 return space_1111(insn, asi);
1538 } else if ((insn & 0x0e000000) == 0x00000000) {
1540 return space_cccc_000x(insn, asi);
1542 } else if ((insn & 0x0e000000) == 0x02000000) {
1544 return space_cccc_001x(insn, asi);
1546 } else if ((insn & 0x0f000010) == 0x06000010) {
1548 return space_cccc_0110__1(insn, asi);
1550 } else if ((insn & 0x0f000010) == 0x07000010) {
1552 return space_cccc_0111__1(insn, asi);
1554 } else if ((insn & 0x0c000000) == 0x04000000) {
1556 return space_cccc_01xx(insn, asi);
1558 } else if ((insn & 0x0e000000) == 0x08000000) {
1560 return space_cccc_100x(insn, asi);
1562 } else if ((insn & 0x0e000000) == 0x0a000000) {
1564 return space_cccc_101x(insn, asi);
1566 } else if ((insn & 0x0fe00000) == 0x0c400000) {
1568 return space_cccc_1100_010x(insn, asi);
1570 } else if ((insn & 0x0e000000) == 0x0c000000) {
1572 return space_cccc_110x(insn, asi);
1576 return space_cccc_111x(insn, asi);
1579 void __init arm_kprobe_decode_init(void)
1581 find_str_pc_offset();
1586 * All ARM instructions listed below.
1588 * Instructions and their general purpose registers are given.
1589 * If a particular register may not use R15, it is prefixed with a "!".
1590 * If marked with a "*" means the value returned by reading R15
1591 * is implementation defined.
1593 * ADC/ADD/AND/BIC/CMN/CMP/EOR/MOV/MVN/ORR/RSB/RSC/SBC/SUB/TEQ
1594 * TST: Rd, Rn, Rm, !Rs
1597 * BX: Rm (R15 legal, but discouraged)
1601 * LDC/2,STC/2 immediate offset & unindex: Rn
1602 * LDC/2,STC/2 immediate pre/post-indexed: !Rn
1603 * LDM(1/3): !Rn, register_list
1604 * LDM(2): !Rn, !register_list
1605 * LDR,STR,PLD immediate offset: Rd, Rn
1606 * LDR,STR,PLD register offset: Rd, Rn, !Rm
1607 * LDR,STR,PLD scaled register offset: Rd, !Rn, !Rm
1608 * LDR,STR immediate pre/post-indexed: Rd, !Rn
1609 * LDR,STR register pre/post-indexed: Rd, !Rn, !Rm
1610 * LDR,STR scaled register pre/post-indexed: Rd, !Rn, !Rm
1611 * LDRB,STRB immediate offset: !Rd, Rn
1612 * LDRB,STRB register offset: !Rd, Rn, !Rm
1613 * LDRB,STRB scaled register offset: !Rd, !Rn, !Rm
1614 * LDRB,STRB immediate pre/post-indexed: !Rd, !Rn
1615 * LDRB,STRB register pre/post-indexed: !Rd, !Rn, !Rm
1616 * LDRB,STRB scaled register pre/post-indexed: !Rd, !Rn, !Rm
1617 * LDRT,LDRBT,STRBT immediate pre/post-indexed: !Rd, !Rn
1618 * LDRT,LDRBT,STRBT register pre/post-indexed: !Rd, !Rn, !Rm
1619 * LDRT,LDRBT,STRBT scaled register pre/post-indexed: !Rd, !Rn, !Rm
1620 * LDRH/SH/SB/D,STRH/SH/SB/D immediate offset: !Rd, Rn
1621 * LDRH/SH/SB/D,STRH/SH/SB/D register offset: !Rd, Rn, !Rm
1622 * LDRH/SH/SB/D,STRH/SH/SB/D immediate pre/post-indexed: !Rd, !Rn
1623 * LDRH/SH/SB/D,STRH/SH/SB/D register pre/post-indexed: !Rd, !Rn, !Rm
1626 * MCRR/2,MRRC/2: !Rd, !Rn
1627 * MLA: !Rd, !Rn, !Rm, !Rs
1629 * MRC/2: !Rd (if Rd==15, only changes cond codes, not the register)
1631 * MUL: !Rd, !Rm, !Rs
1632 * PKH{BT,TB}: !Rd, !Rn, !Rm
1633 * QDADD,[U]QADD/16/8/SUBX: !Rd, !Rm, !Rn
1634 * QDSUB,[U]QSUB/16/8/ADDX: !Rd, !Rm, !Rn
1635 * REV/16/SH: !Rd, !Rm
1637 * {S,U}[H]ADD{16,8,SUBX},{S,U}[H]SUB{16,8,ADDX}: !Rd, !Rn, !Rm
1638 * SEL: !Rd, !Rn, !Rm
1639 * SMLA<x><y>,SMLA{D,W<y>},SMLSD,SMML{A,S}: !Rd, !Rn, !Rm, !Rs
1640 * SMLAL<x><y>,SMLA{D,LD},SMLSLD,SMMULL,SMULW<y>: !RdHi, !RdLo, !Rm, !Rs
1641 * SMMUL,SMUAD,SMUL<x><y>,SMUSD: !Rd, !Rm, !Rs
1643 * STM(1/2): !Rn, register_list* (R15 in reg list not recommended)
1644 * STRT immediate pre/post-indexed: Rd*, !Rn
1645 * STRT register pre/post-indexed: Rd*, !Rn, !Rm
1646 * STRT scaled register pre/post-indexed: Rd*, !Rn, !Rm
1647 * STREX: !Rd, !Rn, !Rm
1648 * SWP/B: !Rd, !Rn, !Rm
1649 * {S,U}XTA{B,B16,H}: !Rd, !Rn, !Rm
1650 * {S,U}XT{B,B16,H}: !Rd, !Rm
1651 * UM{AA,LA,UL}L: !RdHi, !RdLo, !Rm, !Rs
1652 * USA{D8,A8,T,T16}: !Rd, !Rm, !Rs
1654 * May transfer control by writing R15 (possible mode changes or alternate
1655 * mode accesses marked by "*"):
1656 * ALU op (* with s-bit), B, BL, BKPT, BLX(1/2), BX, BXJ, CPS*, CPY,
1657 * LDM(1), LDM(2/3)*, LDR, MOV, RFE*, SWI*
1659 * Instructions that do not take general registers, nor transfer control:
1660 * CDP/2, SETEND, SRS*