2 * arch/arm/kernel/kprobes-decode.c
4 * Copyright (C) 2006, 2007 Motorola Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
17 * We do not have hardware single-stepping on ARM, This
18 * effort is further complicated by the ARM not having a
19 * "next PC" register. Instructions that change the PC
20 * can't be safely single-stepped in a MP environment, so
21 * we have a lot of work to do:
23 * In the prepare phase:
24 * *) If it is an instruction that does anything
25 * with the CPU mode, we reject it for a kprobe.
26 * (This is out of laziness rather than need. The
27 * instructions could be simulated.)
29 * *) Otherwise, decode the instruction rewriting its
30 * registers to take fixed, ordered registers and
31 * setting a handler for it to run the instruction.
33 * In the execution phase by an instruction's handler:
35 * *) If the PC is written to by the instruction, the
36 * instruction must be fully simulated in software.
37 * If it is a conditional instruction, the handler
38 * will use insn[0] to copy its condition code to
39 * set r0 to 1 and insn[1] to "mov pc, lr" to return.
41 * *) Otherwise, a modified form of the instruction is
42 * directly executed. Its handler calls the
43 * instruction in insn[0]. In insn[1] is a
44 * "mov pc, lr" to return.
46 * Before calling, load up the reordered registers
47 * from the original instruction's registers. If one
48 * of the original input registers is the PC, compute
49 * and adjust the appropriate input register.
51 * After call completes, copy the output registers to
52 * the original instruction's original registers.
54 * We don't use a real breakpoint instruction since that
55 * would have us in the kernel go from SVC mode to SVC
56 * mode losing the link register. Instead we use an
57 * undefined instruction. To simplify processing, the
58 * undefined instruction used for kprobes must be reserved
59 * exclusively for kprobes use.
61 * TODO: ifdef out some instruction decoding based on architecture.
64 #include <linux/kernel.h>
65 #include <linux/kprobes.h>
67 #define sign_extend(x, signbit) ((x) | (0 - ((x) & (1 << (signbit)))))
69 #define branch_displacement(insn) sign_extend(((insn) & 0xffffff) << 2, 25)
71 #define is_r15(insn, bitpos) (((insn) & (0xf << bitpos)) == (0xf << bitpos))
74 * Test if load/store instructions writeback the address register.
75 * if P (bit 24) == 0 or W (bit 21) == 1
77 #define is_writeback(insn) ((insn ^ 0x01000000) & 0x01200000)
79 #define PSR_fs (PSR_f|PSR_s)
81 #define KPROBE_RETURN_INSTRUCTION 0xe1a0f00e /* mov pc, lr */
83 typedef long (insn_0arg_fn_t)(void);
84 typedef long (insn_1arg_fn_t)(long);
85 typedef long (insn_2arg_fn_t)(long, long);
86 typedef long (insn_3arg_fn_t)(long, long, long);
87 typedef long (insn_4arg_fn_t)(long, long, long, long);
88 typedef long long (insn_llret_0arg_fn_t)(void);
89 typedef long long (insn_llret_3arg_fn_t)(long, long, long);
90 typedef long long (insn_llret_4arg_fn_t)(long, long, long, long);
94 #ifdef __LITTLE_ENDIAN
95 struct { long r0, r1; };
97 struct { long r1, r0; };
102 * For STR and STM instructions, an ARM core may choose to use either
103 * a +8 or a +12 displacement from the current instruction's address.
104 * Whichever value is chosen for a given core, it must be the same for
105 * both instructions and may not change. This function measures it.
108 static int str_pc_offset;
110 static void __init find_str_pc_offset(void)
112 int addr, scratch, ret;
115 "sub %[ret], pc, #4 \n\t"
116 "str pc, %[addr] \n\t"
117 "ldr %[scr], %[addr] \n\t"
118 "sub %[ret], %[scr], %[ret] \n\t"
119 : [ret] "=r" (ret), [scr] "=r" (scratch), [addr] "+m" (addr));
125 * The insnslot_?arg_r[w]flags() functions below are to keep the
126 * msr -> *fn -> mrs instruction sequences indivisible so that
127 * the state of the CPSR flags aren't inadvertently modified
128 * just before or just after the call.
131 static inline long __kprobes
132 insnslot_0arg_rflags(long cpsr, insn_0arg_fn_t *fn)
134 register long ret asm("r0");
136 __asm__ __volatile__ (
137 "msr cpsr_fs, %[cpsr] \n\t"
141 : [cpsr] "r" (cpsr), [fn] "r" (fn)
147 static inline long long __kprobes
148 insnslot_llret_0arg_rflags(long cpsr, insn_llret_0arg_fn_t *fn)
150 register long ret0 asm("r0");
151 register long ret1 asm("r1");
154 __asm__ __volatile__ (
155 "msr cpsr_fs, %[cpsr] \n\t"
158 : "=r" (ret0), "=r" (ret1)
159 : [cpsr] "r" (cpsr), [fn] "r" (fn)
167 static inline long __kprobes
168 insnslot_1arg_rflags(long r0, long cpsr, insn_1arg_fn_t *fn)
170 register long rr0 asm("r0") = r0;
171 register long ret asm("r0");
173 __asm__ __volatile__ (
174 "msr cpsr_fs, %[cpsr] \n\t"
178 : "0" (rr0), [cpsr] "r" (cpsr), [fn] "r" (fn)
184 static inline long __kprobes
185 insnslot_2arg_rflags(long r0, long r1, long cpsr, insn_2arg_fn_t *fn)
187 register long rr0 asm("r0") = r0;
188 register long rr1 asm("r1") = r1;
189 register long ret asm("r0");
191 __asm__ __volatile__ (
192 "msr cpsr_fs, %[cpsr] \n\t"
196 : "0" (rr0), "r" (rr1),
197 [cpsr] "r" (cpsr), [fn] "r" (fn)
203 static inline long __kprobes
204 insnslot_3arg_rflags(long r0, long r1, long r2, long cpsr, insn_3arg_fn_t *fn)
206 register long rr0 asm("r0") = r0;
207 register long rr1 asm("r1") = r1;
208 register long rr2 asm("r2") = r2;
209 register long ret asm("r0");
211 __asm__ __volatile__ (
212 "msr cpsr_fs, %[cpsr] \n\t"
216 : "0" (rr0), "r" (rr1), "r" (rr2),
217 [cpsr] "r" (cpsr), [fn] "r" (fn)
223 static inline long long __kprobes
224 insnslot_llret_3arg_rflags(long r0, long r1, long r2, long cpsr,
225 insn_llret_3arg_fn_t *fn)
227 register long rr0 asm("r0") = r0;
228 register long rr1 asm("r1") = r1;
229 register long rr2 asm("r2") = r2;
230 register long ret0 asm("r0");
231 register long ret1 asm("r1");
234 __asm__ __volatile__ (
235 "msr cpsr_fs, %[cpsr] \n\t"
238 : "=r" (ret0), "=r" (ret1)
239 : "0" (rr0), "r" (rr1), "r" (rr2),
240 [cpsr] "r" (cpsr), [fn] "r" (fn)
248 static inline long __kprobes
249 insnslot_4arg_rflags(long r0, long r1, long r2, long r3, long cpsr,
252 register long rr0 asm("r0") = r0;
253 register long rr1 asm("r1") = r1;
254 register long rr2 asm("r2") = r2;
255 register long rr3 asm("r3") = r3;
256 register long ret asm("r0");
258 __asm__ __volatile__ (
259 "msr cpsr_fs, %[cpsr] \n\t"
263 : "0" (rr0), "r" (rr1), "r" (rr2), "r" (rr3),
264 [cpsr] "r" (cpsr), [fn] "r" (fn)
270 static inline long __kprobes
271 insnslot_1arg_rwflags(long r0, long *cpsr, insn_1arg_fn_t *fn)
273 register long rr0 asm("r0") = r0;
274 register long ret asm("r0");
275 long oldcpsr = *cpsr;
278 __asm__ __volatile__ (
279 "msr cpsr_fs, %[oldcpsr] \n\t"
282 "mrs %[newcpsr], cpsr \n\t"
283 : "=r" (ret), [newcpsr] "=r" (newcpsr)
284 : "0" (rr0), [oldcpsr] "r" (oldcpsr), [fn] "r" (fn)
287 *cpsr = (oldcpsr & ~PSR_fs) | (newcpsr & PSR_fs);
291 static inline long __kprobes
292 insnslot_2arg_rwflags(long r0, long r1, long *cpsr, insn_2arg_fn_t *fn)
294 register long rr0 asm("r0") = r0;
295 register long rr1 asm("r1") = r1;
296 register long ret asm("r0");
297 long oldcpsr = *cpsr;
300 __asm__ __volatile__ (
301 "msr cpsr_fs, %[oldcpsr] \n\t"
304 "mrs %[newcpsr], cpsr \n\t"
305 : "=r" (ret), [newcpsr] "=r" (newcpsr)
306 : "0" (rr0), "r" (rr1), [oldcpsr] "r" (oldcpsr), [fn] "r" (fn)
309 *cpsr = (oldcpsr & ~PSR_fs) | (newcpsr & PSR_fs);
313 static inline long __kprobes
314 insnslot_3arg_rwflags(long r0, long r1, long r2, long *cpsr,
317 register long rr0 asm("r0") = r0;
318 register long rr1 asm("r1") = r1;
319 register long rr2 asm("r2") = r2;
320 register long ret asm("r0");
321 long oldcpsr = *cpsr;
324 __asm__ __volatile__ (
325 "msr cpsr_fs, %[oldcpsr] \n\t"
328 "mrs %[newcpsr], cpsr \n\t"
329 : "=r" (ret), [newcpsr] "=r" (newcpsr)
330 : "0" (rr0), "r" (rr1), "r" (rr2),
331 [oldcpsr] "r" (oldcpsr), [fn] "r" (fn)
334 *cpsr = (oldcpsr & ~PSR_fs) | (newcpsr & PSR_fs);
338 static inline long __kprobes
339 insnslot_4arg_rwflags(long r0, long r1, long r2, long r3, long *cpsr,
342 register long rr0 asm("r0") = r0;
343 register long rr1 asm("r1") = r1;
344 register long rr2 asm("r2") = r2;
345 register long rr3 asm("r3") = r3;
346 register long ret asm("r0");
347 long oldcpsr = *cpsr;
350 __asm__ __volatile__ (
351 "msr cpsr_fs, %[oldcpsr] \n\t"
354 "mrs %[newcpsr], cpsr \n\t"
355 : "=r" (ret), [newcpsr] "=r" (newcpsr)
356 : "0" (rr0), "r" (rr1), "r" (rr2), "r" (rr3),
357 [oldcpsr] "r" (oldcpsr), [fn] "r" (fn)
360 *cpsr = (oldcpsr & ~PSR_fs) | (newcpsr & PSR_fs);
364 static inline long long __kprobes
365 insnslot_llret_4arg_rwflags(long r0, long r1, long r2, long r3, long *cpsr,
366 insn_llret_4arg_fn_t *fn)
368 register long rr0 asm("r0") = r0;
369 register long rr1 asm("r1") = r1;
370 register long rr2 asm("r2") = r2;
371 register long rr3 asm("r3") = r3;
372 register long ret0 asm("r0");
373 register long ret1 asm("r1");
374 long oldcpsr = *cpsr;
378 __asm__ __volatile__ (
379 "msr cpsr_fs, %[oldcpsr] \n\t"
382 "mrs %[newcpsr], cpsr \n\t"
383 : "=r" (ret0), "=r" (ret1), [newcpsr] "=r" (newcpsr)
384 : "0" (rr0), "r" (rr1), "r" (rr2), "r" (rr3),
385 [oldcpsr] "r" (oldcpsr), [fn] "r" (fn)
388 *cpsr = (oldcpsr & ~PSR_fs) | (newcpsr & PSR_fs);
395 * To avoid the complications of mimicing single-stepping on a
396 * processor without a Next-PC or a single-step mode, and to
397 * avoid having to deal with the side-effects of boosting, we
398 * simulate or emulate (almost) all ARM instructions.
400 * "Simulation" is where the instruction's behavior is duplicated in
401 * C code. "Emulation" is where the original instruction is rewritten
402 * and executed, often by altering its registers.
404 * By having all behavior of the kprobe'd instruction completed before
405 * returning from the kprobe_handler(), all locks (scheduler and
406 * interrupt) can safely be released. There is no need for secondary
407 * breakpoints, no race with MP or preemptable kernels, nor having to
408 * clean up resources counts at a later time impacting overall system
409 * performance. By rewriting the instruction, only the minimum registers
410 * need to be loaded and saved back optimizing performance.
412 * Calling the insnslot_*_rwflags version of a function doesn't hurt
413 * anything even when the CPSR flags aren't updated by the
414 * instruction. It's just a little slower in return for saving
415 * a little space by not having a duplicate function that doesn't
416 * update the flags. (The same optimization can be said for
417 * instructions that do or don't perform register writeback)
418 * Also, instructions can either read the flags, only write the
419 * flags, or read and write the flags. To save combinations
420 * rather than for sheer performance, flag functions just assume
421 * read and write of flags.
424 static void __kprobes simulate_bbl(struct kprobe *p, struct pt_regs *regs)
426 kprobe_opcode_t insn = p->opcode;
427 long iaddr = (long)p->addr;
428 int disp = branch_displacement(insn);
430 if (insn & (1 << 24))
431 regs->ARM_lr = iaddr + 4;
433 regs->ARM_pc = iaddr + 8 + disp;
436 static void __kprobes simulate_blx1(struct kprobe *p, struct pt_regs *regs)
438 kprobe_opcode_t insn = p->opcode;
439 long iaddr = (long)p->addr;
440 int disp = branch_displacement(insn);
442 regs->ARM_lr = iaddr + 4;
443 regs->ARM_pc = iaddr + 8 + disp + ((insn >> 23) & 0x2);
444 regs->ARM_cpsr |= PSR_T_BIT;
447 static void __kprobes simulate_blx2bx(struct kprobe *p, struct pt_regs *regs)
449 kprobe_opcode_t insn = p->opcode;
451 long rmv = regs->uregs[rm];
454 regs->ARM_lr = (long)p->addr + 4;
456 regs->ARM_pc = rmv & ~0x1;
457 regs->ARM_cpsr &= ~PSR_T_BIT;
459 regs->ARM_cpsr |= PSR_T_BIT;
462 static void __kprobes simulate_mrs(struct kprobe *p, struct pt_regs *regs)
464 kprobe_opcode_t insn = p->opcode;
465 int rd = (insn >> 12) & 0xf;
466 unsigned long mask = 0xf8ff03df; /* Mask out execution state */
467 regs->uregs[rd] = regs->ARM_cpsr & mask;
470 static void __kprobes simulate_ldm1stm1(struct kprobe *p, struct pt_regs *regs)
472 kprobe_opcode_t insn = p->opcode;
473 int rn = (insn >> 16) & 0xf;
474 int lbit = insn & (1 << 20);
475 int wbit = insn & (1 << 21);
476 int ubit = insn & (1 << 23);
477 int pbit = insn & (1 << 24);
478 long *addr = (long *)regs->uregs[rn];
483 reg_bit_vector = insn & 0xffff;
484 while (reg_bit_vector) {
485 reg_bit_vector &= (reg_bit_vector - 1);
491 addr += (!pbit == !ubit);
493 reg_bit_vector = insn & 0xffff;
494 while (reg_bit_vector) {
495 int reg = __ffs(reg_bit_vector);
496 reg_bit_vector &= (reg_bit_vector - 1);
498 regs->uregs[reg] = *addr++;
500 *addr++ = regs->uregs[reg];
506 addr -= (!pbit == !ubit);
507 regs->uregs[rn] = (long)addr;
511 static void __kprobes simulate_stm1_pc(struct kprobe *p, struct pt_regs *regs)
513 regs->ARM_pc = (long)p->addr + str_pc_offset;
514 simulate_ldm1stm1(p, regs);
515 regs->ARM_pc = (long)p->addr + 4;
518 static void __kprobes simulate_mov_ipsp(struct kprobe *p, struct pt_regs *regs)
520 regs->uregs[12] = regs->uregs[13];
523 static void __kprobes emulate_ldcstc(struct kprobe *p, struct pt_regs *regs)
525 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
526 kprobe_opcode_t insn = p->opcode;
527 int rn = (insn >> 16) & 0xf;
528 long rnv = regs->uregs[rn];
530 /* Save Rn in case of writeback. */
531 regs->uregs[rn] = insnslot_1arg_rflags(rnv, regs->ARM_cpsr, i_fn);
534 static void __kprobes emulate_ldrd(struct kprobe *p, struct pt_regs *regs)
536 insn_2arg_fn_t *i_fn = (insn_2arg_fn_t *)&p->ainsn.insn[0];
537 kprobe_opcode_t insn = p->opcode;
538 long ppc = (long)p->addr + 8;
539 int rd = (insn >> 12) & 0xf;
540 int rn = (insn >> 16) & 0xf;
541 int rm = insn & 0xf; /* rm may be invalid, don't care. */
542 long rmv = (rm == 15) ? ppc : regs->uregs[rm];
543 long rnv = (rn == 15) ? ppc : regs->uregs[rn];
545 /* Not following the C calling convention here, so need asm(). */
546 __asm__ __volatile__ (
549 "msr cpsr_fs, %[cpsr]\n\t"
551 "mov pc, %[i_fn] \n\t"
552 "str r0, %[rn] \n\t" /* in case of writeback */
553 "str r2, %[rd0] \n\t"
554 "str r3, %[rd1] \n\t"
556 [rd0] "=m" (regs->uregs[rd]),
557 [rd1] "=m" (regs->uregs[rd+1])
559 [cpsr] "r" (regs->ARM_cpsr),
561 : "r0", "r1", "r2", "r3", "lr", "cc"
563 if (is_writeback(insn))
564 regs->uregs[rn] = rnv;
567 static void __kprobes emulate_strd(struct kprobe *p, struct pt_regs *regs)
569 insn_4arg_fn_t *i_fn = (insn_4arg_fn_t *)&p->ainsn.insn[0];
570 kprobe_opcode_t insn = p->opcode;
571 long ppc = (long)p->addr + 8;
572 int rd = (insn >> 12) & 0xf;
573 int rn = (insn >> 16) & 0xf;
575 long rnv = (rn == 15) ? ppc : regs->uregs[rn];
576 /* rm/rmv may be invalid, don't care. */
577 long rmv = (rm == 15) ? ppc : regs->uregs[rm];
580 rnv_wb = insnslot_4arg_rflags(rnv, rmv, regs->uregs[rd],
582 regs->ARM_cpsr, i_fn);
583 if (is_writeback(insn))
584 regs->uregs[rn] = rnv_wb;
587 static void __kprobes emulate_ldr(struct kprobe *p, struct pt_regs *regs)
589 insn_llret_3arg_fn_t *i_fn = (insn_llret_3arg_fn_t *)&p->ainsn.insn[0];
590 kprobe_opcode_t insn = p->opcode;
591 long ppc = (long)p->addr + 8;
593 int rd = (insn >> 12) & 0xf;
594 int rn = (insn >> 16) & 0xf;
597 long rnv = (rn == 15) ? ppc : regs->uregs[rn];
598 long rmv = (rm == 15) ? ppc : regs->uregs[rm];
599 long cpsr = regs->ARM_cpsr;
601 fnr.dr = insnslot_llret_3arg_rflags(rnv, 0, rmv, cpsr, i_fn);
603 regs->uregs[rn] = fnr.r0; /* Save Rn in case of writeback. */
607 #if __LINUX_ARM_ARCH__ >= 5
611 regs->ARM_cpsr = cpsr;
617 regs->uregs[rd] = rdv;
620 static void __kprobes emulate_str(struct kprobe *p, struct pt_regs *regs)
622 insn_3arg_fn_t *i_fn = (insn_3arg_fn_t *)&p->ainsn.insn[0];
623 kprobe_opcode_t insn = p->opcode;
624 long iaddr = (long)p->addr;
625 int rd = (insn >> 12) & 0xf;
626 int rn = (insn >> 16) & 0xf;
628 long rdv = (rd == 15) ? iaddr + str_pc_offset : regs->uregs[rd];
629 long rnv = (rn == 15) ? iaddr + 8 : regs->uregs[rn];
630 long rmv = regs->uregs[rm]; /* rm/rmv may be invalid, don't care. */
633 rnv_wb = insnslot_3arg_rflags(rnv, rdv, rmv, regs->ARM_cpsr, i_fn);
635 regs->uregs[rn] = rnv_wb; /* Save Rn in case of writeback. */
638 static void __kprobes emulate_mrrc(struct kprobe *p, struct pt_regs *regs)
640 insn_llret_0arg_fn_t *i_fn = (insn_llret_0arg_fn_t *)&p->ainsn.insn[0];
641 kprobe_opcode_t insn = p->opcode;
643 int rd = (insn >> 12) & 0xf;
644 int rn = (insn >> 16) & 0xf;
646 fnr.dr = insnslot_llret_0arg_rflags(regs->ARM_cpsr, i_fn);
647 regs->uregs[rn] = fnr.r0;
648 regs->uregs[rd] = fnr.r1;
651 static void __kprobes emulate_mcrr(struct kprobe *p, struct pt_regs *regs)
653 insn_2arg_fn_t *i_fn = (insn_2arg_fn_t *)&p->ainsn.insn[0];
654 kprobe_opcode_t insn = p->opcode;
655 int rd = (insn >> 12) & 0xf;
656 int rn = (insn >> 16) & 0xf;
657 long rnv = regs->uregs[rn];
658 long rdv = regs->uregs[rd];
660 insnslot_2arg_rflags(rnv, rdv, regs->ARM_cpsr, i_fn);
663 static void __kprobes emulate_sat(struct kprobe *p, struct pt_regs *regs)
665 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
666 kprobe_opcode_t insn = p->opcode;
667 int rd = (insn >> 12) & 0xf;
669 long rmv = regs->uregs[rm];
672 regs->uregs[rd] = insnslot_1arg_rwflags(rmv, ®s->ARM_cpsr, i_fn);
675 static void __kprobes emulate_sel(struct kprobe *p, struct pt_regs *regs)
677 insn_2arg_fn_t *i_fn = (insn_2arg_fn_t *)&p->ainsn.insn[0];
678 kprobe_opcode_t insn = p->opcode;
679 int rd = (insn >> 12) & 0xf;
680 int rn = (insn >> 16) & 0xf;
682 long rnv = regs->uregs[rn];
683 long rmv = regs->uregs[rm];
686 regs->uregs[rd] = insnslot_2arg_rflags(rnv, rmv, regs->ARM_cpsr, i_fn);
689 static void __kprobes emulate_none(struct kprobe *p, struct pt_regs *regs)
691 insn_0arg_fn_t *i_fn = (insn_0arg_fn_t *)&p->ainsn.insn[0];
693 insnslot_0arg_rflags(regs->ARM_cpsr, i_fn);
696 static void __kprobes emulate_rd12(struct kprobe *p, struct pt_regs *regs)
698 insn_0arg_fn_t *i_fn = (insn_0arg_fn_t *)&p->ainsn.insn[0];
699 kprobe_opcode_t insn = p->opcode;
700 int rd = (insn >> 12) & 0xf;
702 regs->uregs[rd] = insnslot_0arg_rflags(regs->ARM_cpsr, i_fn);
705 static void __kprobes emulate_ird12(struct kprobe *p, struct pt_regs *regs)
707 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
708 kprobe_opcode_t insn = p->opcode;
709 int ird = (insn >> 12) & 0xf;
711 insnslot_1arg_rflags(regs->uregs[ird], regs->ARM_cpsr, i_fn);
714 static void __kprobes emulate_rn16(struct kprobe *p, struct pt_regs *regs)
716 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
717 kprobe_opcode_t insn = p->opcode;
718 int rn = (insn >> 16) & 0xf;
719 long rnv = regs->uregs[rn];
721 insnslot_1arg_rflags(rnv, regs->ARM_cpsr, i_fn);
724 static void __kprobes emulate_rd12rm0(struct kprobe *p, struct pt_regs *regs)
726 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
727 kprobe_opcode_t insn = p->opcode;
728 int rd = (insn >> 12) & 0xf;
730 long rmv = regs->uregs[rm];
732 regs->uregs[rd] = insnslot_1arg_rflags(rmv, regs->ARM_cpsr, i_fn);
735 static void __kprobes
736 emulate_rd12rn16rm0_rwflags(struct kprobe *p, struct pt_regs *regs)
738 insn_2arg_fn_t *i_fn = (insn_2arg_fn_t *)&p->ainsn.insn[0];
739 kprobe_opcode_t insn = p->opcode;
740 int rd = (insn >> 12) & 0xf;
741 int rn = (insn >> 16) & 0xf;
743 long rnv = regs->uregs[rn];
744 long rmv = regs->uregs[rm];
747 insnslot_2arg_rwflags(rnv, rmv, ®s->ARM_cpsr, i_fn);
750 static void __kprobes
751 emulate_rd16rn12rs8rm0_rwflags(struct kprobe *p, struct pt_regs *regs)
753 insn_3arg_fn_t *i_fn = (insn_3arg_fn_t *)&p->ainsn.insn[0];
754 kprobe_opcode_t insn = p->opcode;
755 int rd = (insn >> 16) & 0xf;
756 int rn = (insn >> 12) & 0xf;
757 int rs = (insn >> 8) & 0xf;
759 long rnv = regs->uregs[rn];
760 long rsv = regs->uregs[rs];
761 long rmv = regs->uregs[rm];
764 insnslot_3arg_rwflags(rnv, rsv, rmv, ®s->ARM_cpsr, i_fn);
767 static void __kprobes
768 emulate_rd16rs8rm0_rwflags(struct kprobe *p, struct pt_regs *regs)
770 insn_2arg_fn_t *i_fn = (insn_2arg_fn_t *)&p->ainsn.insn[0];
771 kprobe_opcode_t insn = p->opcode;
772 int rd = (insn >> 16) & 0xf;
773 int rs = (insn >> 8) & 0xf;
775 long rsv = regs->uregs[rs];
776 long rmv = regs->uregs[rm];
779 insnslot_2arg_rwflags(rsv, rmv, ®s->ARM_cpsr, i_fn);
782 static void __kprobes
783 emulate_rdhi16rdlo12rs8rm0_rwflags(struct kprobe *p, struct pt_regs *regs)
785 insn_llret_4arg_fn_t *i_fn = (insn_llret_4arg_fn_t *)&p->ainsn.insn[0];
786 kprobe_opcode_t insn = p->opcode;
788 int rdhi = (insn >> 16) & 0xf;
789 int rdlo = (insn >> 12) & 0xf;
790 int rs = (insn >> 8) & 0xf;
792 long rsv = regs->uregs[rs];
793 long rmv = regs->uregs[rm];
795 fnr.dr = insnslot_llret_4arg_rwflags(regs->uregs[rdhi],
796 regs->uregs[rdlo], rsv, rmv,
797 ®s->ARM_cpsr, i_fn);
798 regs->uregs[rdhi] = fnr.r0;
799 regs->uregs[rdlo] = fnr.r1;
802 static void __kprobes
803 emulate_alu_imm_rflags(struct kprobe *p, struct pt_regs *regs)
805 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
806 kprobe_opcode_t insn = p->opcode;
807 int rd = (insn >> 12) & 0xf;
808 int rn = (insn >> 16) & 0xf;
809 long rnv = (rn == 15) ? (long)p->addr + 8 : regs->uregs[rn];
811 regs->uregs[rd] = insnslot_1arg_rflags(rnv, regs->ARM_cpsr, i_fn);
814 static void __kprobes
815 emulate_alu_imm_rwflags(struct kprobe *p, struct pt_regs *regs)
817 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
818 kprobe_opcode_t insn = p->opcode;
819 int rd = (insn >> 12) & 0xf;
820 int rn = (insn >> 16) & 0xf;
821 long rnv = (rn == 15) ? (long)p->addr + 8 : regs->uregs[rn];
823 regs->uregs[rd] = insnslot_1arg_rwflags(rnv, ®s->ARM_cpsr, i_fn);
826 static void __kprobes
827 emulate_alu_tests_imm(struct kprobe *p, struct pt_regs *regs)
829 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
830 kprobe_opcode_t insn = p->opcode;
831 int rn = (insn >> 16) & 0xf;
832 long rnv = (rn == 15) ? (long)p->addr + 8 : regs->uregs[rn];
834 insnslot_1arg_rwflags(rnv, ®s->ARM_cpsr, i_fn);
837 static void __kprobes
838 emulate_alu_rflags(struct kprobe *p, struct pt_regs *regs)
840 insn_3arg_fn_t *i_fn = (insn_3arg_fn_t *)&p->ainsn.insn[0];
841 kprobe_opcode_t insn = p->opcode;
842 long ppc = (long)p->addr + 8;
843 int rd = (insn >> 12) & 0xf;
844 int rn = (insn >> 16) & 0xf; /* rn/rnv/rs/rsv may be */
845 int rs = (insn >> 8) & 0xf; /* invalid, don't care. */
847 long rnv = (rn == 15) ? ppc : regs->uregs[rn];
848 long rmv = (rm == 15) ? ppc : regs->uregs[rm];
849 long rsv = regs->uregs[rs];
852 insnslot_3arg_rflags(rnv, rmv, rsv, regs->ARM_cpsr, i_fn);
855 static void __kprobes
856 emulate_alu_rwflags(struct kprobe *p, struct pt_regs *regs)
858 insn_3arg_fn_t *i_fn = (insn_3arg_fn_t *)&p->ainsn.insn[0];
859 kprobe_opcode_t insn = p->opcode;
860 long ppc = (long)p->addr + 8;
861 int rd = (insn >> 12) & 0xf;
862 int rn = (insn >> 16) & 0xf; /* rn/rnv/rs/rsv may be */
863 int rs = (insn >> 8) & 0xf; /* invalid, don't care. */
865 long rnv = (rn == 15) ? ppc : regs->uregs[rn];
866 long rmv = (rm == 15) ? ppc : regs->uregs[rm];
867 long rsv = regs->uregs[rs];
870 insnslot_3arg_rwflags(rnv, rmv, rsv, ®s->ARM_cpsr, i_fn);
873 static void __kprobes
874 emulate_alu_tests(struct kprobe *p, struct pt_regs *regs)
876 insn_3arg_fn_t *i_fn = (insn_3arg_fn_t *)&p->ainsn.insn[0];
877 kprobe_opcode_t insn = p->opcode;
878 long ppc = (long)p->addr + 8;
879 int rn = (insn >> 16) & 0xf;
880 int rs = (insn >> 8) & 0xf; /* rs/rsv may be invalid, don't care. */
882 long rnv = (rn == 15) ? ppc : regs->uregs[rn];
883 long rmv = (rm == 15) ? ppc : regs->uregs[rm];
884 long rsv = regs->uregs[rs];
886 insnslot_3arg_rwflags(rnv, rmv, rsv, ®s->ARM_cpsr, i_fn);
889 static enum kprobe_insn __kprobes
890 prep_emulate_ldr_str(kprobe_opcode_t insn, struct arch_specific_insn *asi)
892 int not_imm = (insn & (1 << 26)) ? (insn & (1 << 25))
893 : (~insn & (1 << 22));
895 if (is_writeback(insn) && is_r15(insn, 16))
896 return INSN_REJECTED; /* Writeback to PC */
899 insn |= 0x00001000; /* Rn = r0, Rd = r1 */
902 insn |= 2; /* Rm = r2 */
905 asi->insn_handler = (insn & (1 << 20)) ? emulate_ldr : emulate_str;
909 static enum kprobe_insn __kprobes
910 prep_emulate_rd12rm0(kprobe_opcode_t insn, struct arch_specific_insn *asi)
912 if (is_r15(insn, 12))
913 return INSN_REJECTED; /* Rd is PC */
915 insn &= 0xffff0ff0; /* Rd = r0, Rm = r0 */
917 asi->insn_handler = emulate_rd12rm0;
921 static enum kprobe_insn __kprobes
922 prep_emulate_rd12rn16rm0_wflags(kprobe_opcode_t insn,
923 struct arch_specific_insn *asi)
925 if (is_r15(insn, 12))
926 return INSN_REJECTED; /* Rd is PC */
928 insn &= 0xfff00ff0; /* Rd = r0, Rn = r0 */
929 insn |= 0x00000001; /* Rm = r1 */
931 asi->insn_handler = emulate_rd12rn16rm0_rwflags;
935 static enum kprobe_insn __kprobes
936 prep_emulate_rd16rs8rm0_wflags(kprobe_opcode_t insn,
937 struct arch_specific_insn *asi)
939 if (is_r15(insn, 16))
940 return INSN_REJECTED; /* Rd is PC */
942 insn &= 0xfff0f0f0; /* Rd = r0, Rs = r0 */
943 insn |= 0x00000001; /* Rm = r1 */
945 asi->insn_handler = emulate_rd16rs8rm0_rwflags;
949 static enum kprobe_insn __kprobes
950 prep_emulate_rd16rn12rs8rm0_wflags(kprobe_opcode_t insn,
951 struct arch_specific_insn *asi)
953 if (is_r15(insn, 16))
954 return INSN_REJECTED; /* Rd is PC */
956 insn &= 0xfff000f0; /* Rd = r0, Rn = r0 */
957 insn |= 0x00000102; /* Rs = r1, Rm = r2 */
959 asi->insn_handler = emulate_rd16rn12rs8rm0_rwflags;
963 static enum kprobe_insn __kprobes
964 prep_emulate_rdhi16rdlo12rs8rm0_wflags(kprobe_opcode_t insn,
965 struct arch_specific_insn *asi)
967 if (is_r15(insn, 16) || is_r15(insn, 12))
968 return INSN_REJECTED; /* RdHi or RdLo is PC */
970 insn &= 0xfff000f0; /* RdHi = r0, RdLo = r1 */
971 insn |= 0x00001203; /* Rs = r2, Rm = r3 */
973 asi->insn_handler = emulate_rdhi16rdlo12rs8rm0_rwflags;
978 * For the instruction masking and comparisons in all the "space_*"
979 * functions below, Do _not_ rearrange the order of tests unless
980 * you're very, very sure of what you are doing. For the sake of
981 * efficiency, the masks for some tests sometimes assume other test
982 * have been done prior to them so the number of patterns to test
983 * for an instruction set can be as broad as possible to reduce the
984 * number of tests needed.
987 static enum kprobe_insn __kprobes
988 space_1111(kprobe_opcode_t insn, struct arch_specific_insn *asi)
990 /* CPS mmod == 1 : 1111 0001 0000 xx10 xxxx xxxx xx0x xxxx */
991 /* RFE : 1111 100x x0x1 xxxx xxxx 1010 xxxx xxxx */
992 /* SRS : 1111 100x x1x0 1101 xxxx 0101 xxxx xxxx */
993 if ((insn & 0xfff30020) == 0xf1020000 ||
994 (insn & 0xfe500f00) == 0xf8100a00 ||
995 (insn & 0xfe5f0f00) == 0xf84d0500)
996 return INSN_REJECTED;
998 /* PLD : 1111 01x1 x101 xxxx xxxx xxxx xxxx xxxx : */
999 if ((insn & 0xfd700000) == 0xf4500000) {
1000 insn &= 0xfff0ffff; /* Rn = r0 */
1001 asi->insn[0] = insn;
1002 asi->insn_handler = emulate_rn16;
1006 /* BLX(1) : 1111 101x xxxx xxxx xxxx xxxx xxxx xxxx : */
1007 if ((insn & 0xfe000000) == 0xfa000000) {
1008 asi->insn_handler = simulate_blx1;
1009 return INSN_GOOD_NO_SLOT;
1012 /* SETEND : 1111 0001 0000 0001 xxxx xxxx 0000 xxxx */
1013 /* CDP2 : 1111 1110 xxxx xxxx xxxx xxxx xxx0 xxxx */
1014 if ((insn & 0xffff00f0) == 0xf1010000 ||
1015 (insn & 0xff000010) == 0xfe000000) {
1016 asi->insn[0] = insn;
1017 asi->insn_handler = emulate_none;
1021 /* MCRR2 : 1111 1100 0100 xxxx xxxx xxxx xxxx xxxx : (Rd != Rn) */
1022 /* MRRC2 : 1111 1100 0101 xxxx xxxx xxxx xxxx xxxx : (Rd != Rn) */
1023 if ((insn & 0xffe00000) == 0xfc400000) {
1024 insn &= 0xfff00fff; /* Rn = r0 */
1025 insn |= 0x00001000; /* Rd = r1 */
1026 asi->insn[0] = insn;
1028 (insn & (1 << 20)) ? emulate_mrrc : emulate_mcrr;
1032 /* LDC2 : 1111 110x xxx1 xxxx xxxx xxxx xxxx xxxx */
1033 /* STC2 : 1111 110x xxx0 xxxx xxxx xxxx xxxx xxxx */
1034 if ((insn & 0xfe000000) == 0xfc000000) {
1035 insn &= 0xfff0ffff; /* Rn = r0 */
1036 asi->insn[0] = insn;
1037 asi->insn_handler = emulate_ldcstc;
1041 /* MCR2 : 1111 1110 xxx0 xxxx xxxx xxxx xxx1 xxxx */
1042 /* MRC2 : 1111 1110 xxx1 xxxx xxxx xxxx xxx1 xxxx */
1043 insn &= 0xffff0fff; /* Rd = r0 */
1044 asi->insn[0] = insn;
1045 asi->insn_handler = (insn & (1 << 20)) ? emulate_rd12 : emulate_ird12;
1049 static enum kprobe_insn __kprobes
1050 space_cccc_000x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1052 /* cccc 0001 0xx0 xxxx xxxx xxxx xxxx xxx0 xxxx */
1053 if ((insn & 0x0f900010) == 0x01000000) {
1055 /* BXJ : cccc 0001 0010 xxxx xxxx xxxx 0010 xxxx */
1056 /* MSR : cccc 0001 0x10 xxxx xxxx xxxx 0000 xxxx */
1057 /* MRS spsr : cccc 0001 0100 xxxx xxxx xxxx 0000 xxxx */
1058 if ((insn & 0x0ff000f0) == 0x01200020 ||
1059 (insn & 0x0fb000f0) == 0x01200000 ||
1060 (insn & 0x0ff000f0) == 0x01400000)
1061 return INSN_REJECTED;
1063 /* MRS cpsr : cccc 0001 0000 xxxx xxxx xxxx 0000 xxxx */
1064 if ((insn & 0x0ff000f0) == 0x01000000) {
1065 if (is_r15(insn, 12))
1066 return INSN_REJECTED; /* Rd is PC */
1067 asi->insn_handler = simulate_mrs;
1068 return INSN_GOOD_NO_SLOT;
1071 /* SMLALxy : cccc 0001 0100 xxxx xxxx xxxx 1xx0 xxxx */
1072 if ((insn & 0x0ff00090) == 0x01400080)
1073 return prep_emulate_rdhi16rdlo12rs8rm0_wflags(insn, asi);
1075 /* SMULWy : cccc 0001 0010 xxxx xxxx xxxx 1x10 xxxx */
1076 /* SMULxy : cccc 0001 0110 xxxx xxxx xxxx 1xx0 xxxx */
1077 if ((insn & 0x0ff000b0) == 0x012000a0 ||
1078 (insn & 0x0ff00090) == 0x01600080)
1079 return prep_emulate_rd16rs8rm0_wflags(insn, asi);
1081 /* SMLAxy : cccc 0001 0000 xxxx xxxx xxxx 1xx0 xxxx : Q */
1082 /* SMLAWy : cccc 0001 0010 xxxx xxxx xxxx 1x00 xxxx : Q */
1083 return prep_emulate_rd16rn12rs8rm0_wflags(insn, asi);
1087 /* cccc 0001 0xx0 xxxx xxxx xxxx xxxx 0xx1 xxxx */
1088 else if ((insn & 0x0f900090) == 0x01000010) {
1090 /* BKPT : 1110 0001 0010 xxxx xxxx xxxx 0111 xxxx */
1091 if ((insn & 0xfff000f0) == 0xe1200070)
1092 return INSN_REJECTED;
1094 /* BLX(2) : cccc 0001 0010 xxxx xxxx xxxx 0011 xxxx */
1095 /* BX : cccc 0001 0010 xxxx xxxx xxxx 0001 xxxx */
1096 if ((insn & 0x0ff000d0) == 0x01200010) {
1097 if ((insn & 0x0ff000ff) == 0x0120003f)
1098 return INSN_REJECTED; /* BLX pc */
1099 asi->insn_handler = simulate_blx2bx;
1100 return INSN_GOOD_NO_SLOT;
1103 /* CLZ : cccc 0001 0110 xxxx xxxx xxxx 0001 xxxx */
1104 if ((insn & 0x0ff000f0) == 0x01600010)
1105 return prep_emulate_rd12rm0(insn, asi);
1107 /* QADD : cccc 0001 0000 xxxx xxxx xxxx 0101 xxxx :Q */
1108 /* QSUB : cccc 0001 0010 xxxx xxxx xxxx 0101 xxxx :Q */
1109 /* QDADD : cccc 0001 0100 xxxx xxxx xxxx 0101 xxxx :Q */
1110 /* QDSUB : cccc 0001 0110 xxxx xxxx xxxx 0101 xxxx :Q */
1111 return prep_emulate_rd12rn16rm0_wflags(insn, asi);
1114 /* cccc 0000 xxxx xxxx xxxx xxxx xxxx 1001 xxxx */
1115 else if ((insn & 0x0f0000f0) == 0x00000090) {
1117 /* MUL : cccc 0000 0000 xxxx xxxx xxxx 1001 xxxx : */
1118 /* MULS : cccc 0000 0001 xxxx xxxx xxxx 1001 xxxx :cc */
1119 /* MLA : cccc 0000 0010 xxxx xxxx xxxx 1001 xxxx : */
1120 /* MLAS : cccc 0000 0011 xxxx xxxx xxxx 1001 xxxx :cc */
1121 /* UMAAL : cccc 0000 0100 xxxx xxxx xxxx 1001 xxxx : */
1122 /* undef : cccc 0000 0101 xxxx xxxx xxxx 1001 xxxx : */
1123 /* MLS : cccc 0000 0110 xxxx xxxx xxxx 1001 xxxx : */
1124 /* undef : cccc 0000 0111 xxxx xxxx xxxx 1001 xxxx : */
1125 /* UMULL : cccc 0000 1000 xxxx xxxx xxxx 1001 xxxx : */
1126 /* UMULLS : cccc 0000 1001 xxxx xxxx xxxx 1001 xxxx :cc */
1127 /* UMLAL : cccc 0000 1010 xxxx xxxx xxxx 1001 xxxx : */
1128 /* UMLALS : cccc 0000 1011 xxxx xxxx xxxx 1001 xxxx :cc */
1129 /* SMULL : cccc 0000 1100 xxxx xxxx xxxx 1001 xxxx : */
1130 /* SMULLS : cccc 0000 1101 xxxx xxxx xxxx 1001 xxxx :cc */
1131 /* SMLAL : cccc 0000 1110 xxxx xxxx xxxx 1001 xxxx : */
1132 /* SMLALS : cccc 0000 1111 xxxx xxxx xxxx 1001 xxxx :cc */
1133 if ((insn & 0x00d00000) == 0x00500000) {
1134 return INSN_REJECTED;
1135 } else if ((insn & 0x00e00000) == 0x00000000) {
1136 return prep_emulate_rd16rs8rm0_wflags(insn, asi);
1137 } else if ((insn & 0x00a00000) == 0x00200000) {
1138 return prep_emulate_rd16rn12rs8rm0_wflags(insn, asi);
1140 return prep_emulate_rdhi16rdlo12rs8rm0_wflags(insn, asi);
1144 /* cccc 000x xxxx xxxx xxxx xxxx xxxx 1xx1 xxxx */
1145 else if ((insn & 0x0e000090) == 0x00000090) {
1147 /* SWP : cccc 0001 0000 xxxx xxxx xxxx 1001 xxxx */
1148 /* SWPB : cccc 0001 0100 xxxx xxxx xxxx 1001 xxxx */
1149 /* ??? : cccc 0001 0x01 xxxx xxxx xxxx 1001 xxxx */
1150 /* ??? : cccc 0001 0x10 xxxx xxxx xxxx 1001 xxxx */
1151 /* ??? : cccc 0001 0x11 xxxx xxxx xxxx 1001 xxxx */
1152 /* STREX : cccc 0001 1000 xxxx xxxx xxxx 1001 xxxx */
1153 /* LDREX : cccc 0001 1001 xxxx xxxx xxxx 1001 xxxx */
1154 /* STREXD: cccc 0001 1010 xxxx xxxx xxxx 1001 xxxx */
1155 /* LDREXD: cccc 0001 1011 xxxx xxxx xxxx 1001 xxxx */
1156 /* STREXB: cccc 0001 1100 xxxx xxxx xxxx 1001 xxxx */
1157 /* LDREXB: cccc 0001 1101 xxxx xxxx xxxx 1001 xxxx */
1158 /* STREXH: cccc 0001 1110 xxxx xxxx xxxx 1001 xxxx */
1159 /* LDREXH: cccc 0001 1111 xxxx xxxx xxxx 1001 xxxx */
1161 /* LDRD : cccc 000x xxx0 xxxx xxxx xxxx 1101 xxxx */
1162 /* STRD : cccc 000x xxx0 xxxx xxxx xxxx 1111 xxxx */
1163 /* LDRH : cccc 000x xxx1 xxxx xxxx xxxx 1011 xxxx */
1164 /* STRH : cccc 000x xxx0 xxxx xxxx xxxx 1011 xxxx */
1165 /* LDRSB : cccc 000x xxx1 xxxx xxxx xxxx 1101 xxxx */
1166 /* LDRSH : cccc 000x xxx1 xxxx xxxx xxxx 1111 xxxx */
1167 if ((insn & 0x0f0000f0) == 0x01000090) {
1168 if ((insn & 0x0fb000f0) == 0x01000090) {
1170 return prep_emulate_rd12rn16rm0_wflags(insn,
1173 /* STREX/LDREX variants and unallocaed space */
1174 return INSN_REJECTED;
1177 } else if ((insn & 0x0e1000d0) == 0x00000d0) {
1179 if ((insn & 0x0000e000) == 0x0000e000)
1180 return INSN_REJECTED; /* Rd is LR or PC */
1181 if (is_writeback(insn) && is_r15(insn, 16))
1182 return INSN_REJECTED; /* Writeback to PC */
1185 insn |= 0x00002000; /* Rn = r0, Rd = r2 */
1186 if (!(insn & (1 << 22))) {
1187 /* Register index */
1189 insn |= 1; /* Rm = r1 */
1191 asi->insn[0] = insn;
1193 (insn & (1 << 5)) ? emulate_strd : emulate_ldrd;
1197 /* LDRH/STRH/LDRSB/LDRSH */
1198 if (is_r15(insn, 12))
1199 return INSN_REJECTED; /* Rd is PC */
1200 return prep_emulate_ldr_str(insn, asi);
1203 /* cccc 000x xxxx xxxx xxxx xxxx xxxx xxxx xxxx */
1206 * ALU op with S bit and Rd == 15 :
1207 * cccc 000x xxx1 xxxx 1111 xxxx xxxx xxxx
1209 if ((insn & 0x0e10f000) == 0x0010f000)
1210 return INSN_REJECTED;
1213 * "mov ip, sp" is the most common kprobe'd instruction by far.
1214 * Check and optimize for it explicitly.
1216 if (insn == 0xe1a0c00d) {
1217 asi->insn_handler = simulate_mov_ipsp;
1218 return INSN_GOOD_NO_SLOT;
1222 * Data processing: Immediate-shift / Register-shift
1223 * ALU op : cccc 000x xxxx xxxx xxxx xxxx xxxx xxxx
1224 * CPY : cccc 0001 1010 xxxx xxxx 0000 0000 xxxx
1225 * MOV : cccc 0001 101x xxxx xxxx xxxx xxxx xxxx
1226 * *S (bit 20) updates condition codes
1227 * ADC/SBC/RSC reads the C flag
1229 insn &= 0xfff00ff0; /* Rn = r0, Rd = r0 */
1230 insn |= 0x00000001; /* Rm = r1 */
1232 insn &= 0xfffff0ff; /* register shift */
1233 insn |= 0x00000200; /* Rs = r2 */
1235 asi->insn[0] = insn;
1237 if ((insn & 0x0f900000) == 0x01100000) {
1239 * TST : cccc 0001 0001 xxxx xxxx xxxx xxxx xxxx
1240 * TEQ : cccc 0001 0011 xxxx xxxx xxxx xxxx xxxx
1241 * CMP : cccc 0001 0101 xxxx xxxx xxxx xxxx xxxx
1242 * CMN : cccc 0001 0111 xxxx xxxx xxxx xxxx xxxx
1244 asi->insn_handler = emulate_alu_tests;
1246 /* ALU ops which write to Rd */
1247 asi->insn_handler = (insn & (1 << 20)) ? /* S-bit */
1248 emulate_alu_rwflags : emulate_alu_rflags;
1253 static enum kprobe_insn __kprobes
1254 space_cccc_001x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1257 * MSR : cccc 0011 0x10 xxxx xxxx xxxx xxxx xxxx
1258 * Undef : cccc 0011 0100 xxxx xxxx xxxx xxxx xxxx
1259 * ALU op with S bit and Rd == 15 :
1260 * cccc 001x xxx1 xxxx 1111 xxxx xxxx xxxx
1262 if ((insn & 0x0fb00000) == 0x03200000 || /* MSR */
1263 (insn & 0x0ff00000) == 0x03400000 || /* Undef */
1264 (insn & 0x0e10f000) == 0x0210f000) /* ALU s-bit, R15 */
1265 return INSN_REJECTED;
1268 * Data processing: 32-bit Immediate
1269 * ALU op : cccc 001x xxxx xxxx xxxx xxxx xxxx xxxx
1270 * MOV : cccc 0011 101x xxxx xxxx xxxx xxxx xxxx
1271 * *S (bit 20) updates condition codes
1272 * ADC/SBC/RSC reads the C flag
1274 insn &= 0xfff00fff; /* Rn = r0 and Rd = r0 */
1275 asi->insn[0] = insn;
1277 if ((insn & 0x0f900000) == 0x03100000) {
1279 * TST : cccc 0011 0001 xxxx xxxx xxxx xxxx xxxx
1280 * TEQ : cccc 0011 0011 xxxx xxxx xxxx xxxx xxxx
1281 * CMP : cccc 0011 0101 xxxx xxxx xxxx xxxx xxxx
1282 * CMN : cccc 0011 0111 xxxx xxxx xxxx xxxx xxxx
1284 asi->insn_handler = emulate_alu_tests_imm;
1286 /* ALU ops which write to Rd */
1287 asi->insn_handler = (insn & (1 << 20)) ? /* S-bit */
1288 emulate_alu_imm_rwflags : emulate_alu_imm_rflags;
1293 static enum kprobe_insn __kprobes
1294 space_cccc_0110__1(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1296 /* SEL : cccc 0110 1000 xxxx xxxx xxxx 1011 xxxx GE: !!! */
1297 if ((insn & 0x0ff000f0) == 0x068000b0) {
1298 if (is_r15(insn, 12))
1299 return INSN_REJECTED; /* Rd is PC */
1300 insn &= 0xfff00ff0; /* Rd = r0, Rn = r0 */
1301 insn |= 0x00000001; /* Rm = r1 */
1302 asi->insn[0] = insn;
1303 asi->insn_handler = emulate_sel;
1307 /* SSAT : cccc 0110 101x xxxx xxxx xxxx xx01 xxxx :Q */
1308 /* USAT : cccc 0110 111x xxxx xxxx xxxx xx01 xxxx :Q */
1309 /* SSAT16 : cccc 0110 1010 xxxx xxxx xxxx 0011 xxxx :Q */
1310 /* USAT16 : cccc 0110 1110 xxxx xxxx xxxx 0011 xxxx :Q */
1311 if ((insn & 0x0fa00030) == 0x06a00010 ||
1312 (insn & 0x0fb000f0) == 0x06a00030) {
1313 if (is_r15(insn, 12))
1314 return INSN_REJECTED; /* Rd is PC */
1315 insn &= 0xffff0ff0; /* Rd = r0, Rm = r0 */
1316 asi->insn[0] = insn;
1317 asi->insn_handler = emulate_sat;
1321 /* REV : cccc 0110 1011 xxxx xxxx xxxx 0011 xxxx */
1322 /* REV16 : cccc 0110 1011 xxxx xxxx xxxx 1011 xxxx */
1323 /* RBIT : cccc 0110 1111 xxxx xxxx xxxx 0011 xxxx */
1324 /* REVSH : cccc 0110 1111 xxxx xxxx xxxx 1011 xxxx */
1325 if ((insn & 0x0ff00070) == 0x06b00030 ||
1326 (insn & 0x0ff00070) == 0x06f00030)
1327 return prep_emulate_rd12rm0(insn, asi);
1329 /* ??? : cccc 0110 0000 xxxx xxxx xxxx xxx1 xxxx : */
1330 /* SADD16 : cccc 0110 0001 xxxx xxxx xxxx 0001 xxxx :GE */
1331 /* SADDSUBX : cccc 0110 0001 xxxx xxxx xxxx 0011 xxxx :GE */
1332 /* SSUBADDX : cccc 0110 0001 xxxx xxxx xxxx 0101 xxxx :GE */
1333 /* SSUB16 : cccc 0110 0001 xxxx xxxx xxxx 0111 xxxx :GE */
1334 /* SADD8 : cccc 0110 0001 xxxx xxxx xxxx 1001 xxxx :GE */
1335 /* ??? : cccc 0110 0001 xxxx xxxx xxxx 1011 xxxx : */
1336 /* ??? : cccc 0110 0001 xxxx xxxx xxxx 1101 xxxx : */
1337 /* SSUB8 : cccc 0110 0001 xxxx xxxx xxxx 1111 xxxx :GE */
1338 /* QADD16 : cccc 0110 0010 xxxx xxxx xxxx 0001 xxxx : */
1339 /* QADDSUBX : cccc 0110 0010 xxxx xxxx xxxx 0011 xxxx : */
1340 /* QSUBADDX : cccc 0110 0010 xxxx xxxx xxxx 0101 xxxx : */
1341 /* QSUB16 : cccc 0110 0010 xxxx xxxx xxxx 0111 xxxx : */
1342 /* QADD8 : cccc 0110 0010 xxxx xxxx xxxx 1001 xxxx : */
1343 /* ??? : cccc 0110 0010 xxxx xxxx xxxx 1011 xxxx : */
1344 /* ??? : cccc 0110 0010 xxxx xxxx xxxx 1101 xxxx : */
1345 /* QSUB8 : cccc 0110 0010 xxxx xxxx xxxx 1111 xxxx : */
1346 /* SHADD16 : cccc 0110 0011 xxxx xxxx xxxx 0001 xxxx : */
1347 /* SHADDSUBX : cccc 0110 0011 xxxx xxxx xxxx 0011 xxxx : */
1348 /* SHSUBADDX : cccc 0110 0011 xxxx xxxx xxxx 0101 xxxx : */
1349 /* SHSUB16 : cccc 0110 0011 xxxx xxxx xxxx 0111 xxxx : */
1350 /* SHADD8 : cccc 0110 0011 xxxx xxxx xxxx 1001 xxxx : */
1351 /* ??? : cccc 0110 0011 xxxx xxxx xxxx 1011 xxxx : */
1352 /* ??? : cccc 0110 0011 xxxx xxxx xxxx 1101 xxxx : */
1353 /* SHSUB8 : cccc 0110 0011 xxxx xxxx xxxx 1111 xxxx : */
1354 /* ??? : cccc 0110 0100 xxxx xxxx xxxx xxx1 xxxx : */
1355 /* UADD16 : cccc 0110 0101 xxxx xxxx xxxx 0001 xxxx :GE */
1356 /* UADDSUBX : cccc 0110 0101 xxxx xxxx xxxx 0011 xxxx :GE */
1357 /* USUBADDX : cccc 0110 0101 xxxx xxxx xxxx 0101 xxxx :GE */
1358 /* USUB16 : cccc 0110 0101 xxxx xxxx xxxx 0111 xxxx :GE */
1359 /* UADD8 : cccc 0110 0101 xxxx xxxx xxxx 1001 xxxx :GE */
1360 /* ??? : cccc 0110 0101 xxxx xxxx xxxx 1011 xxxx : */
1361 /* ??? : cccc 0110 0101 xxxx xxxx xxxx 1101 xxxx : */
1362 /* USUB8 : cccc 0110 0101 xxxx xxxx xxxx 1111 xxxx :GE */
1363 /* UQADD16 : cccc 0110 0110 xxxx xxxx xxxx 0001 xxxx : */
1364 /* UQADDSUBX : cccc 0110 0110 xxxx xxxx xxxx 0011 xxxx : */
1365 /* UQSUBADDX : cccc 0110 0110 xxxx xxxx xxxx 0101 xxxx : */
1366 /* UQSUB16 : cccc 0110 0110 xxxx xxxx xxxx 0111 xxxx : */
1367 /* UQADD8 : cccc 0110 0110 xxxx xxxx xxxx 1001 xxxx : */
1368 /* ??? : cccc 0110 0110 xxxx xxxx xxxx 1011 xxxx : */
1369 /* ??? : cccc 0110 0110 xxxx xxxx xxxx 1101 xxxx : */
1370 /* UQSUB8 : cccc 0110 0110 xxxx xxxx xxxx 1111 xxxx : */
1371 /* UHADD16 : cccc 0110 0111 xxxx xxxx xxxx 0001 xxxx : */
1372 /* UHADDSUBX : cccc 0110 0111 xxxx xxxx xxxx 0011 xxxx : */
1373 /* UHSUBADDX : cccc 0110 0111 xxxx xxxx xxxx 0101 xxxx : */
1374 /* UHSUB16 : cccc 0110 0111 xxxx xxxx xxxx 0111 xxxx : */
1375 /* UHADD8 : cccc 0110 0111 xxxx xxxx xxxx 1001 xxxx : */
1376 /* ??? : cccc 0110 0111 xxxx xxxx xxxx 1011 xxxx : */
1377 /* ??? : cccc 0110 0111 xxxx xxxx xxxx 1101 xxxx : */
1378 /* UHSUB8 : cccc 0110 0111 xxxx xxxx xxxx 1111 xxxx : */
1379 if ((insn & 0x0f800010) == 0x06000010) {
1380 if ((insn & 0x00300000) == 0x00000000 ||
1381 (insn & 0x000000e0) == 0x000000a0 ||
1382 (insn & 0x000000e0) == 0x000000c0)
1383 return INSN_REJECTED; /* Unallocated space */
1384 return prep_emulate_rd12rn16rm0_wflags(insn, asi);
1387 /* PKHBT : cccc 0110 1000 xxxx xxxx xxxx x001 xxxx : */
1388 /* PKHTB : cccc 0110 1000 xxxx xxxx xxxx x101 xxxx : */
1389 if ((insn & 0x0ff00030) == 0x06800010)
1390 return prep_emulate_rd12rn16rm0_wflags(insn, asi);
1392 /* SXTAB16 : cccc 0110 1000 xxxx xxxx xxxx 0111 xxxx : */
1393 /* SXTB16 : cccc 0110 1000 1111 xxxx xxxx 0111 xxxx : */
1394 /* ??? : cccc 0110 1001 xxxx xxxx xxxx 0111 xxxx : */
1395 /* SXTAB : cccc 0110 1010 xxxx xxxx xxxx 0111 xxxx : */
1396 /* SXTB : cccc 0110 1010 1111 xxxx xxxx 0111 xxxx : */
1397 /* SXTAH : cccc 0110 1011 xxxx xxxx xxxx 0111 xxxx : */
1398 /* SXTH : cccc 0110 1011 1111 xxxx xxxx 0111 xxxx : */
1399 /* UXTAB16 : cccc 0110 1100 xxxx xxxx xxxx 0111 xxxx : */
1400 /* UXTB16 : cccc 0110 1100 1111 xxxx xxxx 0111 xxxx : */
1401 /* ??? : cccc 0110 1101 xxxx xxxx xxxx 0111 xxxx : */
1402 /* UXTAB : cccc 0110 1110 xxxx xxxx xxxx 0111 xxxx : */
1403 /* UXTB : cccc 0110 1110 1111 xxxx xxxx 0111 xxxx : */
1404 /* UXTAH : cccc 0110 1111 xxxx xxxx xxxx 0111 xxxx : */
1405 /* UXTH : cccc 0110 1111 1111 xxxx xxxx 0111 xxxx : */
1406 if ((insn & 0x0f8000f0) == 0x06800070) {
1407 if ((insn & 0x00300000) == 0x00100000)
1408 return INSN_REJECTED; /* Unallocated space */
1410 if ((insn & 0x000f0000) == 0x000f0000) {
1411 return prep_emulate_rd12rm0(insn, asi);
1413 return prep_emulate_rd12rn16rm0_wflags(insn, asi);
1417 /* Other instruction encodings aren't yet defined */
1418 return INSN_REJECTED;
1421 static enum kprobe_insn __kprobes
1422 space_cccc_0111__1(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1424 /* Undef : cccc 0111 1111 xxxx xxxx xxxx 1111 xxxx */
1425 if ((insn & 0x0ff000f0) == 0x03f000f0)
1426 return INSN_REJECTED;
1428 /* USADA8 : cccc 0111 1000 xxxx xxxx xxxx 0001 xxxx */
1429 /* USAD8 : cccc 0111 1000 xxxx 1111 xxxx 0001 xxxx */
1430 if ((insn & 0x0ff000f0) == 0x07800010)
1431 return prep_emulate_rd16rn12rs8rm0_wflags(insn, asi);
1433 /* SMLALD : cccc 0111 0100 xxxx xxxx xxxx 00x1 xxxx */
1434 /* SMLSLD : cccc 0111 0100 xxxx xxxx xxxx 01x1 xxxx */
1435 if ((insn & 0x0ff00090) == 0x07400010)
1436 return prep_emulate_rdhi16rdlo12rs8rm0_wflags(insn, asi);
1438 /* SMLAD : cccc 0111 0000 xxxx xxxx xxxx 00x1 xxxx :Q */
1439 /* SMUAD : cccc 0111 0000 xxxx 1111 xxxx 00x1 xxxx :Q */
1440 /* SMLSD : cccc 0111 0000 xxxx xxxx xxxx 01x1 xxxx :Q */
1441 /* SMUSD : cccc 0111 0000 xxxx 1111 xxxx 01x1 xxxx : */
1442 /* SMMLA : cccc 0111 0101 xxxx xxxx xxxx 00x1 xxxx : */
1443 /* SMMUL : cccc 0111 0101 xxxx 1111 xxxx 00x1 xxxx : */
1444 if ((insn & 0x0ff00090) == 0x07000010 ||
1445 (insn & 0x0ff000d0) == 0x07500010) {
1447 if ((insn & 0x0000f000) == 0x0000f000) {
1448 return prep_emulate_rd16rs8rm0_wflags(insn, asi);
1450 return prep_emulate_rd16rn12rs8rm0_wflags(insn, asi);
1454 /* SMMLS : cccc 0111 0101 xxxx xxxx xxxx 11x1 xxxx : */
1455 if ((insn & 0x0ff000d0) == 0x075000d0)
1456 return prep_emulate_rd16rn12rs8rm0_wflags(insn, asi);
1458 return INSN_REJECTED;
1461 static enum kprobe_insn __kprobes
1462 space_cccc_01xx(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1464 /* LDR : cccc 01xx x0x1 xxxx xxxx xxxx xxxx xxxx */
1465 /* LDRB : cccc 01xx x1x1 xxxx xxxx xxxx xxxx xxxx */
1466 /* LDRBT : cccc 01x0 x111 xxxx xxxx xxxx xxxx xxxx */
1467 /* LDRT : cccc 01x0 x011 xxxx xxxx xxxx xxxx xxxx */
1468 /* STR : cccc 01xx x0x0 xxxx xxxx xxxx xxxx xxxx */
1469 /* STRB : cccc 01xx x1x0 xxxx xxxx xxxx xxxx xxxx */
1470 /* STRBT : cccc 01x0 x110 xxxx xxxx xxxx xxxx xxxx */
1471 /* STRT : cccc 01x0 x010 xxxx xxxx xxxx xxxx xxxx */
1473 if ((insn & 0x00500000) == 0x00500000 && is_r15(insn, 12))
1474 return INSN_REJECTED; /* LDRB into PC */
1476 return prep_emulate_ldr_str(insn, asi);
1479 static enum kprobe_insn __kprobes
1480 space_cccc_100x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1482 /* LDM(2) : cccc 100x x101 xxxx 0xxx xxxx xxxx xxxx */
1483 /* LDM(3) : cccc 100x x1x1 xxxx 1xxx xxxx xxxx xxxx */
1484 if ((insn & 0x0e708000) == 0x85000000 ||
1485 (insn & 0x0e508000) == 0x85010000)
1486 return INSN_REJECTED;
1488 /* LDM(1) : cccc 100x x0x1 xxxx xxxx xxxx xxxx xxxx */
1489 /* STM(1) : cccc 100x x0x0 xxxx xxxx xxxx xxxx xxxx */
1490 asi->insn_handler = ((insn & 0x108000) == 0x008000) ? /* STM & R15 */
1491 simulate_stm1_pc : simulate_ldm1stm1;
1492 return INSN_GOOD_NO_SLOT;
1495 static enum kprobe_insn __kprobes
1496 space_cccc_101x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1498 /* B : cccc 1010 xxxx xxxx xxxx xxxx xxxx xxxx */
1499 /* BL : cccc 1011 xxxx xxxx xxxx xxxx xxxx xxxx */
1500 asi->insn_handler = simulate_bbl;
1501 return INSN_GOOD_NO_SLOT;
1504 static enum kprobe_insn __kprobes
1505 space_cccc_1100_010x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1507 /* MCRR : cccc 1100 0100 xxxx xxxx xxxx xxxx xxxx : (Rd!=Rn) */
1508 /* MRRC : cccc 1100 0101 xxxx xxxx xxxx xxxx xxxx : (Rd!=Rn) */
1509 if (is_r15(insn, 16) || is_r15(insn, 12))
1510 return INSN_REJECTED; /* Rn or Rd is PC */
1513 insn |= 0x00001000; /* Rn = r0, Rd = r1 */
1514 asi->insn[0] = insn;
1515 asi->insn_handler = (insn & (1 << 20)) ? emulate_mrrc : emulate_mcrr;
1519 static enum kprobe_insn __kprobes
1520 space_cccc_110x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1522 /* LDC : cccc 110x xxx1 xxxx xxxx xxxx xxxx xxxx */
1523 /* STC : cccc 110x xxx0 xxxx xxxx xxxx xxxx xxxx */
1524 insn &= 0xfff0ffff; /* Rn = r0 */
1525 asi->insn[0] = insn;
1526 asi->insn_handler = emulate_ldcstc;
1530 static enum kprobe_insn __kprobes
1531 space_cccc_111x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1533 /* BKPT : 1110 0001 0010 xxxx xxxx xxxx 0111 xxxx */
1534 /* SWI : cccc 1111 xxxx xxxx xxxx xxxx xxxx xxxx */
1535 if ((insn & 0xfff000f0) == 0xe1200070 ||
1536 (insn & 0x0f000000) == 0x0f000000)
1537 return INSN_REJECTED;
1539 /* CDP : cccc 1110 xxxx xxxx xxxx xxxx xxx0 xxxx */
1540 if ((insn & 0x0f000010) == 0x0e000000) {
1541 asi->insn[0] = insn;
1542 asi->insn_handler = emulate_none;
1546 /* MCR : cccc 1110 xxx0 xxxx xxxx xxxx xxx1 xxxx */
1547 /* MRC : cccc 1110 xxx1 xxxx xxxx xxxx xxx1 xxxx */
1548 insn &= 0xffff0fff; /* Rd = r0 */
1549 asi->insn[0] = insn;
1550 asi->insn_handler = (insn & (1 << 20)) ? emulate_rd12 : emulate_ird12;
1554 static unsigned long __kprobes __check_eq(unsigned long cpsr)
1556 return cpsr & PSR_Z_BIT;
1559 static unsigned long __kprobes __check_ne(unsigned long cpsr)
1561 return (~cpsr) & PSR_Z_BIT;
1564 static unsigned long __kprobes __check_cs(unsigned long cpsr)
1566 return cpsr & PSR_C_BIT;
1569 static unsigned long __kprobes __check_cc(unsigned long cpsr)
1571 return (~cpsr) & PSR_C_BIT;
1574 static unsigned long __kprobes __check_mi(unsigned long cpsr)
1576 return cpsr & PSR_N_BIT;
1579 static unsigned long __kprobes __check_pl(unsigned long cpsr)
1581 return (~cpsr) & PSR_N_BIT;
1584 static unsigned long __kprobes __check_vs(unsigned long cpsr)
1586 return cpsr & PSR_V_BIT;
1589 static unsigned long __kprobes __check_vc(unsigned long cpsr)
1591 return (~cpsr) & PSR_V_BIT;
1594 static unsigned long __kprobes __check_hi(unsigned long cpsr)
1596 cpsr &= ~(cpsr >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */
1597 return cpsr & PSR_C_BIT;
1600 static unsigned long __kprobes __check_ls(unsigned long cpsr)
1602 cpsr &= ~(cpsr >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */
1603 return (~cpsr) & PSR_C_BIT;
1606 static unsigned long __kprobes __check_ge(unsigned long cpsr)
1608 cpsr ^= (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
1609 return (~cpsr) & PSR_N_BIT;
1612 static unsigned long __kprobes __check_lt(unsigned long cpsr)
1614 cpsr ^= (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
1615 return cpsr & PSR_N_BIT;
1618 static unsigned long __kprobes __check_gt(unsigned long cpsr)
1620 unsigned long temp = cpsr ^ (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
1621 temp |= (cpsr << 1); /* PSR_N_BIT |= PSR_Z_BIT */
1622 return (~temp) & PSR_N_BIT;
1625 static unsigned long __kprobes __check_le(unsigned long cpsr)
1627 unsigned long temp = cpsr ^ (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
1628 temp |= (cpsr << 1); /* PSR_N_BIT |= PSR_Z_BIT */
1629 return temp & PSR_N_BIT;
1632 static unsigned long __kprobes __check_al(unsigned long cpsr)
1637 static kprobe_check_cc * const condition_checks[16] = {
1638 &__check_eq, &__check_ne, &__check_cs, &__check_cc,
1639 &__check_mi, &__check_pl, &__check_vs, &__check_vc,
1640 &__check_hi, &__check_ls, &__check_ge, &__check_lt,
1641 &__check_gt, &__check_le, &__check_al, &__check_al
1645 * INSN_REJECTED If instruction is one not allowed to kprobe,
1646 * INSN_GOOD If instruction is supported and uses instruction slot,
1647 * INSN_GOOD_NO_SLOT If instruction is supported but doesn't use its slot.
1649 * For instructions we don't want to kprobe (INSN_REJECTED return result):
1650 * These are generally ones that modify the processor state making
1651 * them "hard" to simulate such as switches processor modes or
1652 * make accesses in alternate modes. Any of these could be simulated
1653 * if the work was put into it, but low return considering they
1654 * should also be very rare.
1656 enum kprobe_insn __kprobes
1657 arm_kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1659 asi->insn_check_cc = condition_checks[insn>>28];
1660 asi->insn[1] = KPROBE_RETURN_INSTRUCTION;
1662 if ((insn & 0xf0000000) == 0xf0000000) {
1664 return space_1111(insn, asi);
1666 } else if ((insn & 0x0e000000) == 0x00000000) {
1668 return space_cccc_000x(insn, asi);
1670 } else if ((insn & 0x0e000000) == 0x02000000) {
1672 return space_cccc_001x(insn, asi);
1674 } else if ((insn & 0x0f000010) == 0x06000010) {
1676 return space_cccc_0110__1(insn, asi);
1678 } else if ((insn & 0x0f000010) == 0x07000010) {
1680 return space_cccc_0111__1(insn, asi);
1682 } else if ((insn & 0x0c000000) == 0x04000000) {
1684 return space_cccc_01xx(insn, asi);
1686 } else if ((insn & 0x0e000000) == 0x08000000) {
1688 return space_cccc_100x(insn, asi);
1690 } else if ((insn & 0x0e000000) == 0x0a000000) {
1692 return space_cccc_101x(insn, asi);
1694 } else if ((insn & 0x0fe00000) == 0x0c400000) {
1696 return space_cccc_1100_010x(insn, asi);
1698 } else if ((insn & 0x0e000000) == 0x0c000000) {
1700 return space_cccc_110x(insn, asi);
1704 return space_cccc_111x(insn, asi);
1707 void __init arm_kprobe_decode_init(void)
1709 find_str_pc_offset();
1714 * All ARM instructions listed below.
1716 * Instructions and their general purpose registers are given.
1717 * If a particular register may not use R15, it is prefixed with a "!".
1718 * If marked with a "*" means the value returned by reading R15
1719 * is implementation defined.
1721 * ADC/ADD/AND/BIC/CMN/CMP/EOR/MOV/MVN/ORR/RSB/RSC/SBC/SUB/TEQ
1722 * TST: Rd, Rn, Rm, !Rs
1725 * BX: Rm (R15 legal, but discouraged)
1729 * LDC/2,STC/2 immediate offset & unindex: Rn
1730 * LDC/2,STC/2 immediate pre/post-indexed: !Rn
1731 * LDM(1/3): !Rn, register_list
1732 * LDM(2): !Rn, !register_list
1733 * LDR,STR,PLD immediate offset: Rd, Rn
1734 * LDR,STR,PLD register offset: Rd, Rn, !Rm
1735 * LDR,STR,PLD scaled register offset: Rd, !Rn, !Rm
1736 * LDR,STR immediate pre/post-indexed: Rd, !Rn
1737 * LDR,STR register pre/post-indexed: Rd, !Rn, !Rm
1738 * LDR,STR scaled register pre/post-indexed: Rd, !Rn, !Rm
1739 * LDRB,STRB immediate offset: !Rd, Rn
1740 * LDRB,STRB register offset: !Rd, Rn, !Rm
1741 * LDRB,STRB scaled register offset: !Rd, !Rn, !Rm
1742 * LDRB,STRB immediate pre/post-indexed: !Rd, !Rn
1743 * LDRB,STRB register pre/post-indexed: !Rd, !Rn, !Rm
1744 * LDRB,STRB scaled register pre/post-indexed: !Rd, !Rn, !Rm
1745 * LDRT,LDRBT,STRBT immediate pre/post-indexed: !Rd, !Rn
1746 * LDRT,LDRBT,STRBT register pre/post-indexed: !Rd, !Rn, !Rm
1747 * LDRT,LDRBT,STRBT scaled register pre/post-indexed: !Rd, !Rn, !Rm
1748 * LDRH/SH/SB/D,STRH/SH/SB/D immediate offset: !Rd, Rn
1749 * LDRH/SH/SB/D,STRH/SH/SB/D register offset: !Rd, Rn, !Rm
1750 * LDRH/SH/SB/D,STRH/SH/SB/D immediate pre/post-indexed: !Rd, !Rn
1751 * LDRH/SH/SB/D,STRH/SH/SB/D register pre/post-indexed: !Rd, !Rn, !Rm
1754 * MCRR/2,MRRC/2: !Rd, !Rn
1755 * MLA: !Rd, !Rn, !Rm, !Rs
1757 * MRC/2: !Rd (if Rd==15, only changes cond codes, not the register)
1759 * MUL: !Rd, !Rm, !Rs
1760 * PKH{BT,TB}: !Rd, !Rn, !Rm
1761 * QDADD,[U]QADD/16/8/SUBX: !Rd, !Rm, !Rn
1762 * QDSUB,[U]QSUB/16/8/ADDX: !Rd, !Rm, !Rn
1763 * REV/16/SH: !Rd, !Rm
1765 * {S,U}[H]ADD{16,8,SUBX},{S,U}[H]SUB{16,8,ADDX}: !Rd, !Rn, !Rm
1766 * SEL: !Rd, !Rn, !Rm
1767 * SMLA<x><y>,SMLA{D,W<y>},SMLSD,SMML{A,S}: !Rd, !Rn, !Rm, !Rs
1768 * SMLAL<x><y>,SMLA{D,LD},SMLSLD,SMMULL,SMULW<y>: !RdHi, !RdLo, !Rm, !Rs
1769 * SMMUL,SMUAD,SMUL<x><y>,SMUSD: !Rd, !Rm, !Rs
1771 * STM(1/2): !Rn, register_list* (R15 in reg list not recommended)
1772 * STRT immediate pre/post-indexed: Rd*, !Rn
1773 * STRT register pre/post-indexed: Rd*, !Rn, !Rm
1774 * STRT scaled register pre/post-indexed: Rd*, !Rn, !Rm
1775 * STREX: !Rd, !Rn, !Rm
1776 * SWP/B: !Rd, !Rn, !Rm
1777 * {S,U}XTA{B,B16,H}: !Rd, !Rn, !Rm
1778 * {S,U}XT{B,B16,H}: !Rd, !Rm
1779 * UM{AA,LA,UL}L: !RdHi, !RdLo, !Rm, !Rs
1780 * USA{D8,A8,T,T16}: !Rd, !Rm, !Rs
1782 * May transfer control by writing R15 (possible mode changes or alternate
1783 * mode accesses marked by "*"):
1784 * ALU op (* with s-bit), B, BL, BKPT, BLX(1/2), BX, BXJ, CPS*, CPY,
1785 * LDM(1), LDM(2/3)*, LDR, MOV, RFE*, SWI*
1787 * Instructions that do not take general registers, nor transfer control:
1788 * CDP/2, SETEND, SRS*