2 * linux/arch/arm/kernel/head.S
4 * Copyright (C) 1994-2002 Russell King
5 * Copyright (c) 2003 ARM Limited
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * Kernel startup code for all 32-bit CPUs
14 #include <linux/config.h>
15 #include <linux/linkage.h>
16 #include <linux/init.h>
18 #include <asm/assembler.h>
19 #include <asm/domain.h>
20 #include <asm/procinfo.h>
21 #include <asm/ptrace.h>
22 #include <asm/asm-offsets.h>
23 #include <asm/memory.h>
24 #include <asm/thread_info.h>
25 #include <asm/system.h>
27 #define PROCINFO_MMUFLAGS 8
28 #define PROCINFO_INITFUNC 12
30 #define MACHINFO_TYPE 0
31 #define MACHINFO_PHYSRAM 4
32 #define MACHINFO_PHYSIO 8
33 #define MACHINFO_PGOFFIO 12
34 #define MACHINFO_NAME 16
36 #define KERNEL_RAM_ADDR (PAGE_OFFSET + TEXT_OFFSET)
39 * swapper_pg_dir is the virtual address of the initial page table.
40 * We place the page tables 16K below KERNEL_RAM_ADDR. Therefore, we must
41 * make sure that KERNEL_RAM_ADDR is correctly set. Currently, we expect
42 * the least significant 16 bits to be 0x8000, but we could probably
43 * relax this restriction to KERNEL_RAM_ADDR >= PAGE_OFFSET + 0x4000.
45 #if (KERNEL_RAM_ADDR & 0xffff) != 0x8000
46 #error KERNEL_RAM_ADDR must start at 0xXXXX8000
50 .equ swapper_pg_dir, KERNEL_RAM_ADDR - 0x4000
53 ldr \rd, =(__virt_to_phys(KERNEL_RAM_ADDR - 0x4000))
56 #ifdef CONFIG_XIP_KERNEL
57 #define TEXTADDR XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR)
59 #define TEXTADDR KERNEL_RAM_ADDR
63 * Kernel startup entry point.
64 * ---------------------------
66 * This is normally called from the decompressor code. The requirements
67 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
70 * This code is mostly position independent, so if you link the kernel at
71 * 0xc0008000, you call this at __pa(0xc0008000).
73 * See linux/arch/arm/tools/mach-types for the complete list of machine
76 * We're trying to keep crap to a minimum; DO NOT add any machine specific
77 * crap here - that's what the boot loader (or in extreme, well justified
78 * circumstances, zImage) is for.
81 .type stext, %function
83 msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC @ ensure svc mode
85 mrc p15, 0, r9, c0, c0 @ get processor id
86 bl __lookup_processor_type @ r5=procinfo r9=cpuid
87 movs r10, r5 @ invalid processor (r5=0)?
88 beq __error_p @ yes, error 'p'
89 bl __lookup_machine_type @ r5=machinfo
90 movs r8, r5 @ invalid machine (r5=0)?
91 beq __error_a @ yes, error 'a'
92 bl __create_page_tables
95 * The following calls CPU specific code in a position independent
96 * manner. See arch/arm/mm/proc-*.S for details. r10 = base of
97 * xxx_proc_info structure selected by __lookup_machine_type
98 * above. On return, the CPU will be ready for the MMU to be
99 * turned on, and r0 will hold the CPU control register value.
101 ldr r13, __switch_data @ address to jump to after
102 @ mmu has been enabled
103 adr lr, __enable_mmu @ return (PIC) address
104 add pc, r10, #PROCINFO_INITFUNC
106 #if defined(CONFIG_SMP)
107 .type secondary_startup, #function
108 ENTRY(secondary_startup)
110 * Common entry point for secondary CPUs.
112 * Ensure that we're in SVC mode, and IRQs are disabled. Lookup
113 * the processor type - there is no need to check the machine type
114 * as it has already been validated by the primary processor.
116 msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC
117 mrc p15, 0, r9, c0, c0 @ get processor id
118 bl __lookup_processor_type
119 movs r10, r5 @ invalid processor?
120 moveq r0, #'p' @ yes, error 'p'
124 * Use the page tables supplied from __cpu_up.
126 adr r4, __secondary_data
127 ldmia r4, {r5, r6, r13} @ address to jump to after
128 sub r4, r4, r5 @ mmu has been enabled
129 ldr r4, [r6, r4] @ get secondary_data.pgdir
130 adr lr, __enable_mmu @ return address
131 add pc, r10, #12 @ initialise processor
132 @ (return control reg)
135 * r6 = &secondary_data
137 ENTRY(__secondary_switched)
138 ldr sp, [r6, #4] @ get secondary_data.stack
140 b secondary_start_kernel
142 .type __secondary_data, %object
146 .long __secondary_switched
147 #endif /* defined(CONFIG_SMP) */
152 * Setup common bits before finally enabling the MMU. Essentially
153 * this is just loading the page table pointer and domain access
156 .type __enable_mmu, %function
158 #ifdef CONFIG_ALIGNMENT_TRAP
163 #ifdef CONFIG_CPU_DCACHE_DISABLE
166 #ifdef CONFIG_CPU_BPREDICT_DISABLE
169 #ifdef CONFIG_CPU_ICACHE_DISABLE
172 mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
173 domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
174 domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
175 domain_val(DOMAIN_IO, DOMAIN_CLIENT))
176 mcr p15, 0, r5, c3, c0, 0 @ load domain access register
177 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
181 * Enable the MMU. This completely changes the structure of the visible
182 * memory space. You will not be able to trace execution through this.
183 * If you have an enquiry about this, *please* check the linux-arm-kernel
184 * mailing list archives BEFORE sending another post to the list.
186 * r0 = cp#15 control register
187 * r13 = *virtual* address to jump to upon completion
189 * other registers depend on the function called upon completion
192 .type __turn_mmu_on, %function
195 mcr p15, 0, r0, c1, c0, 0 @ write control reg
196 mrc p15, 0, r3, c0, c0, 0 @ read id reg
204 * Setup the initial page tables. We only setup the barest
205 * amount which are required to get the kernel running, which
206 * generally means mapping in the kernel code.
213 * r0, r3, r6, r7 corrupted
214 * r4 = physical page table address
216 .type __create_page_tables, %function
217 __create_page_tables:
218 pgtbl r4 @ page table address
221 * Clear the 16K level 1 swapper page table
233 ldr r7, [r10, #PROCINFO_MMUFLAGS] @ mmuflags
236 * Create identity mapping for first MB of kernel to
237 * cater for the MMU enable. This identity mapping
238 * will be removed by paging_init(). We use our current program
239 * counter to determine corresponding section base address.
241 mov r6, pc, lsr #20 @ start of kernel section
242 orr r3, r7, r6, lsl #20 @ flags + kernel base
243 str r3, [r4, r6, lsl #2] @ identity mapping
246 * Now setup the pagetables for our kernel direct
247 * mapped region. We round TEXTADDR down to the
248 * nearest megabyte boundary. It is assumed that
249 * the kernel fits within 4 contigous 1MB sections.
251 add r0, r4, #(TEXTADDR & 0xff000000) >> 18 @ start of kernel
252 str r3, [r0, #(TEXTADDR & 0x00f00000) >> 18]!
254 str r3, [r0, #4]! @ KERNEL + 1MB
256 str r3, [r0, #4]! @ KERNEL + 2MB
258 str r3, [r0, #4] @ KERNEL + 3MB
261 * Then map first 1MB of ram in case it contains our boot params.
263 add r0, r4, #PAGE_OFFSET >> 18
264 orr r6, r7, #PHYS_OFFSET
267 #ifdef CONFIG_XIP_KERNEL
269 * Map some ram to cover our .data and .bss areas.
270 * Mapping 3MB should be plenty.
272 sub r3, r4, #PHYS_OFFSET
274 add r0, r0, r3, lsl #2
275 add r6, r6, r3, lsl #20
277 add r6, r6, #(1 << 20)
279 add r6, r6, #(1 << 20)
283 #ifdef CONFIG_DEBUG_LL
284 bic r7, r7, #0x0c @ turn off cacheable
285 @ and bufferable bits
287 * Map in IO space for serial debugging.
288 * This allows debug messages to be output
289 * via a serial console before paging_init.
291 ldr r3, [r8, #MACHINFO_PGOFFIO]
293 rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long)
294 cmp r3, #0x0800 @ limit to 512MB
297 ldr r3, [r8, #MACHINFO_PHYSIO]
303 #if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS)
305 * If we're using the NetWinder or CATS, we also need to map
306 * in the 16550-type serial port for the debug messages
308 add r0, r4, #0xff000000 >> 18
309 orr r3, r7, #0x7c000000
312 #ifdef CONFIG_ARCH_RPC
314 * Map in screen at 0x02000000 & SCREEN2_BASE
315 * Similar reasons here - for debug. This is
316 * only for Acorn RiscPC architectures.
318 add r0, r4, #0x02000000 >> 18
319 orr r3, r7, #0x02000000
321 add r0, r4, #0xd8000000 >> 18
328 #include "head-common.S"