2 * linux/arch/arm/kernel/head.S
4 * Copyright (C) 1994-2002 Russell King
5 * Copyright (c) 2003 ARM Limited
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * Kernel startup code for all 32-bit CPUs
14 #include <linux/linkage.h>
15 #include <linux/init.h>
17 #include <asm/assembler.h>
19 #include <asm/domain.h>
20 #include <asm/ptrace.h>
21 #include <asm/asm-offsets.h>
22 #include <asm/memory.h>
23 #include <asm/thread_info.h>
24 #include <asm/pgtable.h>
26 #ifdef CONFIG_DEBUG_LL
27 #include <mach/debug-macro.S>
31 * swapper_pg_dir is the virtual address of the initial page table.
32 * We place the page tables 16K below KERNEL_RAM_VADDR. Therefore, we must
33 * make sure that KERNEL_RAM_VADDR is correctly set. Currently, we expect
34 * the least significant 16 bits to be 0x8000, but we could probably
35 * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000.
37 #define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET)
38 #if (KERNEL_RAM_VADDR & 0xffff) != 0x8000
39 #error KERNEL_RAM_VADDR must start at 0xXXXX8000
42 #ifdef CONFIG_ARM_LPAE
43 /* LPAE requires an additional page for the PGD */
44 #define PG_DIR_SIZE 0x5000
47 #define PG_DIR_SIZE 0x4000
52 .equ swapper_pg_dir, KERNEL_RAM_VADDR - PG_DIR_SIZE
54 .macro pgtbl, rd, phys
55 add \rd, \phys, #TEXT_OFFSET - PG_DIR_SIZE
59 * Kernel startup entry point.
60 * ---------------------------
62 * This is normally called from the decompressor code. The requirements
63 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
64 * r1 = machine nr, r2 = atags or dtb pointer.
66 * This code is mostly position independent, so if you link the kernel at
67 * 0xc0008000, you call this at __pa(0xc0008000).
69 * See linux/arch/arm/tools/mach-types for the complete list of machine
72 * We're trying to keep crap to a minimum; DO NOT add any machine specific
73 * crap here - that's what the boot loader (or in extreme, well justified
74 * circumstances, zImage) is for.
81 THUMB( adr r9, BSYM(1f) ) @ Kernel is always entered in ARM.
82 THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
83 THUMB( .thumb ) @ switch to Thumb now.
86 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
88 mrc p15, 0, r9, c0, c0 @ get processor id
89 bl __lookup_processor_type @ r5=procinfo r9=cpuid
90 movs r10, r5 @ invalid processor (r5=0)?
91 THUMB( it eq ) @ force fixup-able long branch encoding
92 beq __error_p @ yes, error 'p'
94 #ifdef CONFIG_ARM_LPAE
95 mrc p15, 0, r3, c0, c1, 4 @ read ID_MMFR0
96 and r3, r3, #0xf @ extract VMSA support
97 cmp r3, #5 @ long-descriptor translation table format?
98 THUMB( it lo ) @ force fixup-able long branch encoding
99 blo __error_p @ only classic page table format
102 #ifndef CONFIG_XIP_KERNEL
105 sub r4, r3, r4 @ (PHYS_OFFSET - PAGE_OFFSET)
106 add r8, r8, r4 @ PHYS_OFFSET
108 ldr r8, =PHYS_OFFSET @ always constant in this case
112 * r1 = machine no, r2 = atags or dtb,
113 * r8 = phys_offset, r9 = cpuid, r10 = procinfo
116 #ifdef CONFIG_SMP_ON_UP
119 #ifdef CONFIG_ARM_PATCH_PHYS_VIRT
122 bl __create_page_tables
125 * The following calls CPU specific code in a position independent
126 * manner. See arch/arm/mm/proc-*.S for details. r10 = base of
127 * xxx_proc_info structure selected by __lookup_processor_type
128 * above. On return, the CPU will be ready for the MMU to be
129 * turned on, and r0 will hold the CPU control register value.
131 ldr r13, =__mmap_switched @ address to jump to after
132 @ mmu has been enabled
133 adr lr, BSYM(1f) @ return (PIC) address
134 mov r8, r4 @ set TTBR1 to swapper_pg_dir
135 ARM( add pc, r10, #PROCINFO_INITFUNC )
136 THUMB( add r12, r10, #PROCINFO_INITFUNC )
141 #ifndef CONFIG_XIP_KERNEL
147 * Setup the initial page tables. We only setup the barest
148 * amount which are required to get the kernel running, which
149 * generally means mapping in the kernel code.
151 * r8 = phys_offset, r9 = cpuid, r10 = procinfo
154 * r0, r3, r5-r7 corrupted
155 * r4 = physical page table address
157 __create_page_tables:
158 pgtbl r4, r8 @ page table address
161 * Clear the swapper page table
165 add r6, r0, #PG_DIR_SIZE
173 #ifdef CONFIG_ARM_LPAE
175 * Build the PGD table (first level) to point to the PMD table. A PGD
176 * entry is 64-bit wide.
179 add r3, r4, #0x1000 @ first PMD table address
180 orr r3, r3, #3 @ PGD block type
181 mov r6, #4 @ PTRS_PER_PGD
182 mov r7, #1 << (55 - 32) @ L_PGD_SWAPPER
183 1: str r3, [r0], #4 @ set bottom PGD entry bits
184 str r7, [r0], #4 @ set top PGD entry bits
185 add r3, r3, #0x1000 @ next PMD table
189 add r4, r4, #0x1000 @ point to the PMD tables
192 ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags
195 * Create identity mapping to cater for __enable_mmu.
196 * This identity mapping will be removed by paging_init().
198 adr r0, __turn_mmu_on_loc
199 ldmia r0, {r3, r5, r6}
200 sub r0, r0, r3 @ virt->phys offset
201 add r5, r5, r0 @ phys __turn_mmu_on
202 add r6, r6, r0 @ phys __turn_mmu_on_end
203 mov r5, r5, lsr #SECTION_SHIFT
204 mov r6, r6, lsr #SECTION_SHIFT
206 1: orr r3, r7, r5, lsl #SECTION_SHIFT @ flags + kernel base
207 str r3, [r4, r5, lsl #PMD_ORDER] @ identity mapping
209 addlo r5, r5, #1 @ next section
213 * Map our RAM from the start to the end of the kernel .bss section.
215 add r0, r4, #PAGE_OFFSET >> (SECTION_SHIFT - PMD_ORDER)
218 add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
219 1: str r3, [r0], #1 << PMD_ORDER
220 add r3, r3, #1 << SECTION_SHIFT
224 #ifdef CONFIG_XIP_KERNEL
226 * Map the kernel image separately as it is not located in RAM.
228 #define XIP_START XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR)
230 mov r3, r3, lsr #SECTION_SHIFT
231 orr r3, r7, r3, lsl #SECTION_SHIFT
232 add r0, r4, #(XIP_START & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER)
233 str r3, [r0, #((XIP_START & 0x00f00000) >> SECTION_SHIFT) << PMD_ORDER]!
234 ldr r6, =(_edata_loc - 1)
235 add r0, r0, #1 << PMD_ORDER
236 add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
238 add r3, r3, #1 << SECTION_SHIFT
239 strls r3, [r0], #1 << PMD_ORDER
244 * Then map boot params address in r2 if specified.
246 mov r0, r2, lsr #SECTION_SHIFT
247 movs r0, r0, lsl #SECTION_SHIFT
249 addne r3, r3, #PAGE_OFFSET
250 addne r3, r4, r3, lsr #(SECTION_SHIFT - PMD_ORDER)
254 #ifdef CONFIG_DEBUG_LL
255 #if !defined(CONFIG_DEBUG_ICEDCC) && !defined(CONFIG_DEBUG_SEMIHOSTING)
257 * Map in IO space for serial debugging.
258 * This allows debug messages to be output
259 * via a serial console before paging_init.
263 mov r3, r3, lsr #SECTION_SHIFT
264 mov r3, r3, lsl #PMD_ORDER
267 mov r3, r7, lsr #SECTION_SHIFT
268 ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
269 orr r3, r7, r3, lsl #SECTION_SHIFT
270 #ifdef CONFIG_ARM_LPAE
271 mov r7, #1 << (54 - 32) @ XN
273 orr r3, r3, #PMD_SECT_XN
276 #ifdef CONFIG_ARM_LPAE
280 #else /* CONFIG_DEBUG_ICEDCC || CONFIG_DEBUG_SEMIHOSTING */
281 /* we don't need any serial debugging mappings */
282 ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
285 #if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS)
287 * If we're using the NetWinder or CATS, we also need to map
288 * in the 16550-type serial port for the debug messages
290 add r0, r4, #0xff000000 >> (SECTION_SHIFT - PMD_ORDER)
291 orr r3, r7, #0x7c000000
294 #ifdef CONFIG_ARCH_RPC
296 * Map in screen at 0x02000000 & SCREEN2_BASE
297 * Similar reasons here - for debug. This is
298 * only for Acorn RiscPC architectures.
300 add r0, r4, #0x02000000 >> (SECTION_SHIFT - PMD_ORDER)
301 orr r3, r7, #0x02000000
303 add r0, r4, #0xd8000000 >> (SECTION_SHIFT - PMD_ORDER)
307 #ifdef CONFIG_ARM_LPAE
308 sub r4, r4, #0x1000 @ point to the PGD table
311 ENDPROC(__create_page_tables)
317 .long __turn_mmu_on_end
319 #if defined(CONFIG_SMP)
321 ENTRY(secondary_startup)
323 * Common entry point for secondary CPUs.
325 * Ensure that we're in SVC mode, and IRQs are disabled. Lookup
326 * the processor type - there is no need to check the machine type
327 * as it has already been validated by the primary processor.
329 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9
330 mrc p15, 0, r9, c0, c0 @ get processor id
331 bl __lookup_processor_type
332 movs r10, r5 @ invalid processor?
333 moveq r0, #'p' @ yes, error 'p'
334 THUMB( it eq ) @ force fixup-able long branch encoding
338 * Use the page tables supplied from __cpu_up.
340 adr r4, __secondary_data
341 ldmia r4, {r5, r7, r12} @ address to jump to after
342 sub lr, r4, r5 @ mmu has been enabled
343 ldr r4, [r7, lr] @ get secondary_data.pgdir
345 ldr r8, [r7, lr] @ get secondary_data.swapper_pg_dir
346 adr lr, BSYM(__enable_mmu) @ return address
347 mov r13, r12 @ __secondary_switched address
348 ARM( add pc, r10, #PROCINFO_INITFUNC ) @ initialise processor
349 @ (return control reg)
350 THUMB( add r12, r10, #PROCINFO_INITFUNC )
352 ENDPROC(secondary_startup)
355 * r6 = &secondary_data
357 ENTRY(__secondary_switched)
358 ldr sp, [r7, #4] @ get secondary_data.stack
360 b secondary_start_kernel
361 ENDPROC(__secondary_switched)
365 .type __secondary_data, %object
369 .long __secondary_switched
370 #endif /* defined(CONFIG_SMP) */
375 * Setup common bits before finally enabling the MMU. Essentially
376 * this is just loading the page table pointer and domain access
379 * r0 = cp#15 control register
381 * r2 = atags or dtb pointer
382 * r4 = page table pointer
384 * r13 = *virtual* address to jump to upon completion
387 #if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6
392 #ifdef CONFIG_CPU_DCACHE_DISABLE
395 #ifdef CONFIG_CPU_BPREDICT_DISABLE
398 #ifdef CONFIG_CPU_ICACHE_DISABLE
401 #ifdef CONFIG_ARM_LPAE
403 mcrr p15, 0, r4, r5, c2 @ load TTBR0
405 mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
406 domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
407 domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
408 domain_val(DOMAIN_IO, DOMAIN_CLIENT))
409 mcr p15, 0, r5, c3, c0, 0 @ load domain access register
410 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
413 ENDPROC(__enable_mmu)
416 * Enable the MMU. This completely changes the structure of the visible
417 * memory space. You will not be able to trace execution through this.
418 * If you have an enquiry about this, *please* check the linux-arm-kernel
419 * mailing list archives BEFORE sending another post to the list.
421 * r0 = cp#15 control register
423 * r2 = atags or dtb pointer
425 * r13 = *virtual* address to jump to upon completion
427 * other registers depend on the function called upon completion
430 .pushsection .idmap.text, "ax"
434 mcr p15, 0, r0, c1, c0, 0 @ write control reg
435 mrc p15, 0, r3, c0, c0, 0 @ read id reg
441 ENDPROC(__turn_mmu_on)
445 #ifdef CONFIG_SMP_ON_UP
448 and r3, r9, #0x000f0000 @ architecture version
449 teq r3, #0x000f0000 @ CPU ID supported?
450 bne __fixup_smp_on_up @ no, assume UP
452 bic r3, r9, #0x00ff0000
453 bic r3, r3, #0x0000000f @ mask 0xff00fff0
455 orr r4, r4, #0x0000b000
456 orr r4, r4, #0x00000020 @ val 0x4100b020
457 teq r3, r4 @ ARM 11MPCore?
458 moveq pc, lr @ yes, assume SMP
460 mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
461 and r0, r0, #0xc0000000 @ multiprocessing extensions and
462 teq r0, #0x80000000 @ not part of a uniprocessor system?
463 moveq pc, lr @ yes, assume SMP
471 b __do_fixup_smp_on_up
488 __do_fixup_smp_on_up:
492 ARM( str r6, [r0, r3] )
493 THUMB( add r0, r0, r3 )
495 THUMB( mov r6, r6, ror #16 ) @ Convert word order for big-endian.
497 THUMB( strh r6, [r0], #2 ) @ For Thumb-2, store as two halfwords
498 THUMB( mov r6, r6, lsr #16 ) @ to be robust against misaligned r3.
499 THUMB( strh r6, [r0] )
500 b __do_fixup_smp_on_up
501 ENDPROC(__do_fixup_smp_on_up)
504 stmfd sp!, {r4 - r6, lr}
508 bl __do_fixup_smp_on_up
509 ldmfd sp!, {r4 - r6, pc}
512 #ifdef CONFIG_ARM_PATCH_PHYS_VIRT
514 /* __fixup_pv_table - patch the stub instructions with the delta between
515 * PHYS_OFFSET and PAGE_OFFSET, which is assumed to be 16MiB aligned and
516 * can be expressed by an immediate shifter operand. The stub instruction
517 * has a form of '(add|sub) rd, rn, #imm'.
522 ldmia r0, {r3-r5, r7}
523 sub r3, r0, r3 @ PHYS_OFFSET - PAGE_OFFSET
524 add r4, r4, r3 @ adjust table start address
525 add r5, r5, r3 @ adjust table end address
526 add r7, r7, r3 @ adjust __pv_phys_offset address
527 str r8, [r7] @ save computed PHYS_OFFSET to __pv_phys_offset
528 mov r6, r3, lsr #24 @ constant for add/sub instructions
529 teq r3, r6, lsl #24 @ must be 16MiB aligned
530 THUMB( it ne @ cross section branch )
532 str r6, [r7, #4] @ save to __pv_offset
534 ENDPROC(__fixup_pv_table)
538 .long __pv_table_begin
540 2: .long __pv_phys_offset
544 #ifdef CONFIG_THUMB2_KERNEL
553 orr r6, r6, r7, lsl #12
559 orr ip, r6 @ mask in offset bits 31-24
562 ldrcc r7, [r4], #4 @ use branch for delay slot
568 bic ip, ip, #0x000000ff
569 orr ip, ip, r6 @ mask in offset bits 31-24
572 ldrcc r7, [r4], #4 @ use branch for delay slot
576 ENDPROC(__fixup_a_pv_table)
578 ENTRY(fixup_pv_table)
579 stmfd sp!, {r4 - r7, lr}
580 ldr r2, 2f @ get address of __pv_phys_offset
581 mov r3, #0 @ no offset
582 mov r4, r0 @ r0 = table start
583 add r5, r0, r1 @ r1 = table size
584 ldr r6, [r2, #4] @ get __pv_offset
585 bl __fixup_a_pv_table
586 ldmfd sp!, {r4 - r7, pc}
587 ENDPROC(fixup_pv_table)
590 2: .long __pv_phys_offset
593 .globl __pv_phys_offset
594 .type __pv_phys_offset, %object
597 .size __pv_phys_offset, . - __pv_phys_offset
602 #include "head-common.S"