2 * linux/arch/arm/kernel/head.S
4 * Copyright (C) 1994-2002 Russell King
5 * Copyright (c) 2003 ARM Limited
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * Kernel startup code for all 32-bit CPUs
14 #include <linux/linkage.h>
15 #include <linux/init.h>
17 #include <asm/assembler.h>
18 #include <asm/domain.h>
19 #include <asm/ptrace.h>
20 #include <asm/asm-offsets.h>
21 #include <asm/memory.h>
22 #include <asm/thread_info.h>
23 #include <asm/system.h>
24 #include <asm/pgtable.h>
26 #ifdef CONFIG_DEBUG_LL
27 #include <mach/debug-macro.S>
31 * swapper_pg_dir is the virtual address of the initial page table.
32 * We place the page tables 16K below KERNEL_RAM_VADDR. Therefore, we must
33 * make sure that KERNEL_RAM_VADDR is correctly set. Currently, we expect
34 * the least significant 16 bits to be 0x8000, but we could probably
35 * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000.
37 #define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET)
38 #if (KERNEL_RAM_VADDR & 0xffff) != 0x8000
39 #error KERNEL_RAM_VADDR must start at 0xXXXX8000
42 #define PG_DIR_SIZE 0x4000
46 .equ swapper_pg_dir, KERNEL_RAM_VADDR - PG_DIR_SIZE
48 .macro pgtbl, rd, phys
49 add \rd, \phys, #TEXT_OFFSET - PG_DIR_SIZE
52 #ifdef CONFIG_XIP_KERNEL
53 #define KERNEL_START XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR)
54 #define KERNEL_END _edata_loc
56 #define KERNEL_START KERNEL_RAM_VADDR
57 #define KERNEL_END _end
61 * Kernel startup entry point.
62 * ---------------------------
64 * This is normally called from the decompressor code. The requirements
65 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
66 * r1 = machine nr, r2 = atags or dtb pointer.
68 * This code is mostly position independent, so if you link the kernel at
69 * 0xc0008000, you call this at __pa(0xc0008000).
71 * See linux/arch/arm/tools/mach-types for the complete list of machine
74 * We're trying to keep crap to a minimum; DO NOT add any machine specific
75 * crap here - that's what the boot loader (or in extreme, well justified
76 * circumstances, zImage) is for.
83 THUMB( adr r9, BSYM(1f) ) @ Kernel is always entered in ARM.
84 THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
85 THUMB( .thumb ) @ switch to Thumb now.
88 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
90 mrc p15, 0, r9, c0, c0 @ get processor id
91 bl __lookup_processor_type @ r5=procinfo r9=cpuid
92 movs r10, r5 @ invalid processor (r5=0)?
93 THUMB( it eq ) @ force fixup-able long branch encoding
94 beq __error_p @ yes, error 'p'
96 #ifndef CONFIG_XIP_KERNEL
99 sub r4, r3, r4 @ (PHYS_OFFSET - PAGE_OFFSET)
100 add r8, r8, r4 @ PHYS_OFFSET
102 ldr r8, =PHYS_OFFSET @ always constant in this case
106 * r1 = machine no, r2 = atags or dtb,
107 * r8 = phys_offset, r9 = cpuid, r10 = procinfo
110 #ifdef CONFIG_SMP_ON_UP
113 #ifdef CONFIG_ARM_PATCH_PHYS_VIRT
116 bl __create_page_tables
119 * The following calls CPU specific code in a position independent
120 * manner. See arch/arm/mm/proc-*.S for details. r10 = base of
121 * xxx_proc_info structure selected by __lookup_processor_type
122 * above. On return, the CPU will be ready for the MMU to be
123 * turned on, and r0 will hold the CPU control register value.
125 ldr r13, =__mmap_switched @ address to jump to after
126 @ mmu has been enabled
127 adr lr, BSYM(1f) @ return (PIC) address
128 mov r8, r4 @ set TTBR1 to swapper_pg_dir
129 ARM( add pc, r10, #PROCINFO_INITFUNC )
130 THUMB( add r12, r10, #PROCINFO_INITFUNC )
135 #ifndef CONFIG_XIP_KERNEL
141 * Setup the initial page tables. We only setup the barest
142 * amount which are required to get the kernel running, which
143 * generally means mapping in the kernel code.
145 * r8 = phys_offset, r9 = cpuid, r10 = procinfo
148 * r0, r3, r5-r7 corrupted
149 * r4 = physical page table address
151 __create_page_tables:
152 pgtbl r4, r8 @ page table address
155 * Clear the swapper page table
159 add r6, r0, #PG_DIR_SIZE
167 ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags
170 * Create identity mapping to cater for __enable_mmu.
171 * This identity mapping will be removed by paging_init().
173 adr r0, __enable_mmu_loc
174 ldmia r0, {r3, r5, r6}
175 sub r0, r0, r3 @ virt->phys offset
176 add r5, r5, r0 @ phys __enable_mmu
177 add r6, r6, r0 @ phys __enable_mmu_end
178 mov r5, r5, lsr #SECTION_SHIFT
179 mov r6, r6, lsr #SECTION_SHIFT
181 1: orr r3, r7, r5, lsl #SECTION_SHIFT @ flags + kernel base
182 str r3, [r4, r5, lsl #PMD_ORDER] @ identity mapping
184 addlo r5, r5, #1 @ next section
188 * Now setup the pagetables for our kernel direct
192 mov r3, r3, lsr #SECTION_SHIFT
193 orr r3, r7, r3, lsl #SECTION_SHIFT
194 add r0, r4, #(KERNEL_START & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER)
195 str r3, [r0, #((KERNEL_START & 0x00f00000) >> SECTION_SHIFT) << PMD_ORDER]!
196 ldr r6, =(KERNEL_END - 1)
197 add r0, r0, #1 << PMD_ORDER
198 add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
200 add r3, r3, #1 << SECTION_SHIFT
201 strls r3, [r0], #1 << PMD_ORDER
204 #ifdef CONFIG_XIP_KERNEL
206 * Map some ram to cover our .data and .bss areas.
208 add r3, r8, #TEXT_OFFSET
210 add r0, r4, #(KERNEL_RAM_VADDR & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER)
211 str r3, [r0, #(KERNEL_RAM_VADDR & 0x00f00000) >> (SECTION_SHIFT - PMD_ORDER)]!
214 add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
222 * Then map boot params address in r2 or
223 * the first 1MB of ram if boot params address is not specified.
224 * We map 2 sections in case the ATAGs/DTB crosses a section boundary.
226 mov r0, r2, lsr #SECTION_SHIFT
227 movs r0, r0, lsl #SECTION_SHIFT
230 add r3, r3, #PAGE_OFFSET
231 add r3, r4, r3, lsr #(SECTION_SHIFT - PMD_ORDER)
233 str r6, [r3], #1 << PMD_ORDER
234 add r6, r6, #1 << SECTION_SHIFT
237 #ifdef CONFIG_DEBUG_LL
238 #ifndef CONFIG_DEBUG_ICEDCC
240 * Map in IO space for serial debugging.
241 * This allows debug messages to be output
242 * via a serial console before paging_init.
246 mov r3, r3, lsr #SECTION_SHIFT
247 mov r3, r3, lsl #PMD_ORDER
250 rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long)
251 cmp r3, #0x0800 @ limit to 512MB
254 mov r3, r7, lsr #SECTION_SHIFT
255 ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
256 orr r3, r7, r3, lsl #SECTION_SHIFT
258 add r3, r3, #1 << SECTION_SHIFT
262 #else /* CONFIG_DEBUG_ICEDCC */
263 /* we don't need any serial debugging mappings for ICEDCC */
264 ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
265 #endif /* !CONFIG_DEBUG_ICEDCC */
267 #if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS)
269 * If we're using the NetWinder or CATS, we also need to map
270 * in the 16550-type serial port for the debug messages
272 add r0, r4, #0xff000000 >> (SECTION_SHIFT - PMD_ORDER)
273 orr r3, r7, #0x7c000000
276 #ifdef CONFIG_ARCH_RPC
278 * Map in screen at 0x02000000 & SCREEN2_BASE
279 * Similar reasons here - for debug. This is
280 * only for Acorn RiscPC architectures.
282 add r0, r4, #0x02000000 >> (SECTION_SHIFT - PMD_ORDER)
283 orr r3, r7, #0x02000000
285 add r0, r4, #0xd8000000 >> (SECTION_SHIFT - PMD_ORDER)
290 ENDPROC(__create_page_tables)
296 .long __enable_mmu_end
298 #if defined(CONFIG_SMP)
300 ENTRY(secondary_startup)
302 * Common entry point for secondary CPUs.
304 * Ensure that we're in SVC mode, and IRQs are disabled. Lookup
305 * the processor type - there is no need to check the machine type
306 * as it has already been validated by the primary processor.
308 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9
309 mrc p15, 0, r9, c0, c0 @ get processor id
310 bl __lookup_processor_type
311 movs r10, r5 @ invalid processor?
312 moveq r0, #'p' @ yes, error 'p'
313 THUMB( it eq ) @ force fixup-able long branch encoding
317 * Use the page tables supplied from __cpu_up.
319 adr r4, __secondary_data
320 ldmia r4, {r5, r7, r12} @ address to jump to after
321 sub lr, r4, r5 @ mmu has been enabled
322 ldr r4, [r7, lr] @ get secondary_data.pgdir
324 ldr r8, [r7, lr] @ get secondary_data.swapper_pg_dir
325 adr lr, BSYM(__enable_mmu) @ return address
326 mov r13, r12 @ __secondary_switched address
327 ARM( add pc, r10, #PROCINFO_INITFUNC ) @ initialise processor
328 @ (return control reg)
329 THUMB( add r12, r10, #PROCINFO_INITFUNC )
331 ENDPROC(secondary_startup)
334 * r6 = &secondary_data
336 ENTRY(__secondary_switched)
337 ldr sp, [r7, #4] @ get secondary_data.stack
339 b secondary_start_kernel
340 ENDPROC(__secondary_switched)
344 .type __secondary_data, %object
348 .long __secondary_switched
349 #endif /* defined(CONFIG_SMP) */
354 * Setup common bits before finally enabling the MMU. Essentially
355 * this is just loading the page table pointer and domain access
358 * r0 = cp#15 control register
360 * r2 = atags or dtb pointer
361 * r4 = page table pointer
363 * r13 = *virtual* address to jump to upon completion
366 #if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6
371 #ifdef CONFIG_CPU_DCACHE_DISABLE
374 #ifdef CONFIG_CPU_BPREDICT_DISABLE
377 #ifdef CONFIG_CPU_ICACHE_DISABLE
380 mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
381 domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
382 domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
383 domain_val(DOMAIN_IO, DOMAIN_CLIENT))
384 mcr p15, 0, r5, c3, c0, 0 @ load domain access register
385 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
387 ENDPROC(__enable_mmu)
390 * Enable the MMU. This completely changes the structure of the visible
391 * memory space. You will not be able to trace execution through this.
392 * If you have an enquiry about this, *please* check the linux-arm-kernel
393 * mailing list archives BEFORE sending another post to the list.
395 * r0 = cp#15 control register
397 * r2 = atags or dtb pointer
399 * r13 = *virtual* address to jump to upon completion
401 * other registers depend on the function called upon completion
406 mcr p15, 0, r0, c1, c0, 0 @ write control reg
407 mrc p15, 0, r3, c0, c0, 0 @ read id reg
412 ENDPROC(__turn_mmu_on)
415 #ifdef CONFIG_SMP_ON_UP
418 and r3, r9, #0x000f0000 @ architecture version
419 teq r3, #0x000f0000 @ CPU ID supported?
420 bne __fixup_smp_on_up @ no, assume UP
422 bic r3, r9, #0x00ff0000
423 bic r3, r3, #0x0000000f @ mask 0xff00fff0
425 orr r4, r4, #0x0000b000
426 orr r4, r4, #0x00000020 @ val 0x4100b020
427 teq r3, r4 @ ARM 11MPCore?
428 moveq pc, lr @ yes, assume SMP
430 mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
431 and r0, r0, #0xc0000000 @ multiprocessing extensions and
432 teq r0, #0x80000000 @ not part of a uniprocessor system?
433 moveq pc, lr @ yes, assume SMP
441 b __do_fixup_smp_on_up
458 __do_fixup_smp_on_up:
462 ARM( str r6, [r0, r3] )
463 THUMB( add r0, r0, r3 )
465 THUMB( mov r6, r6, ror #16 ) @ Convert word order for big-endian.
467 THUMB( strh r6, [r0], #2 ) @ For Thumb-2, store as two halfwords
468 THUMB( mov r6, r6, lsr #16 ) @ to be robust against misaligned r3.
469 THUMB( strh r6, [r0] )
470 b __do_fixup_smp_on_up
471 ENDPROC(__do_fixup_smp_on_up)
474 stmfd sp!, {r4 - r6, lr}
478 bl __do_fixup_smp_on_up
479 ldmfd sp!, {r4 - r6, pc}
482 #ifdef CONFIG_ARM_PATCH_PHYS_VIRT
484 /* __fixup_pv_table - patch the stub instructions with the delta between
485 * PHYS_OFFSET and PAGE_OFFSET, which is assumed to be 16MiB aligned and
486 * can be expressed by an immediate shifter operand. The stub instruction
487 * has a form of '(add|sub) rd, rn, #imm'.
492 ldmia r0, {r3-r5, r7}
493 sub r3, r0, r3 @ PHYS_OFFSET - PAGE_OFFSET
494 add r4, r4, r3 @ adjust table start address
495 add r5, r5, r3 @ adjust table end address
496 add r7, r7, r3 @ adjust __pv_phys_offset address
497 str r8, [r7] @ save computed PHYS_OFFSET to __pv_phys_offset
498 mov r6, r3, lsr #24 @ constant for add/sub instructions
499 teq r3, r6, lsl #24 @ must be 16MiB aligned
500 THUMB( it ne @ cross section branch )
502 str r6, [r7, #4] @ save to __pv_offset
504 ENDPROC(__fixup_pv_table)
508 .long __pv_table_begin
510 2: .long __pv_phys_offset
514 #ifdef CONFIG_THUMB2_KERNEL
523 orr r6, r6, r7, lsl #12
529 orr ip, r6 @ mask in offset bits 31-24
532 ldrcc r7, [r4], #4 @ use branch for delay slot
538 bic ip, ip, #0x000000ff
539 orr ip, ip, r6 @ mask in offset bits 31-24
542 ldrcc r7, [r4], #4 @ use branch for delay slot
546 ENDPROC(__fixup_a_pv_table)
548 ENTRY(fixup_pv_table)
549 stmfd sp!, {r4 - r7, lr}
550 ldr r2, 2f @ get address of __pv_phys_offset
551 mov r3, #0 @ no offset
552 mov r4, r0 @ r0 = table start
553 add r5, r0, r1 @ r1 = table size
554 ldr r6, [r2, #4] @ get __pv_offset
555 bl __fixup_a_pv_table
556 ldmfd sp!, {r4 - r7, pc}
557 ENDPROC(fixup_pv_table)
560 2: .long __pv_phys_offset
563 .globl __pv_phys_offset
564 .type __pv_phys_offset, %object
567 .size __pv_phys_offset, . - __pv_phys_offset
572 #include "head-common.S"