2 * linux/arch/arm/kernel/bios32.c
4 * PCI bios-type initialisation for PCI machines
6 * Bits taken from various places.
8 #include <linux/export.h>
9 #include <linux/kernel.h>
10 #include <linux/pci.h>
11 #include <linux/slab.h>
12 #include <linux/init.h>
15 #include <asm/mach-types.h>
16 #include <asm/mach/map.h>
17 #include <asm/mach/pci.h>
22 * We can't use pci_find_device() here since we are
23 * called from interrupt context.
25 static void pcibios_bus_report_status(struct pci_bus *bus, u_int status_mask, int warn)
29 list_for_each_entry(dev, &bus->devices, bus_list) {
33 * ignore host bridge - we handle
36 if (dev->bus->number == 0 && dev->devfn == 0)
39 pci_read_config_word(dev, PCI_STATUS, &status);
43 if ((status & status_mask) == 0)
46 /* clear the status errors */
47 pci_write_config_word(dev, PCI_STATUS, status & status_mask);
50 printk("(%s: %04X) ", pci_name(dev), status);
53 list_for_each_entry(dev, &bus->devices, bus_list)
55 pcibios_bus_report_status(dev->subordinate, status_mask, warn);
58 void pcibios_report_status(u_int status_mask, int warn)
62 list_for_each(l, &pci_root_buses) {
63 struct pci_bus *bus = pci_bus_b(l);
65 pcibios_bus_report_status(bus, status_mask, warn);
70 * We don't use this to fix the device, but initialisation of it.
71 * It's not the correct use for this, but it works.
72 * Note that the arbiter/ISA bridge appears to be buggy, specifically in
75 * 2. ISA bridge ping-pong
76 * 3. ISA bridge master handling of target RETRY
78 * Bug 3 is responsible for the sound DMA grinding to a halt. We now
81 static void __devinit pci_fixup_83c553(struct pci_dev *dev)
84 * Set memory region to start at address 0, and enable IO
86 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_SPACE_MEMORY);
87 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO);
89 dev->resource[0].end -= dev->resource[0].start;
90 dev->resource[0].start = 0;
93 * All memory requests from ISA to be channelled to PCI
95 pci_write_config_byte(dev, 0x48, 0xff);
98 * Enable ping-pong on bus master to ISA bridge transactions.
99 * This improves the sound DMA substantially. The fixed
100 * priority arbiter also helps (see below).
102 pci_write_config_byte(dev, 0x42, 0x01);
107 pci_write_config_byte(dev, 0x40, 0x22);
110 * We used to set the arbiter to "park on last master" (bit
111 * 1 set), but unfortunately the CyberPro does not park the
112 * bus. We must therefore park on CPU. Unfortunately, this
113 * may trigger yet another bug in the 553.
115 pci_write_config_byte(dev, 0x83, 0x02);
118 * Make the ISA DMA request lowest priority, and disable
119 * rotating priorities completely.
121 pci_write_config_byte(dev, 0x80, 0x11);
122 pci_write_config_byte(dev, 0x81, 0x00);
125 * Route INTA input to IRQ 11, and set IRQ11 to be level
128 pci_write_config_word(dev, 0x44, 0xb000);
131 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_83C553, pci_fixup_83c553);
133 static void __devinit pci_fixup_unassign(struct pci_dev *dev)
135 dev->resource[0].end -= dev->resource[0].start;
136 dev->resource[0].start = 0;
138 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_89C940F, pci_fixup_unassign);
141 * Prevent the PCI layer from seeing the resources allocated to this device
142 * if it is the host bridge by marking it as such. These resources are of
143 * no consequence to the PCI layer (they are handled elsewhere).
145 static void __devinit pci_fixup_dec21285(struct pci_dev *dev)
149 if (dev->devfn == 0) {
151 dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
152 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
153 dev->resource[i].start = 0;
154 dev->resource[i].end = 0;
155 dev->resource[i].flags = 0;
159 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21285, pci_fixup_dec21285);
162 * PCI IDE controllers use non-standard I/O port decoding, respect it.
164 static void __devinit pci_fixup_ide_bases(struct pci_dev *dev)
169 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
172 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
173 r = dev->resource + i;
174 if ((r->start & ~0x80) == 0x374) {
180 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
183 * Put the DEC21142 to sleep
185 static void __devinit pci_fixup_dec21142(struct pci_dev *dev)
187 pci_write_config_dword(dev, 0x40, 0x80000000);
189 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142, pci_fixup_dec21142);
192 * The CY82C693 needs some rather major fixups to ensure that it does
193 * the right thing. Idea from the Alpha people, with a few additions.
195 * We ensure that the IDE base registers are set to 1f0/3f4 for the
196 * primary bus, and 170/374 for the secondary bus. Also, hide them
197 * from the PCI subsystem view as well so we won't try to perform
198 * our own auto-configuration on them.
200 * In addition, we ensure that the PCI IDE interrupts are routed to
201 * IRQ 14 and IRQ 15 respectively.
203 * The above gets us to a point where the IDE on this device is
204 * functional. However, The CY82C693U _does not work_ in bus
205 * master mode without locking the PCI bus solid.
207 static void __devinit pci_fixup_cy82c693(struct pci_dev *dev)
209 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
212 if (dev->class & 0x80) { /* primary */
215 } else { /* secondary */
220 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
221 base0 | PCI_BASE_ADDRESS_SPACE_IO);
222 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1,
223 base1 | PCI_BASE_ADDRESS_SPACE_IO);
225 dev->resource[0].start = 0;
226 dev->resource[0].end = 0;
227 dev->resource[0].flags = 0;
229 dev->resource[1].start = 0;
230 dev->resource[1].end = 0;
231 dev->resource[1].flags = 0;
232 } else if (PCI_FUNC(dev->devfn) == 0) {
234 * Setup IDE IRQ routing.
236 pci_write_config_byte(dev, 0x4b, 14);
237 pci_write_config_byte(dev, 0x4c, 15);
240 * Disable FREQACK handshake, enable USB.
242 pci_write_config_byte(dev, 0x4d, 0x41);
245 * Enable PCI retry, and PCI post-write buffer.
247 pci_write_config_byte(dev, 0x44, 0x17);
250 * Enable ISA master and DMA post write buffering.
252 pci_write_config_byte(dev, 0x45, 0x03);
255 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693);
257 static void __devinit pci_fixup_it8152(struct pci_dev *dev)
260 /* fixup for ITE 8152 devices */
261 /* FIXME: add defines for class 0x68000 and 0x80103 */
262 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST ||
263 dev->class == 0x68000 ||
264 dev->class == 0x80103) {
265 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
266 dev->resource[i].start = 0;
267 dev->resource[i].end = 0;
268 dev->resource[i].flags = 0;
272 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8152, pci_fixup_it8152);
276 void __devinit pcibios_update_irq(struct pci_dev *dev, int irq)
279 printk("PCI: Assigning IRQ %02d to %s\n", irq, pci_name(dev));
280 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
284 * If the bus contains any of these devices, then we must not turn on
285 * parity checking of any kind. Currently this is CyberPro 20x0 only.
287 static inline int pdev_bad_for_parity(struct pci_dev *dev)
289 return ((dev->vendor == PCI_VENDOR_ID_INTERG &&
290 (dev->device == PCI_DEVICE_ID_INTERG_2000 ||
291 dev->device == PCI_DEVICE_ID_INTERG_2010)) ||
292 (dev->vendor == PCI_VENDOR_ID_ITE &&
293 dev->device == PCI_DEVICE_ID_ITE_8152));
298 * pcibios_fixup_bus - Called after each bus is probed,
299 * but before its children are examined.
301 void pcibios_fixup_bus(struct pci_bus *bus)
304 u16 features = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_FAST_BACK;
307 * Walk the devices on this bus, working out what we can
310 list_for_each_entry(dev, &bus->devices, bus_list) {
313 pci_read_config_word(dev, PCI_STATUS, &status);
316 * If any device on this bus does not support fast back
317 * to back transfers, then the bus as a whole is not able
318 * to support them. Having fast back to back transfers
319 * on saves us one PCI cycle per transaction.
321 if (!(status & PCI_STATUS_FAST_BACK))
322 features &= ~PCI_COMMAND_FAST_BACK;
324 if (pdev_bad_for_parity(dev))
325 features &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
327 switch (dev->class >> 8) {
328 case PCI_CLASS_BRIDGE_PCI:
329 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &status);
330 status |= PCI_BRIDGE_CTL_PARITY|PCI_BRIDGE_CTL_MASTER_ABORT;
331 status &= ~(PCI_BRIDGE_CTL_BUS_RESET|PCI_BRIDGE_CTL_FAST_BACK);
332 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, status);
335 case PCI_CLASS_BRIDGE_CARDBUS:
336 pci_read_config_word(dev, PCI_CB_BRIDGE_CONTROL, &status);
337 status |= PCI_CB_BRIDGE_CTL_PARITY|PCI_CB_BRIDGE_CTL_MASTER_ABORT;
338 pci_write_config_word(dev, PCI_CB_BRIDGE_CONTROL, status);
344 * Now walk the devices again, this time setting them up.
346 list_for_each_entry(dev, &bus->devices, bus_list) {
349 pci_read_config_word(dev, PCI_COMMAND, &cmd);
351 pci_write_config_word(dev, PCI_COMMAND, cmd);
353 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
354 L1_CACHE_BYTES >> 2);
358 * Propagate the flags to the PCI bridge.
360 if (bus->self && bus->self->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
361 if (features & PCI_COMMAND_FAST_BACK)
362 bus->bridge_ctl |= PCI_BRIDGE_CTL_FAST_BACK;
363 if (features & PCI_COMMAND_PARITY)
364 bus->bridge_ctl |= PCI_BRIDGE_CTL_PARITY;
368 * Report what we did for this bus
370 printk(KERN_INFO "PCI: bus%d: Fast back to back transfers %sabled\n",
371 bus->number, (features & PCI_COMMAND_FAST_BACK) ? "en" : "dis");
373 #ifdef CONFIG_HOTPLUG
374 EXPORT_SYMBOL(pcibios_fixup_bus);
378 * Swizzle the device pin each time we cross a bridge. If a platform does
379 * not provide a swizzle function, we perform the standard PCI swizzling.
381 * The default swizzling walks up the bus tree one level at a time, applying
382 * the standard swizzle function at each step, stopping when it finds the PCI
383 * root bus. This will return the slot number of the bridge device on the
384 * root bus and the interrupt pin on that device which should correspond
385 * with the downstream device interrupt.
387 * Platforms may override this, in which case the slot and pin returned
388 * depend entirely on the platform code. However, please note that the
389 * PCI standard swizzle is implemented on plug-in cards and Cardbus based
390 * PCI extenders, so it can not be ignored.
392 static u8 __devinit pcibios_swizzle(struct pci_dev *dev, u8 *pin)
394 struct pci_sys_data *sys = dev->sysdata;
395 int slot, oldpin = *pin;
398 slot = sys->swizzle(dev, pin);
400 slot = pci_common_swizzle(dev, pin);
403 printk("PCI: %s swizzling pin %d => pin %d slot %d\n",
404 pci_name(dev), oldpin, *pin, slot);
410 * Map a slot/pin to an IRQ.
412 static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
414 struct pci_sys_data *sys = dev->sysdata;
418 irq = sys->map_irq(dev, slot, pin);
421 printk("PCI: %s mapping slot %d pin %d => irq %d\n",
422 pci_name(dev), slot, pin, irq);
427 static int __init pcibios_init_resources(int busnr, struct pci_sys_data *sys)
430 struct pci_host_bridge_window *window;
432 if (list_empty(&sys->resources)) {
433 pci_add_resource_offset(&sys->resources,
434 &iomem_resource, sys->mem_offset);
437 list_for_each_entry(window, &sys->resources, list) {
438 if (resource_type(window->res) == IORESOURCE_IO)
442 sys->io_res.start = (busnr * SZ_64K) ? : pcibios_min_io;
443 sys->io_res.end = (busnr + 1) * SZ_64K - 1;
444 sys->io_res.flags = IORESOURCE_IO;
445 sys->io_res.name = sys->io_res_name;
446 sprintf(sys->io_res_name, "PCI%d I/O", busnr);
448 ret = request_resource(&ioport_resource, &sys->io_res);
450 pr_err("PCI: unable to allocate I/O port region (%d)\n", ret);
453 pci_add_resource_offset(&sys->resources, &sys->io_res,
459 static void __init pcibios_init_hw(struct hw_pci *hw, struct list_head *head)
461 struct pci_sys_data *sys = NULL;
465 for (nr = busnr = 0; nr < hw->nr_controllers; nr++) {
466 sys = kzalloc(sizeof(struct pci_sys_data), GFP_KERNEL);
468 panic("PCI: unable to allocate sys data!");
470 #ifdef CONFIG_PCI_DOMAINS
471 sys->domain = hw->domain;
474 sys->swizzle = hw->swizzle;
475 sys->map_irq = hw->map_irq;
476 INIT_LIST_HEAD(&sys->resources);
478 ret = hw->setup(nr, sys);
481 ret = pcibios_init_resources(nr, sys);
488 sys->bus = hw->scan(nr, sys);
490 sys->bus = pci_scan_root_bus(NULL, sys->busnr,
491 hw->ops, sys, &sys->resources);
494 panic("PCI: unable to scan bus!");
496 busnr = sys->bus->busn_res.end + 1;
498 list_add(&sys->node, head);
507 void __init pci_common_init(struct hw_pci *hw)
509 struct pci_sys_data *sys;
512 pci_add_flags(PCI_REASSIGN_ALL_RSRC);
515 pcibios_init_hw(hw, &head);
519 pci_fixup_irqs(pcibios_swizzle, pcibios_map_irq);
521 list_for_each_entry(sys, &head, node) {
522 struct pci_bus *bus = sys->bus;
524 if (!pci_has_flag(PCI_PROBE_ONLY)) {
526 * Size the bridge windows.
528 pci_bus_size_bridges(bus);
533 pci_bus_assign_resources(bus);
538 pci_enable_bridges(bus);
542 * Tell drivers about devices found.
544 pci_bus_add_devices(bus);
548 #ifndef CONFIG_PCI_HOST_ITE8152
549 void pcibios_set_master(struct pci_dev *dev)
551 /* No special bus mastering setup handling */
555 char * __init pcibios_setup(char *str)
557 if (!strcmp(str, "debug")) {
560 } else if (!strcmp(str, "firmware")) {
561 pci_add_flags(PCI_PROBE_ONLY);
568 * From arch/i386/kernel/pci-i386.c:
570 * We need to avoid collisions with `mirrored' VGA ports
571 * and other strange ISA hardware, so we always want the
572 * addresses to be allocated in the 0x000-0x0ff region
575 * Why? Because some silly external IO cards only decode
576 * the low 10 bits of the IO address. The 0x00-0xff region
577 * is reserved for motherboard devices that decode all 16
578 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
579 * but we want to try to avoid allocating at 0x2900-0x2bff
580 * which might be mirrored at 0x0100-0x03ff..
582 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
583 resource_size_t size, resource_size_t align)
585 resource_size_t start = res->start;
587 if (res->flags & IORESOURCE_IO && start & 0x300)
588 start = (start + 0x3ff) & ~0x3ff;
590 start = (start + align - 1) & ~(align - 1);
596 * pcibios_enable_device - Enable I/O and memory.
597 * @dev: PCI device to be enabled
599 int pcibios_enable_device(struct pci_dev *dev, int mask)
605 pci_read_config_word(dev, PCI_COMMAND, &cmd);
607 for (idx = 0; idx < 6; idx++) {
608 /* Only set up the requested stuff */
609 if (!(mask & (1 << idx)))
612 r = dev->resource + idx;
613 if (!r->start && r->end) {
614 printk(KERN_ERR "PCI: Device %s not available because"
615 " of resource collisions\n", pci_name(dev));
618 if (r->flags & IORESOURCE_IO)
619 cmd |= PCI_COMMAND_IO;
620 if (r->flags & IORESOURCE_MEM)
621 cmd |= PCI_COMMAND_MEMORY;
625 * Bridges (eg, cardbus bridges) need to be fully enabled
627 if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE)
628 cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
630 if (cmd != old_cmd) {
631 printk("PCI: enabling device %s (%04x -> %04x)\n",
632 pci_name(dev), old_cmd, cmd);
633 pci_write_config_word(dev, PCI_COMMAND, cmd);
638 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
639 enum pci_mmap_state mmap_state, int write_combine)
641 struct pci_sys_data *root = dev->sysdata;
644 if (mmap_state == pci_mmap_io) {
647 phys = vma->vm_pgoff + (root->mem_offset >> PAGE_SHIFT);
653 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
655 if (remap_pfn_range(vma, vma->vm_start, phys,
656 vma->vm_end - vma->vm_start,
663 void __init pci_map_io_early(unsigned long pfn)
665 struct map_desc pci_io_desc = {
666 .virtual = PCI_IO_VIRT_BASE,
671 pci_io_desc.pfn = pfn;
672 iotable_init(&pci_io_desc, 1);