1 #ifndef __ASM_ARM_SYSTEM_H
2 #define __ASM_ARM_SYSTEM_H
6 #define CPU_ARCH_UNKNOWN 0
7 #define CPU_ARCH_ARMv3 1
8 #define CPU_ARCH_ARMv4 2
9 #define CPU_ARCH_ARMv4T 3
10 #define CPU_ARCH_ARMv5 4
11 #define CPU_ARCH_ARMv5T 5
12 #define CPU_ARCH_ARMv5TE 6
13 #define CPU_ARCH_ARMv5TEJ 7
14 #define CPU_ARCH_ARMv6 8
15 #define CPU_ARCH_ARMv7 9
18 * CR1 bits (CP#15 CR1)
20 #define CR_M (1 << 0) /* MMU enable */
21 #define CR_A (1 << 1) /* Alignment abort enable */
22 #define CR_C (1 << 2) /* Dcache enable */
23 #define CR_W (1 << 3) /* Write buffer enable */
24 #define CR_P (1 << 4) /* 32-bit exception handler */
25 #define CR_D (1 << 5) /* 32-bit data address range */
26 #define CR_L (1 << 6) /* Implementation defined */
27 #define CR_B (1 << 7) /* Big endian */
28 #define CR_S (1 << 8) /* System MMU protection */
29 #define CR_R (1 << 9) /* ROM MMU protection */
30 #define CR_F (1 << 10) /* Implementation defined */
31 #define CR_Z (1 << 11) /* Implementation defined */
32 #define CR_I (1 << 12) /* Icache enable */
33 #define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
34 #define CR_RR (1 << 14) /* Round Robin cache replacement */
35 #define CR_L4 (1 << 15) /* LDR pc can set T bit */
36 #define CR_DT (1 << 16)
37 #define CR_IT (1 << 18)
38 #define CR_ST (1 << 19)
39 #define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
40 #define CR_U (1 << 22) /* Unaligned access operation */
41 #define CR_XP (1 << 23) /* Extended page tables */
42 #define CR_VE (1 << 24) /* Vectored interrupts */
43 #define CR_EE (1 << 25) /* Exception (Big) Endian */
44 #define CR_TRE (1 << 28) /* TEX remap enable */
45 #define CR_AFE (1 << 29) /* Access flag enable */
46 #define CR_TE (1 << 30) /* Thumb exception enable */
49 * This is used to ensure the compiler did actually allocate the register we
50 * asked it for some inline assembly sequences. Apparently we can't trust
51 * the compiler from one version to another so a bit of paranoia won't hurt.
52 * This string is meant to be concatenated with the inline asm string and
53 * will cause compilation to stop on mismatch.
54 * (for details, see gcc PR 15089)
56 #define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
60 #include <linux/linkage.h>
61 #include <linux/irqflags.h>
63 #include <asm/outercache.h>
65 #define __exception __attribute__((section(".exception.text")))
70 /* information about the system we're running on */
71 extern unsigned int system_rev;
72 extern unsigned int system_serial_low;
73 extern unsigned int system_serial_high;
74 extern unsigned int mem_fclk_21285;
78 void die(const char *msg, struct pt_regs *regs, int err);
81 void arm_notify_die(const char *str, struct pt_regs *regs, struct siginfo *info,
82 unsigned long err, unsigned long trap);
84 void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
86 int sig, int code, const char *name);
88 void hook_ifault_code(int nr, int (*fn)(unsigned long, unsigned int,
90 int sig, int code, const char *name);
93 ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
95 extern asmlinkage void __backtrace(void);
96 extern asmlinkage void c_backtrace(unsigned long fp, int pmode);
99 extern void show_pte(struct mm_struct *mm, unsigned long addr);
100 extern void __show_regs(struct pt_regs *);
102 extern int cpu_architecture(void);
103 extern void cpu_init(void);
105 void arm_machine_restart(char mode, const char *cmd);
106 extern void (*arm_pm_restart)(char str, const char *cmd);
108 #define UDBG_UNDEFINED (1 << 0)
109 #define UDBG_SYSCALL (1 << 1)
110 #define UDBG_BADABORT (1 << 2)
111 #define UDBG_SEGV (1 << 3)
112 #define UDBG_BUS (1 << 4)
114 extern unsigned int user_debug;
116 #if __LINUX_ARM_ARCH__ >= 4
117 #define vectors_high() (cr_alignment & CR_V)
119 #define vectors_high() (0)
122 #if __LINUX_ARM_ARCH__ >= 7
123 #define isb() __asm__ __volatile__ ("isb" : : : "memory")
124 #define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
125 #define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
126 #elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6
127 #define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
128 : : "r" (0) : "memory")
129 #define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
130 : : "r" (0) : "memory")
131 #define dmb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
132 : : "r" (0) : "memory")
133 #elif defined(CONFIG_CPU_FA526)
134 #define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
135 : : "r" (0) : "memory")
136 #define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
137 : : "r" (0) : "memory")
138 #define dmb() __asm__ __volatile__ ("" : : : "memory")
140 #define isb() __asm__ __volatile__ ("" : : : "memory")
141 #define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
142 : : "r" (0) : "memory")
143 #define dmb() __asm__ __volatile__ ("" : : : "memory")
146 #ifdef CONFIG_ARCH_HAS_BARRIERS
147 #include <mach/barriers.h>
148 #elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP)
149 #define mb() do { dsb(); outer_sync(); } while (0)
153 #include <asm/memory.h>
154 #define mb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
155 #define rmb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
156 #define wmb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
160 #define smp_mb() barrier()
161 #define smp_rmb() barrier()
162 #define smp_wmb() barrier()
164 #define smp_mb() dmb()
165 #define smp_rmb() dmb()
166 #define smp_wmb() dmb()
169 #define read_barrier_depends() do { } while(0)
170 #define smp_read_barrier_depends() do { } while(0)
172 #define set_mb(var, value) do { var = value; smp_mb(); } while (0)
173 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
175 extern unsigned long cr_no_alignment; /* defined in entry-armv.S */
176 extern unsigned long cr_alignment; /* defined in entry-armv.S */
178 static inline unsigned int get_cr(void)
181 asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc");
185 static inline void set_cr(unsigned int val)
187 asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR"
188 : : "r" (val) : "cc");
193 extern void adjust_cr(unsigned long mask, unsigned long set);
196 #define CPACC_FULL(n) (3 << (n * 2))
197 #define CPACC_SVC(n) (1 << (n * 2))
198 #define CPACC_DISABLE(n) (0 << (n * 2))
200 static inline unsigned int get_copro_access(void)
203 asm("mrc p15, 0, %0, c1, c0, 2 @ get copro access"
204 : "=r" (val) : : "cc");
208 static inline void set_copro_access(unsigned int val)
210 asm volatile("mcr p15, 0, %0, c1, c0, 2 @ set copro access"
211 : : "r" (val) : "cc");
216 * switch_mm() may do a full cache flush over the context switch,
217 * so enable interrupts over the context switch to avoid high
220 #define __ARCH_WANT_INTERRUPTS_ON_CTXSW
223 * switch_to(prev, next) should switch from task `prev' to `next'
224 * `prev' will never be the same as `next'. schedule() itself
225 * contains the memory barrier to tell GCC not to cache `current'.
227 extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *);
229 #define switch_to(prev,next,last) \
231 last = __switch_to(prev,task_thread_info(prev), task_thread_info(next)); \
234 #if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
236 * On the StrongARM, "swp" is terminally broken since it bypasses the
237 * cache totally. This means that the cache becomes inconsistent, and,
238 * since we use normal loads/stores as well, this is really bad.
239 * Typically, this causes oopsen in filp_close, but could have other,
240 * more disasterous effects. There are two work-arounds:
241 * 1. Disable interrupts and emulate the atomic swap
242 * 2. Clean the cache, perform atomic swap, flush the cache
244 * We choose (1) since its the "easiest" to achieve here and is not
245 * dependent on the processor type.
247 * NOTE that this solution won't work on an SMP system, so explcitly
253 static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
255 extern void __bad_xchg(volatile void *, int);
260 #if __LINUX_ARM_ARCH__ >= 6
267 #if __LINUX_ARM_ARCH__ >= 6
269 asm volatile("@ __xchg1\n"
270 "1: ldrexb %0, [%3]\n"
271 " strexb %1, %2, [%3]\n"
274 : "=&r" (ret), "=&r" (tmp)
279 asm volatile("@ __xchg4\n"
280 "1: ldrex %0, [%3]\n"
281 " strex %1, %2, [%3]\n"
284 : "=&r" (ret), "=&r" (tmp)
288 #elif defined(swp_is_buggy)
290 #error SMP is not supported on this platform
293 raw_local_irq_save(flags);
294 ret = *(volatile unsigned char *)ptr;
295 *(volatile unsigned char *)ptr = x;
296 raw_local_irq_restore(flags);
300 raw_local_irq_save(flags);
301 ret = *(volatile unsigned long *)ptr;
302 *(volatile unsigned long *)ptr = x;
303 raw_local_irq_restore(flags);
307 asm volatile("@ __xchg1\n"
314 asm volatile("@ __xchg4\n"
322 __bad_xchg(ptr, size), ret = 0;
330 extern void disable_hlt(void);
331 extern void enable_hlt(void);
333 void cpu_idle_wait(void);
335 #include <asm-generic/cmpxchg-local.h>
337 #if __LINUX_ARM_ARCH__ < 6
340 #error "SMP is not supported on this platform"
344 * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
347 #define cmpxchg_local(ptr, o, n) \
348 ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
349 (unsigned long)(n), sizeof(*(ptr))))
350 #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
353 #include <asm-generic/cmpxchg.h>
356 #else /* __LINUX_ARM_ARCH__ >= 6 */
358 extern void __bad_cmpxchg(volatile void *ptr, int size);
361 * cmpxchg only support 32-bits operands on ARMv6.
364 static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
365 unsigned long new, int size)
367 unsigned long oldval, res;
370 #ifdef CONFIG_CPU_32v6K
373 asm volatile("@ __cmpxchg1\n"
377 " strexbeq %0, %4, [%2]\n"
378 : "=&r" (res), "=&r" (oldval)
379 : "r" (ptr), "Ir" (old), "r" (new)
385 asm volatile("@ __cmpxchg1\n"
389 " strexheq %0, %4, [%2]\n"
390 : "=&r" (res), "=&r" (oldval)
391 : "r" (ptr), "Ir" (old), "r" (new)
395 #endif /* CONFIG_CPU_32v6K */
398 asm volatile("@ __cmpxchg4\n"
402 " strexeq %0, %4, [%2]\n"
403 : "=&r" (res), "=&r" (oldval)
404 : "r" (ptr), "Ir" (old), "r" (new)
409 __bad_cmpxchg(ptr, size);
416 static inline unsigned long __cmpxchg_mb(volatile void *ptr, unsigned long old,
417 unsigned long new, int size)
422 ret = __cmpxchg(ptr, old, new, size);
428 #define cmpxchg(ptr,o,n) \
429 ((__typeof__(*(ptr)))__cmpxchg_mb((ptr), \
430 (unsigned long)(o), \
431 (unsigned long)(n), \
434 static inline unsigned long __cmpxchg_local(volatile void *ptr,
436 unsigned long new, int size)
441 #ifndef CONFIG_CPU_32v6K
444 ret = __cmpxchg_local_generic(ptr, old, new, size);
446 #endif /* !CONFIG_CPU_32v6K */
448 ret = __cmpxchg(ptr, old, new, size);
454 #define cmpxchg_local(ptr,o,n) \
455 ((__typeof__(*(ptr)))__cmpxchg_local((ptr), \
456 (unsigned long)(o), \
457 (unsigned long)(n), \
460 #ifdef CONFIG_CPU_32v6K
463 * Note : ARMv7-M (currently unsupported by Linux) does not support
464 * ldrexd/strexd. If ARMv7-M is ever supported by the Linux kernel, it should
465 * not be allowed to use __cmpxchg64.
467 static inline unsigned long long __cmpxchg64(volatile void *ptr,
468 unsigned long long old,
469 unsigned long long new)
471 register unsigned long long oldval asm("r0");
472 register unsigned long long __old asm("r2") = old;
473 register unsigned long long __new asm("r4") = new;
479 " ldrexd %1, %H1, [%2]\n"
483 " strexdeq %0, %4, %H4, [%2]\n"
484 : "=&r" (res), "=&r" (oldval)
485 : "r" (ptr), "Ir" (__old), "r" (__new)
492 static inline unsigned long long __cmpxchg64_mb(volatile void *ptr,
493 unsigned long long old,
494 unsigned long long new)
496 unsigned long long ret;
499 ret = __cmpxchg64(ptr, old, new);
505 #define cmpxchg64(ptr,o,n) \
506 ((__typeof__(*(ptr)))__cmpxchg64_mb((ptr), \
507 (unsigned long long)(o), \
508 (unsigned long long)(n)))
510 #define cmpxchg64_local(ptr,o,n) \
511 ((__typeof__(*(ptr)))__cmpxchg64((ptr), \
512 (unsigned long long)(o), \
513 (unsigned long long)(n)))
515 #else /* !CONFIG_CPU_32v6K */
517 #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
519 #endif /* CONFIG_CPU_32v6K */
521 #endif /* __LINUX_ARM_ARCH__ >= 6 */
523 #endif /* __ASSEMBLY__ */
525 #define arch_align_stack(x) (x)
527 #endif /* __KERNEL__ */