5 #include <asm-generic/pci-dma-compat.h>
7 #include <mach/hardware.h> /* for PCIBIOS_MIN_* */
9 #ifdef CONFIG_PCI_HOST_ITE8152
10 /* ITE bridge requires setting latency timer to avoid early bus access
11 termination by PIC bus mater devices
13 extern void pcibios_set_master(struct pci_dev *dev);
15 static inline void pcibios_set_master(struct pci_dev *dev)
17 /* No special bus mastering setup handling */
21 static inline void pcibios_penalize_isa_irq(int irq, int active)
23 /* We don't do dynamic PCI IRQ allocation */
27 * The PCI address space does equal the physical memory address space.
28 * The networking and block device layers use this boolean for bounce
31 #define PCI_DMA_BUS_IS_PHYS (1)
34 static inline void pci_dma_burst_advice(struct pci_dev *pdev,
35 enum pci_dma_burst_strategy *strat,
36 unsigned long *strategy_parameter)
38 *strat = PCI_DMA_BURST_INFINITY;
39 *strategy_parameter = ~0UL;
44 extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
45 enum pci_mmap_state mmap_state, int write_combine);
48 pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
49 struct resource *res);
52 pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
53 struct pci_bus_region *region);
56 * Dummy implementation; always return 0.
58 static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
63 #endif /* __KERNEL__ */