3 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #ifndef __ASM_ARCH_MX31_REGS_H
25 #define __ASM_ARCH_MX31_REGS_H
27 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
28 #include <asm/types.h>
30 /* Clock control module registers */
31 struct clock_control_regs {
68 /* Bit definitions for RCSR register in CCM */
69 #define CCM_RCSR_NF16B (1 << 31)
70 #define CCM_RCSR_NFMS (1 << 30)
74 #define __REG(x) (*((volatile u32 *)(x)))
75 #define __REG16(x) (*((volatile u16 *)(x)))
76 #define __REG8(x) (*((volatile u8 *)(x)))
78 #define CCM_BASE 0x53f80000
79 #define CCM_CCMR (CCM_BASE + 0x00)
80 #define CCM_PDR0 (CCM_BASE + 0x04)
81 #define CCM_PDR1 (CCM_BASE + 0x08)
82 #define CCM_RCSR (CCM_BASE + 0x0c)
83 #define CCM_MPCTL (CCM_BASE + 0x10)
84 #define CCM_UPCTL (CCM_BASE + 0x14)
85 #define CCM_SPCTL (CCM_BASE + 0x18)
86 #define CCM_COSR (CCM_BASE + 0x1C)
87 #define CCM_CGR0 (CCM_BASE + 0x20)
88 #define CCM_CGR1 (CCM_BASE + 0x24)
89 #define CCM_CGR2 (CCM_BASE + 0x28)
91 #define CCMR_MDS (1 << 7)
92 #define CCMR_SBYCS (1 << 4)
93 #define CCMR_MPE (1 << 3)
94 #define CCMR_PRCS_MASK (3 << 1)
95 #define CCMR_FPM (1 << 1)
96 #define CCMR_CKIH (2 << 1)
98 #define PDR0_CSI_PODF(x) (((x) & 0x1ff) << 23)
99 #define PDR0_PER_PODF(x) (((x) & 0x1f) << 16)
100 #define PDR0_HSP_PODF(x) (((x) & 0x7) << 11)
101 #define PDR0_NFC_PODF(x) (((x) & 0x7) << 8)
102 #define PDR0_IPG_PODF(x) (((x) & 0x3) << 6)
103 #define PDR0_MAX_PODF(x) (((x) & 0x7) << 3)
104 #define PDR0_MCU_PODF(x) ((x) & 0x7)
106 #define PLL_PD(x) (((x) & 0xf) << 26)
107 #define PLL_MFD(x) (((x) & 0x3ff) << 16)
108 #define PLL_MFI(x) (((x) & 0xf) << 10)
109 #define PLL_MFN(x) (((x) & 0x3ff) << 0)
111 #define WEIM_ESDCTL0 0xB8001000
112 #define WEIM_ESDCFG0 0xB8001004
113 #define WEIM_ESDCTL1 0xB8001008
114 #define WEIM_ESDCFG1 0xB800100C
115 #define WEIM_ESDMISC 0xB8001010
117 #define ESDCTL_SDE (1 << 31)
118 #define ESDCTL_CMD_RW (0 << 28)
119 #define ESDCTL_CMD_PRECHARGE (1 << 28)
120 #define ESDCTL_CMD_AUTOREFRESH (2 << 28)
121 #define ESDCTL_CMD_LOADMODEREG (3 << 28)
122 #define ESDCTL_CMD_MANUALREFRESH (4 << 28)
123 #define ESDCTL_ROW_13 (2 << 24)
124 #define ESDCTL_ROW(x) ((x) << 24)
125 #define ESDCTL_COL_9 (1 << 20)
126 #define ESDCTL_COL(x) ((x) << 20)
127 #define ESDCTL_DSIZ(x) ((x) << 16)
128 #define ESDCTL_SREFR(x) ((x) << 13)
129 #define ESDCTL_PWDT(x) ((x) << 10)
130 #define ESDCTL_FP(x) ((x) << 8)
131 #define ESDCTL_BL(x) ((x) << 7)
132 #define ESDCTL_PRCT(x) ((x) << 0)
134 #define WEIM_BASE 0xb8002000
135 #define CSCR_U(x) (WEIM_BASE + (x) * 0x10)
136 #define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10)
137 #define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10)
139 #define IOMUXC_BASE 0x43FAC000
140 #define IOMUXC_GPR (IOMUXC_BASE + 0x8)
141 #define IOMUXC_SW_MUX_CTL(x) (IOMUXC_BASE + 0xc + (x) * 4)
142 #define IOMUXC_SW_PAD_CTL(x) (IOMUXC_BASE + 0x154 + (x) * 4)
144 #define IPU_BASE 0x53fc0000
145 #define IPU_CONF IPU_BASE
147 #define IPU_CONF_PXL_ENDIAN (1<<8)
148 #define IPU_CONF_DU_EN (1<<7)
149 #define IPU_CONF_DI_EN (1<<6)
150 #define IPU_CONF_ADC_EN (1<<5)
151 #define IPU_CONF_SDC_EN (1<<4)
152 #define IPU_CONF_PF_EN (1<<3)
153 #define IPU_CONF_ROT_EN (1<<2)
154 #define IPU_CONF_IC_EN (1<<1)
155 #define IPU_CONF_SCI_EN (1<<0)
157 #define ARM_PPMRR 0x40000015
159 #define WDOG_BASE 0x53FDC000
164 #define GPIO1_BASE_ADDR 0x53FCC000
165 #define GPIO2_BASE_ADDR 0x53FD0000
166 #define GPIO3_BASE_ADDR 0x53FA4000
167 #define GPIO_DR 0x00000000 /* data register */
168 #define GPIO_GDIR 0x00000004 /* direction register */
169 #define GPIO_PSR 0x00000008 /* pad status register */
172 * Signal Multiplexing (IOMUX)
175 /* bits in the SW_MUX_CTL registers */
176 #define MUX_CTL_OUT_GPIO_DR (0 << 4)
177 #define MUX_CTL_OUT_FUNC (1 << 4)
178 #define MUX_CTL_OUT_ALT1 (2 << 4)
179 #define MUX_CTL_OUT_ALT2 (3 << 4)
180 #define MUX_CTL_OUT_ALT3 (4 << 4)
181 #define MUX_CTL_OUT_ALT4 (5 << 4)
182 #define MUX_CTL_OUT_ALT5 (6 << 4)
183 #define MUX_CTL_OUT_ALT6 (7 << 4)
184 #define MUX_CTL_IN_NONE (0 << 0)
185 #define MUX_CTL_IN_GPIO (1 << 0)
186 #define MUX_CTL_IN_FUNC (2 << 0)
187 #define MUX_CTL_IN_ALT1 (4 << 0)
188 #define MUX_CTL_IN_ALT2 (8 << 0)
190 #define MUX_CTL_FUNC (MUX_CTL_OUT_FUNC | MUX_CTL_IN_FUNC)
191 #define MUX_CTL_ALT1 (MUX_CTL_OUT_ALT1 | MUX_CTL_IN_ALT1)
192 #define MUX_CTL_ALT2 (MUX_CTL_OUT_ALT2 | MUX_CTL_IN_ALT2)
193 #define MUX_CTL_GPIO (MUX_CTL_OUT_GPIO_DR | MUX_CTL_IN_GPIO)
195 /* Register offsets based on IOMUXC_BASE */
197 #define MUX_CTL_RTS1 0x7c
198 #define MUX_CTL_CTS1 0x7d
199 #define MUX_CTL_DTR_DCE1 0x7e
200 #define MUX_CTL_DSR_DCE1 0x7f
201 #define MUX_CTL_CSPI2_SCLK 0x80
202 #define MUX_CTL_CSPI2_SPI_RDY 0x81
203 #define MUX_CTL_RXD1 0x82
204 #define MUX_CTL_TXD1 0x83
205 #define MUX_CTL_CSPI2_MISO 0x84
206 #define MUX_CTL_CSPI2_SS0 0x85
207 #define MUX_CTL_CSPI2_SS1 0x86
208 #define MUX_CTL_CSPI2_SS2 0x87
209 #define MUX_CTL_CSPI1_SS2 0x88
210 #define MUX_CTL_CSPI1_SCLK 0x89
211 #define MUX_CTL_CSPI1_SPI_RDY 0x8a
212 #define MUX_CTL_CSPI2_MOSI 0x8b
213 #define MUX_CTL_CSPI1_MOSI 0x8c
214 #define MUX_CTL_CSPI1_MISO 0x8d
215 #define MUX_CTL_CSPI1_SS0 0x8e
216 #define MUX_CTL_CSPI1_SS1 0x8f
218 #define MUX_CTL_NFC_WP 0xD0
219 #define MUX_CTL_NFC_CE 0xD1
220 #define MUX_CTL_NFC_RB 0xD2
221 #define MUX_CTL_NFC_WE 0xD4
222 #define MUX_CTL_NFC_RE 0xD5
223 #define MUX_CTL_NFC_ALE 0xD6
224 #define MUX_CTL_NFC_CLE 0xD7
228 * Helper macros for the MUX_[contact name]__[pin function] macros
230 #define IOMUX_MODE_POS 9
231 #define IOMUX_MODE(contact, mode) (((mode) << IOMUX_MODE_POS) | (contact))
234 * These macros can be used in mx31_gpio_mux() and have the form
235 * MUX_[contact name]__[pin function]
237 #define MUX_RXD1__UART1_RXD_MUX IOMUX_MODE(MUX_CTL_RXD1, MUX_CTL_FUNC)
238 #define MUX_TXD1__UART1_TXD_MUX IOMUX_MODE(MUX_CTL_TXD1, MUX_CTL_FUNC)
239 #define MUX_RTS1__UART1_RTS_B IOMUX_MODE(MUX_CTL_RTS1, MUX_CTL_FUNC)
240 #define MUX_CTS1__UART1_CTS_B IOMUX_MODE(MUX_CTL_CTS1, MUX_CTL_FUNC)
242 #define MUX_CSPI2_SS0__CSPI2_SS0_B IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_FUNC)
243 #define MUX_CSPI2_SS1__CSPI2_SS1_B IOMUX_MODE(MUX_CTL_CSPI2_SS1, MUX_CTL_FUNC)
244 #define MUX_CSPI2_SS2__CSPI2_SS2_B IOMUX_MODE(MUX_CTL_CSPI2_SS2, MUX_CTL_FUNC)
245 #define MUX_CSPI2_MOSI__CSPI2_MOSI IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_FUNC)
246 #define MUX_CSPI2_MISO__CSPI2_MISO IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_FUNC)
247 #define MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B \
248 IOMUX_MODE(MUX_CTL_CSPI2_SPI_RDY, MUX_CTL_FUNC)
249 #define MUX_CSPI2_SCLK__CSPI2_CLK IOMUX_MODE(MUX_CTL_CSPI2_SCLK, MUX_CTL_FUNC)
251 #define MUX_CSPI1_SS0__CSPI1_SS0_B IOMUX_MODE(MUX_CTL_CSPI1_SS0, MUX_CTL_FUNC)
252 #define MUX_CSPI1_SS1__CSPI1_SS1_B IOMUX_MODE(MUX_CTL_CSPI1_SS1, MUX_CTL_FUNC)
253 #define MUX_CSPI1_SS2__CSPI1_SS2_B IOMUX_MODE(MUX_CTL_CSPI1_SS2, MUX_CTL_FUNC)
254 #define MUX_CSPI1_MOSI__CSPI1_MOSI IOMUX_MODE(MUX_CTL_CSPI1_MOSI, MUX_CTL_FUNC)
255 #define MUX_CSPI1_MISO__CSPI1_MISO IOMUX_MODE(MUX_CTL_CSPI1_MISO, MUX_CTL_FUNC)
256 #define MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B \
257 IOMUX_MODE(MUX_CTL_CSPI1_SPI_RDY, MUX_CTL_FUNC)
258 #define MUX_CSPI1_SCLK__CSPI1_CLK IOMUX_MODE(MUX_CTL_CSPI1_SCLK, MUX_CTL_FUNC)
260 #define MUX_CSPI2_MOSI__I2C2_SCL IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_ALT1)
261 #define MUX_CSPI2_MISO__I2C2_SDA IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_ALT1)
263 /* PAD control registers for SDR/DDR */
264 #define IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B (IOMUXC_BASE + 0x26C)
265 #define IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0 (IOMUXC_BASE + 0x270)
266 #define IOMUXC_SW_PAD_CTL_BCLK_RW_RAS (IOMUXC_BASE + 0x274)
267 #define IOMUXC_SW_PAD_CTL_CS5_ECB_LBA (IOMUXC_BASE + 0x278)
268 #define IOMUXC_SW_PAD_CTL_CS2_CS3_CS4 (IOMUXC_BASE + 0x27C)
269 #define IOMUXC_SW_PAD_CTL_OE_CS0_CS1 (IOMUXC_BASE + 0x280)
270 #define IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1 (IOMUXC_BASE + 0x284)
271 #define IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2 (IOMUXC_BASE + 0x288)
272 #define IOMUXC_SW_PAD_CTL_SD29_SD30_SD31 (IOMUXC_BASE + 0x28C)
273 #define IOMUXC_SW_PAD_CTL_SD26_SD27_SD28 (IOMUXC_BASE + 0x290)
274 #define IOMUXC_SW_PAD_CTL_SD23_SD24_SD25 (IOMUXC_BASE + 0x294)
275 #define IOMUXC_SW_PAD_CTL_SD20_SD21_SD22 (IOMUXC_BASE + 0x298)
276 #define IOMUXC_SW_PAD_CTL_SD17_SD18_SD19 (IOMUXC_BASE + 0x29C)
277 #define IOMUXC_SW_PAD_CTL_SD14_SD15_SD16 (IOMUXC_BASE + 0x2A0)
278 #define IOMUXC_SW_PAD_CTL_SD11_SD12_SD13 (IOMUXC_BASE + 0x2A4)
279 #define IOMUXC_SW_PAD_CTL_SD8_SD9_SD10 (IOMUXC_BASE + 0x2A8)
280 #define IOMUXC_SW_PAD_CTL_SD5_SD6_SD7 (IOMUXC_BASE + 0x2AC)
281 #define IOMUXC_SW_PAD_CTL_SD2_SD3_SD4 (IOMUXC_BASE + 0x2B0)
282 #define IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1 (IOMUXC_BASE + 0x2B4)
283 #define IOMUXC_SW_PAD_CTL_A24_A25_SDBA1 (IOMUXC_BASE + 0x2B8)
284 #define IOMUXC_SW_PAD_CTL_A21_A22_A23 (IOMUXC_BASE + 0x2BC)
285 #define IOMUXC_SW_PAD_CTL_A18_A19_A20 (IOMUXC_BASE + 0x2C0)
286 #define IOMUXC_SW_PAD_CTL_A15_A16_A17 (IOMUXC_BASE + 0x2C4)
287 #define IOMUXC_SW_PAD_CTL_A12_A13_A14 (IOMUXC_BASE + 0x2C8)
288 #define IOMUXC_SW_PAD_CTL_A10_MA10_A11 (IOMUXC_BASE + 0x2CC)
289 #define IOMUXC_SW_PAD_CTL_A7_A8_A9 (IOMUXC_BASE + 0x2D0)
290 #define IOMUXC_SW_PAD_CTL_A4_A5_A6 (IOMUXC_BASE + 0x2D4)
291 #define IOMUXC_SW_PAD_CTL_A1_A2_A3 (IOMUXC_BASE + 0x2D8)
292 #define IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0 (IOMUXC_BASE + 0x2DC)
295 * Memory regions and CS
297 #define IPU_MEM_BASE 0x70000000
298 #define CSD0_BASE 0x80000000
299 #define CSD1_BASE 0x90000000
300 #define CS0_BASE 0xA0000000
301 #define CS1_BASE 0xA8000000
302 #define CS2_BASE 0xB0000000
303 #define CS3_BASE 0xB2000000
304 #define CS4_BASE 0xB4000000
305 #define CS4_PSRAM_BASE 0xB5000000
306 #define CS5_BASE 0xB6000000
307 #define PCMCIA_MEM_BASE 0xC0000000
312 #define NFC_BASE_ADDR 0xB8000000
315 * Internal RAM (16KB)
317 #define IRAM_BASE_ADDR 0x1FFFC000
318 #define IRAM_SIZE (16 * 1024)
320 #endif /* __ASM_ARCH_MX31_REGS_H */