arch/arm/dts/rk3588s-u-boot.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
   4  */
   5
   6 #include "rockchip-u-boot.dtsi"
   7
   8 / {
   9         aliases {
  10                 spi5 = &sfc;
  11         };
  12
  13         dmc {
  14                 compatible = "rockchip,rk3588-dmc";
  15                 bootph-all;
  16                 status = "okay";
  17         };
  18
  19         usb_host0_xhci: usb@fc000000 {
  20                 compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
  21                 reg = <0x0 0xfc000000 0x0 0x400000>;
  22                 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
  23                 clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,
  24                          <&cru ACLK_USB3OTG0>;
  25                 clock-names = "ref_clk", "suspend_clk", "bus_clk";
  26                 dr_mode = "otg";
  27                 phys = <&u2phy0_otg>, <&usbdp_phy0_u3>;
  28                 phy-names = "usb2-phy", "usb3-phy";
  29                 phy_type = "utmi_wide";
  30                 power-domains = <&power RK3588_PD_USB>;
  31                 resets = <&cru SRST_A_USB3OTG0>;
  32                 snps,dis_enblslpm_quirk;
  33                 snps,dis-u1-entry-quirk;
  34                 snps,dis-u2-entry-quirk;
  35                 snps,dis-u2-freeclk-exists-quirk;
  36                 snps,dis-del-phy-power-chg-quirk;
  37                 snps,dis-tx-ipgap-linecheck-quirk;
  38                 status = "disabled";
  39         };
  40
  41         usbdpphy0_grf: syscon@fd5c8000 {
  42                 compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
  43                 reg = <0x0 0xfd5c8000 0x0 0x4000>;
  44         };
  45
  46         usb2phy0_grf: syscon@fd5d0000 {
  47                 compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
  48                              "simple-mfd";
  49                 reg = <0x0 0xfd5d0000 0x0 0x4000>;
  50                 #address-cells = <1>;
  51                 #size-cells = <1>;
  52
  53                 u2phy0: usb2-phy@0 {
  54                         compatible = "rockchip,rk3588-usb2phy";
  55                         reg = <0x0 0x10>;
  56                         interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>;
  57                         resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>;
  58                         reset-names = "phy", "apb";
  59                         clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
  60                         clock-names = "phyclk";
  61                         clock-output-names = "usb480m_phy0";
  62                         #clock-cells = <0>;
  63                         status = "disabled";
  64
  65                         u2phy0_otg: otg-port {
  66                                 #phy-cells = <0>;
  67                                 status = "disabled";
  68                         };
  69                 };
  70         };
  71
  72         vo0_grf: syscon@fd5a6000 {
  73                 compatible = "rockchip,rk3588-vo-grf", "syscon";
  74                 reg = <0x0 0xfd5a6000 0x0 0x2000>;
  75                 clocks = <&cru PCLK_VO0GRF>;
  76         };
  77
  78         usb_grf: syscon@fd5ac000 {
  79                 compatible = "rockchip,rk3588-usb-grf", "syscon";
  80                 reg = <0x0 0xfd5ac000 0x0 0x4000>;
  81         };
  82
  83         usbdpphy0_grf: syscon@fd5c8000 {
  84                 compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
  85                 reg = <0x0 0xfd5c8000 0x0 0x4000>;
  86         };
  87
  88         rng: rng@fe378000 {
  89                 compatible = "rockchip,trngv1";
  90                 reg = <0x0 0xfe378000 0x0 0x200>;
  91                 status = "disabled";
  92         };
  93
  94         usbdp_phy0: phy@fed80000 {
  95                 compatible = "rockchip,rk3588-usbdp-phy";
  96                 reg = <0x0 0xfed80000 0x0 0x10000>;
  97                 rockchip,u2phy-grf = <&usb2phy0_grf>;
  98                 rockchip,usb-grf = <&usb_grf>;
  99                 rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
 100                 rockchip,vo-grf = <&vo0_grf>;
 101                 clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
 102                          <&cru CLK_USBDP_PHY0_IMMORTAL>,
 103                          <&cru PCLK_USBDPPHY0>,
 104                          <&u2phy0>;
 105                 clock-names = "refclk", "immortal", "pclk", "utmi";
 106                 resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
 107                          <&cru SRST_USBDP_COMBO_PHY0_CMN>,
 108                          <&cru SRST_USBDP_COMBO_PHY0_LANE>,
 109                          <&cru SRST_USBDP_COMBO_PHY0_PCS>,
 110                          <&cru SRST_P_USBDPPHY0>;
 111                 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
 112                 status = "disabled";
 113
 114                 usbdp_phy0_dp: dp-port {
 115                         #phy-cells = <0>;
 116                         status = "disabled";
 117                 };
 118
 119                 usbdp_phy0_u3: usb3-port {
 120                         #phy-cells = <0>;
 121                         status = "disabled";
 122                 };
 123         };
 124 };
 125
 126 &emmc_bus8 {
 127         bootph-all;
 128 };
 129
 130 &emmc_clk {
 131         bootph-all;
 132 };
 133
 134 &emmc_cmd {
 135         bootph-all;
 136 };
 137
 138 &emmc_data_strobe {
 139         bootph-all;
 140 };
 141
 142 &emmc_rstnout {
 143         bootph-all;
 144 };
 145
 146 &pinctrl {
 147         bootph-all;
 148 };
 149
 150 &pcfg_pull_none {
 151         bootph-all;
 152 };
 153
 154 &pcfg_pull_up_drv_level_2 {
 155         bootph-all;
 156 };
 157
 158 &pcfg_pull_up {
 159         bootph-all;
 160 };
 161
 162 &xin24m {
 163         bootph-all;
 164         status = "okay";
 165 };
 166
 167 &cru {
 168         bootph-pre-ram;
 169         status = "okay";
 170 };
 171
 172 &sys_grf {
 173         bootph-pre-ram;
 174         status = "okay";
 175 };
 176
 177 &pmu1grf {
 178         bootph-all;
 179 };
 180
 181 &scmi {
 182         bootph-pre-ram;
 183 };
 184
 185 &scmi_clk {
 186         bootph-pre-ram;
 187 };
 188
 189 &sdmmc {
 190         bootph-pre-ram;
 191         u-boot,spl-fifo-mode;
 192 };
 193
 194 &sdhci {
 195         bootph-pre-ram;
 196         u-boot,spl-fifo-mode;
 197 };
 198
 199 &sdmmc_bus4 {
 200         bootph-all;
 201 };
 202
 203 &sdmmc_clk {
 204         bootph-all;
 205 };
 206
 207 &sdmmc_cmd {
 208         bootph-all;
 209 };
 210
 211 &sdmmc_det {
 212         bootph-all;
 213 };
 214
 215 &uart2 {
 216         clock-frequency = <24000000>;
 217         bootph-pre-ram;
 218         status = "okay";
 219 };
 220
 221 &uart2m0_xfer {
 222         bootph-all;
 223 };
 224
 225 &ioc {
 226         bootph-pre-ram;
 227 };
 228
 229 #ifdef CONFIG_ROCKCHIP_SPI_IMAGE
 230 &binman {
 231         simple-bin-spi {
 232                 mkimage {
 233                         args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
 234                         offset = <0x8000>;
 235                 };
 236         };
 237 };
 238 #endif