arch/arm/dts/rk3568-rock-3a-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2021 Rockchip Electronics Co., Ltd
   4  * (C) Copyright 2023 Akash Gajjar <gajjar04akash@gmail.com>
   5  */
   6
   7 #include "rk356x-u-boot.dtsi"
   8
   9 &pcie3x2 {
  10         pinctrl-0 = <&pcie3x2_reset_h>;
  11 };
  12
  13 &pinctrl {
  14         pcie {
  15                 pcie3x2_reset_h: pcie3x2-reset-h {
  16                         rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
  17                 };
  18         };
  19 };
  20
  21 &sdhci {
  22         cap-mmc-highspeed;
  23         mmc-ddr-1_8v;
  24         mmc-hs200-1_8v;
  25         mmc-hs400-1_8v;
  26         mmc-hs400-enhanced-strobe;
  27 };
  28
  29 &sfc {
  30         bootph-pre-ram;
  31         u-boot,spl-sfc-no-dma;
  32         #address-cells = <1>;
  33         #size-cells = <0>;
  34         status = "okay";
  35
  36         flash@0 {
  37                 bootph-pre-ram;
  38                 compatible = "jedec,spi-nor";
  39                 reg = <0>;
  40                 spi-max-frequency = <24000000>;
  41                 spi-rx-bus-width = <4>;
  42                 spi-tx-bus-width = <1>;
  43         };
  44 };