arch/arm/dts/rk3368.dtsi

   1 /*
   2  * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3368-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/thermal/thermal.h>
  49 #include <dt-bindings/memory/rk3368-dmc.h>
  50
  51 / {
  52         compatible = "rockchip,rk3368";
  53         interrupt-parent = <&gic>;
  54         #address-cells = <2>;
  55         #size-cells = <2>;
  56
  57         aliases {
  58                 ethernet0 = &gmac;
  59                 i2c0 = &i2c0;
  60                 i2c1 = &i2c1;
  61                 i2c2 = &i2c2;
  62                 i2c3 = &i2c3;
  63                 i2c4 = &i2c4;
  64                 i2c5 = &i2c5;
  65                 serial0 = &uart0;
  66                 serial1 = &uart1;
  67                 serial2 = &uart2;
  68                 serial3 = &uart3;
  69                 serial4 = &uart4;
  70                 spi0 = &spi0;
  71                 spi1 = &spi1;
  72                 spi2 = &spi2;
  73         };
  74
  75         cpus {
  76                 #address-cells = <0x2>;
  77                 #size-cells = <0x0>;
  78
  79                 cpu-map {
  80                         cluster0 {
  81                                 core0 {
  82                                         cpu = <&cpu_b0>;
  83                                 };
  84                                 core1 {
  85                                         cpu = <&cpu_b1>;
  86                                 };
  87                                 core2 {
  88                                         cpu = <&cpu_b2>;
  89                                 };
  90                                 core3 {
  91                                         cpu = <&cpu_b3>;
  92                                 };
  93                         };
  94
  95                         cluster1 {
  96                                 core0 {
  97                                         cpu = <&cpu_l0>;
  98                                 };
  99                                 core1 {
 100                                         cpu = <&cpu_l1>;
 101                                 };
 102                                 core2 {
 103                                         cpu = <&cpu_l2>;
 104                                 };
 105                                 core3 {
 106                                         cpu = <&cpu_l3>;
 107                                 };
 108                         };
 109                 };
 110
 111                 idle-states {
 112                         entry-method = "psci";
 113
 114                         cpu_sleep: cpu-sleep-0 {
 115                                 compatible = "arm,idle-state";
 116                                 arm,psci-suspend-param = <0x1010000>;
 117                                 entry-latency-us = <0x3fffffff>;
 118                                 exit-latency-us = <0x40000000>;
 119                                 min-residency-us = <0xffffffff>;
 120                         };
 121                 };
 122
 123                 cpu_l0: cpu@0 {
 124                         device_type = "cpu";
 125                         compatible = "arm,cortex-a53", "arm,armv8";
 126                         reg = <0x0 0x0>;
 127                         cpu-idle-states = <&cpu_sleep>;
 128                         enable-method = "psci";
 129
 130                         #cooling-cells = <2>; /* min followed by max */
 131                 };
 132
 133                 cpu_l1: cpu@1 {
 134                         device_type = "cpu";
 135                         compatible = "arm,cortex-a53", "arm,armv8";
 136                         reg = <0x0 0x1>;
 137                         cpu-idle-states = <&cpu_sleep>;
 138                         enable-method = "psci";
 139                 };
 140
 141                 cpu_l2: cpu@2 {
 142                         device_type = "cpu";
 143                         compatible = "arm,cortex-a53", "arm,armv8";
 144                         reg = <0x0 0x2>;
 145                         cpu-idle-states = <&cpu_sleep>;
 146                         enable-method = "psci";
 147                 };
 148
 149                 cpu_l3: cpu@3 {
 150                         device_type = "cpu";
 151                         compatible = "arm,cortex-a53", "arm,armv8";
 152                         reg = <0x0 0x3>;
 153                         cpu-idle-states = <&cpu_sleep>;
 154                         enable-method = "psci";
 155                 };
 156
 157                 cpu_b0: cpu@100 {
 158                         device_type = "cpu";
 159                         compatible = "arm,cortex-a53", "arm,armv8";
 160                         reg = <0x0 0x100>;
 161                         cpu-idle-states = <&cpu_sleep>;
 162                         enable-method = "psci";
 163
 164                         #cooling-cells = <2>; /* min followed by max */
 165                 };
 166
 167                 cpu_b1: cpu@101 {
 168                         device_type = "cpu";
 169                         compatible = "arm,cortex-a53", "arm,armv8";
 170                         reg = <0x0 0x101>;
 171                         cpu-idle-states = <&cpu_sleep>;
 172                         enable-method = "psci";
 173                 };
 174
 175                 cpu_b2: cpu@102 {
 176                         device_type = "cpu";
 177                         compatible = "arm,cortex-a53", "arm,armv8";
 178                         reg = <0x0 0x102>;
 179                         cpu-idle-states = <&cpu_sleep>;
 180                         enable-method = "psci";
 181                 };
 182
 183                 cpu_b3: cpu@103 {
 184                         device_type = "cpu";
 185                         compatible = "arm,cortex-a53", "arm,armv8";
 186                         reg = <0x0 0x103>;
 187                         cpu-idle-states = <&cpu_sleep>;
 188                         enable-method = "psci";
 189                 };
 190         };
 191
 192         arm-pmu {
 193                 compatible = "arm,armv8-pmuv3";
 194                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 195                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 196                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 197                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 198                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 199                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 200                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 201                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 202                 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
 203                                      <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
 204                                      <&cpu_b2>, <&cpu_b3>;
 205         };
 206
 207         psci {
 208                 compatible = "arm,psci-0.2";
 209                 method = "smc";
 210         };
 211
 212         timer {
 213                 compatible = "arm,armv8-timer";
 214                 interrupts = <GIC_PPI 13
 215                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 216                              <GIC_PPI 14
 217                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 218                              <GIC_PPI 11
 219                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 220                              <GIC_PPI 10
 221                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 222         };
 223
 224         xin24m: oscillator {
 225                 compatible = "fixed-clock";
 226                 clock-frequency = <24000000>;
 227                 clock-output-names = "xin24m";
 228                 #clock-cells = <0>;
 229         };
 230
 231         dmc: dmc@ff610000 {
 232                 compatible = "rockchip,rk3368-dmc", "syscon";
 233                 rockchip,cru = <&cru>;
 234                 rockchip,grf = <&grf>;
 235                 rockchip,msch = <&service_msch>;
 236                 reg = <0 0xff610000 0 0x400
 237                        0 0xff620000 0 0x400>;
 238         };
 239
 240         service_msch: syscon@ffac0000 {
 241                 u-boot,dm-pre-reloc;
 242                 compatible = "rockchip,rk3368-msch", "syscon";
 243                 reg = <0x0 0xffac0000 0x0 0x2000>;
 244                 status = "okay";
 245         };
 246
 247         sdmmc: dwmmc@ff0c0000 {
 248                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 249                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 250                 clock-freq-min-max = <400000 150000000>;
 251                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 252                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 253                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 254                 fifo-depth = <0x100>;
 255                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 256                 status = "disabled";
 257         };
 258
 259         sdio0: dwmmc@ff0d0000 {
 260                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 261                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 262                 clock-freq-min-max = <400000 150000000>;
 263                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 264                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 265                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 266                 fifo-depth = <0x100>;
 267                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 268                 status = "disabled";
 269         };
 270
 271         emmc: dwmmc@ff0f0000 {
 272                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 273                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 274                 clock-freq-min-max = <400000 150000000>;
 275                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 276                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 277                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 278                 fifo-depth = <0x100>;
 279                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 280                 status = "disabled";
 281         };
 282
 283         saradc: saradc@ff100000 {
 284                 compatible = "rockchip,saradc";
 285                 reg = <0x0 0xff100000 0x0 0x100>;
 286                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 287                 #io-channel-cells = <1>;
 288                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 289                 clock-names = "saradc", "apb_pclk";
 290                 status = "disabled";
 291         };
 292
 293         spi0: spi@ff110000 {
 294                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 295                 reg = <0x0 0xff110000 0x0 0x1000>;
 296                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 297                 clock-names = "spiclk", "apb_pclk";
 298                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 299                 pinctrl-names = "default";
 300                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 301                 #address-cells = <1>;
 302                 #size-cells = <0>;
 303                 status = "disabled";
 304         };
 305
 306         spi1: spi@ff120000 {
 307                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 308                 reg = <0x0 0xff120000 0x0 0x1000>;
 309                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 310                 clock-names = "spiclk", "apb_pclk";
 311                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 312                 pinctrl-names = "default";
 313                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 314                 #address-cells = <1>;
 315                 #size-cells = <0>;
 316                 status = "disabled";
 317         };
 318
 319         spi2: spi@ff130000 {
 320                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 321                 reg = <0x0 0xff130000 0x0 0x1000>;
 322                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 323                 clock-names = "spiclk", "apb_pclk";
 324                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 325                 pinctrl-names = "default";
 326                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 327                 #address-cells = <1>;
 328                 #size-cells = <0>;
 329                 status = "disabled";
 330         };
 331
 332         i2c1: i2c@ff140000 {
 333                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 334                 reg = <0x0 0xff140000 0x0 0x1000>;
 335                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 336                 #address-cells = <1>;
 337                 #size-cells = <0>;
 338                 clock-names = "i2c";
 339                 clocks = <&cru PCLK_I2C1>;
 340                 pinctrl-names = "default";
 341                 pinctrl-0 = <&i2c1_xfer>;
 342                 status = "disabled";
 343         };
 344
 345         i2c3: i2c@ff150000 {
 346                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 347                 reg = <0x0 0xff150000 0x0 0x1000>;
 348                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 349                 #address-cells = <1>;
 350                 #size-cells = <0>;
 351                 clock-names = "i2c";
 352                 clocks = <&cru PCLK_I2C3>;
 353                 pinctrl-names = "default";
 354                 pinctrl-0 = <&i2c3_xfer>;
 355                 status = "disabled";
 356         };
 357
 358         i2c4: i2c@ff160000 {
 359                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 360                 reg = <0x0 0xff160000 0x0 0x1000>;
 361                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 362                 #address-cells = <1>;
 363                 #size-cells = <0>;
 364                 clock-names = "i2c";
 365                 clocks = <&cru PCLK_I2C4>;
 366                 pinctrl-names = "default";
 367                 pinctrl-0 = <&i2c4_xfer>;
 368                 status = "disabled";
 369         };
 370
 371         i2c5: i2c@ff170000 {
 372                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 373                 reg = <0x0 0xff170000 0x0 0x1000>;
 374                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 375                 #address-cells = <1>;
 376                 #size-cells = <0>;
 377                 clock-names = "i2c";
 378                 clocks = <&cru PCLK_I2C5>;
 379                 pinctrl-names = "default";
 380                 pinctrl-0 = <&i2c5_xfer>;
 381                 status = "disabled";
 382         };
 383
 384         uart0: serial@ff180000 {
 385                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 386                 reg = <0x0 0xff180000 0x0 0x100>;
 387                 clock-frequency = <24000000>;
 388                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 389                 clock-names = "baudclk", "apb_pclk";
 390                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 391                 reg-shift = <2>;
 392                 reg-io-width = <4>;
 393                 pinctrl-names = "default";
 394                 pinctrl-0 = <&uart0_xfer>;
 395                 status = "disabled";
 396         };
 397
 398         uart1: serial@ff190000 {
 399                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 400                 reg = <0x0 0xff190000 0x0 0x100>;
 401                 clock-frequency = <24000000>;
 402                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 403                 clock-names = "baudclk", "apb_pclk";
 404                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 405                 reg-shift = <2>;
 406                 reg-io-width = <4>;
 407                 pinctrl-names = "default";
 408                 pinctrl-1 = <&uart0_xfer>;
 409                 status = "disabled";
 410         };
 411
 412         uart3: serial@ff1b0000 {
 413                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 414                 reg = <0x0 0xff1b0000 0x0 0x100>;
 415                 clock-frequency = <24000000>;
 416                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 417                 clock-names = "baudclk", "apb_pclk";
 418                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 419                 reg-shift = <2>;
 420                 reg-io-width = <4>;
 421                 pinctrl-names = "default";
 422                 pinctrl-0 = <&uart3_xfer>;
 423                 status = "disabled";
 424         };
 425
 426         uart4: serial@ff1c0000 {
 427                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 428                 reg = <0x0 0xff1c0000 0x0 0x100>;
 429                 clock-frequency = <24000000>;
 430                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 431                 clock-names = "baudclk", "apb_pclk";
 432                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 433                 reg-shift = <2>;
 434                 reg-io-width = <4>;
 435                 pinctrl-names = "default";
 436                 pinctrl-0 = <&uart4_xfer>;
 437                 status = "disabled";
 438         };
 439
 440         thermal-zones {
 441                 cpu {
 442                         polling-delay-passive = <100>; /* milliseconds */
 443                         polling-delay = <5000>; /* milliseconds */
 444
 445                         thermal-sensors = <&tsadc 0>;
 446
 447                         trips {
 448                                 cpu_alert0: cpu_alert0 {
 449                                         temperature = <75000>; /* millicelsius */
 450                                         hysteresis = <2000>; /* millicelsius */
 451                                         type = "passive";
 452                                 };
 453                                 cpu_alert1: cpu_alert1 {
 454                                         temperature = <80000>; /* millicelsius */
 455                                         hysteresis = <2000>; /* millicelsius */
 456                                         type = "passive";
 457                                 };
 458                                 cpu_crit: cpu_crit {
 459                                         temperature = <95000>; /* millicelsius */
 460                                         hysteresis = <2000>; /* millicelsius */
 461                                         type = "critical";
 462                                 };
 463                         };
 464
 465                         cooling-maps {
 466                                 map0 {
 467                                         trip = <&cpu_alert0>;
 468                                         cooling-device =
 469                                         <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 470                                 };
 471                                 map1 {
 472                                         trip = <&cpu_alert1>;
 473                                         cooling-device =
 474                                         <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 475                                 };
 476                         };
 477                 };
 478
 479                 gpu {
 480                         polling-delay-passive = <100>; /* milliseconds */
 481                         polling-delay = <5000>; /* milliseconds */
 482
 483                         thermal-sensors = <&tsadc 1>;
 484
 485                         trips {
 486                                 gpu_alert0: gpu_alert0 {
 487                                         temperature = <80000>; /* millicelsius */
 488                                         hysteresis = <2000>; /* millicelsius */
 489                                         type = "passive";
 490                                 };
 491                                 gpu_crit: gpu_crit {
 492                                         temperature = <115000>; /* millicelsius */
 493                                         hysteresis = <2000>; /* millicelsius */
 494                                         type = "critical";
 495                                 };
 496                         };
 497
 498                         cooling-maps {
 499                                 map0 {
 500                                         trip = <&gpu_alert0>;
 501                                         cooling-device =
 502                                         <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 503                                 };
 504                         };
 505                 };
 506         };
 507
 508         tsadc: tsadc@ff280000 {
 509                 compatible = "rockchip,rk3368-tsadc";
 510                 reg = <0x0 0xff280000 0x0 0x100>;
 511                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 512                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 513                 clock-names = "tsadc", "apb_pclk";
 514                 resets = <&cru SRST_TSADC>;
 515                 reset-names = "tsadc-apb";
 516                 pinctrl-names = "init", "default", "sleep";
 517                 pinctrl-0 = <&otp_gpio>;
 518                 pinctrl-1 = <&otp_out>;
 519                 pinctrl-2 = <&otp_gpio>;
 520                 #thermal-sensor-cells = <1>;
 521                 rockchip,hw-tshut-temp = <95000>;
 522                 status = "disabled";
 523         };
 524
 525         gmac: ethernet@ff290000 {
 526                 compatible = "rockchip,rk3368-gmac";
 527                 reg = <0x0 0xff290000 0x0 0x10000>;
 528                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 529                 interrupt-names = "macirq";
 530                 rockchip,grf = <&grf>;
 531                 clocks = <&cru SCLK_MAC>,
 532                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 533                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 534                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 535                 clock-names = "stmmaceth",
 536                         "mac_clk_rx", "mac_clk_tx",
 537                         "clk_mac_ref", "clk_mac_refout",
 538                         "aclk_mac", "pclk_mac";
 539                 status = "disabled";
 540         };
 541
 542         usb_host0_ehci: usb@ff500000 {
 543                 compatible = "generic-ehci";
 544                 reg = <0x0 0xff500000 0x0 0x100>;
 545                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 546                 clocks = <&cru HCLK_HOST0>;
 547                 clock-names = "usbhost";
 548                 status = "disabled";
 549         };
 550
 551         usb_otg: usb@ff580000 {
 552                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
 553                                 "snps,dwc2";
 554                 reg = <0x0 0xff580000 0x0 0x40000>;
 555                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 556                 clocks = <&cru HCLK_OTG0>;
 557                 clock-names = "otg";
 558                 dr_mode = "otg";
 559                 g-np-tx-fifo-size = <16>;
 560                 g-rx-fifo-size = <275>;
 561                 g-tx-fifo-size = <256 128 128 64 64 32>;
 562                 g-use-dma;
 563                 status = "disabled";
 564         };
 565
 566         i2c0: i2c@ff650000 {
 567                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 568                 reg = <0x0 0xff650000 0x0 0x1000>;
 569                 clocks = <&cru PCLK_I2C0>;
 570                 clock-names = "i2c";
 571                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 572                 pinctrl-names = "default";
 573                 pinctrl-0 = <&i2c0_xfer>;
 574                 #address-cells = <1>;
 575                 #size-cells = <0>;
 576                 status = "disabled";
 577         };
 578
 579         i2c2: i2c@ff660000 {
 580                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 581                 reg = <0x0 0xff660000 0x0 0x1000>;
 582                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 583                 #address-cells = <1>;
 584                 #size-cells = <0>;
 585                 clock-names = "i2c";
 586                 clocks = <&cru PCLK_I2C2>;
 587                 pinctrl-names = "default";
 588                 pinctrl-0 = <&i2c2_xfer>;
 589                 status = "disabled";
 590         };
 591
 592         pwm0: pwm@ff680000 {
 593                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 594                 reg = <0x0 0xff680000 0x0 0x10>;
 595                 #pwm-cells = <3>;
 596                 pinctrl-names = "default";
 597                 pinctrl-0 = <&pwm0_pin>;
 598                 clocks = <&cru PCLK_PWM1>;
 599                 clock-names = "pwm";
 600                 status = "disabled";
 601         };
 602
 603         pwm1: pwm@ff680010 {
 604                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 605                 reg = <0x0 0xff680010 0x0 0x10>;
 606                 #pwm-cells = <3>;
 607                 pinctrl-names = "default";
 608                 pinctrl-0 = <&pwm1_pin>;
 609                 clocks = <&cru PCLK_PWM1>;
 610                 clock-names = "pwm";
 611                 status = "disabled";
 612         };
 613
 614         pwm2: pwm@ff680020 {
 615                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 616                 reg = <0x0 0xff680020 0x0 0x10>;
 617                 #pwm-cells = <3>;
 618                 clocks = <&cru PCLK_PWM1>;
 619                 clock-names = "pwm";
 620                 status = "disabled";
 621         };
 622
 623         pwm3: pwm@ff680030 {
 624                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 625                 reg = <0x0 0xff680030 0x0 0x10>;
 626                 #pwm-cells = <3>;
 627                 pinctrl-names = "default";
 628                 pinctrl-0 = <&pwm3_pin>;
 629                 clocks = <&cru PCLK_PWM1>;
 630                 clock-names = "pwm";
 631                 status = "disabled";
 632         };
 633
 634         uart2: serial@ff690000 {
 635                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 636                 reg = <0x0 0xff690000 0x0 0x100>;
 637                 clock-frequency = <24000000>;
 638                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 639                 clock-names = "baudclk", "apb_pclk";
 640                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 641                 pinctrl-names = "default";
 642                 pinctrl-0 = <&uart2_xfer>;
 643                 reg-shift = <2>;
 644                 reg-io-width = <4>;
 645                 status = "disabled";
 646         };
 647
 648         mbox: mbox@ff6b0000 {
 649                 compatible = "rockchip,rk3368-mailbox";
 650                 reg = <0x0 0xff6b0000 0x0 0x1000>;
 651                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 652                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 653                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 654                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 655                 clocks = <&cru PCLK_MAILBOX>;
 656                 clock-names = "pclk_mailbox";
 657                 #mbox-cells = <1>;
 658         };
 659
 660         pmugrf: syscon@ff738000 {
 661                 u-boot,dm-pre-reloc;
 662                 compatible = "rockchip,rk3368-pmugrf", "syscon";
 663                 reg = <0x0 0xff738000 0x0 0x1000>;
 664         };
 665
 666         sgrf: syscon@ff740000 {
 667                 compatible = "rockchip,rk3368-sgrf", "syscon";
 668                 reg = <0x0 0xff740000 0x0 0x1000>;
 669         };
 670
 671         cru: clock-controller@ff760000 {
 672                 u-boot,dm-pre-reloc;
 673                 compatible = "rockchip,rk3368-cru";
 674                 reg = <0x0 0xff760000 0x0 0x1000>;
 675                 rockchip,grf = <&grf>;
 676                 #clock-cells = <1>;
 677                 #reset-cells = <1>;
 678         };
 679
 680         grf: syscon@ff770000 {
 681                 u-boot,dm-pre-reloc;
 682                 compatible = "rockchip,rk3368-grf", "syscon";
 683                 reg = <0x0 0xff770000 0x0 0x1000>;
 684         };
 685
 686         wdt: watchdog@ff800000 {
 687                 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
 688                 reg = <0x0 0xff800000 0x0 0x100>;
 689                 clocks = <&cru PCLK_WDT>;
 690                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 691                 status = "disabled";
 692         };
 693
 694         timer@ff810000 {
 695                 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
 696                 reg = <0x0 0xff810000 0x0 0x20>;
 697                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 698         };
 699
 700         gic: interrupt-controller@ffb71000 {
 701                 compatible = "arm,gic-400";
 702                 interrupt-controller;
 703                 #interrupt-cells = <3>;
 704                 #address-cells = <0>;
 705
 706                 reg = <0x0 0xffb71000 0x0 0x1000>,
 707                       <0x0 0xffb72000 0x0 0x1000>,
 708                       <0x0 0xffb74000 0x0 0x2000>,
 709                       <0x0 0xffb76000 0x0 0x2000>;
 710                 interrupts = <GIC_PPI 9
 711                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 712         };
 713
 714         pinctrl: pinctrl {
 715                 compatible = "rockchip,rk3368-pinctrl";
 716                 rockchip,grf = <&grf>;
 717                 rockchip,pmu = <&pmugrf>;
 718                 #address-cells = <0x2>;
 719                 #size-cells = <0x2>;
 720                 ranges;
 721
 722                 gpio0: gpio0@ff750000 {
 723                         compatible = "rockchip,gpio-bank";
 724                         reg = <0x0 0xff750000 0x0 0x100>;
 725                         clocks = <&cru PCLK_GPIO0>;
 726                         interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
 727
 728                         gpio-controller;
 729                         #gpio-cells = <0x2>;
 730
 731                         interrupt-controller;
 732                         #interrupt-cells = <0x2>;
 733                 };
 734
 735                 gpio1: gpio1@ff780000 {
 736                         compatible = "rockchip,gpio-bank";
 737                         reg = <0x0 0xff780000 0x0 0x100>;
 738                         clocks = <&cru PCLK_GPIO1>;
 739                         interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
 740
 741                         gpio-controller;
 742                         #gpio-cells = <0x2>;
 743
 744                         interrupt-controller;
 745                         #interrupt-cells = <0x2>;
 746                 };
 747
 748                 gpio2: gpio2@ff790000 {
 749                         compatible = "rockchip,gpio-bank";
 750                         reg = <0x0 0xff790000 0x0 0x100>;
 751                         clocks = <&cru PCLK_GPIO2>;
 752                         interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
 753
 754                         gpio-controller;
 755                         #gpio-cells = <0x2>;
 756
 757                         interrupt-controller;
 758                         #interrupt-cells = <0x2>;
 759                 };
 760
 761                 gpio3: gpio3@ff7a0000 {
 762                         compatible = "rockchip,gpio-bank";
 763                         reg = <0x0 0xff7a0000 0x0 0x100>;
 764                         clocks = <&cru PCLK_GPIO3>;
 765                         interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
 766
 767                         gpio-controller;
 768                         #gpio-cells = <0x2>;
 769
 770                         interrupt-controller;
 771                         #interrupt-cells = <0x2>;
 772                 };
 773
 774                 pcfg_pull_up: pcfg-pull-up {
 775                         bias-pull-up;
 776                 };
 777
 778                 pcfg_pull_down: pcfg-pull-down {
 779                         bias-pull-down;
 780                 };
 781
 782                 pcfg_pull_none: pcfg-pull-none {
 783                         bias-disable;
 784                 };
 785
 786                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 787                         bias-disable;
 788                         drive-strength = <12>;
 789                 };
 790
 791                 emmc {
 792                         emmc_clk: emmc-clk {
 793                                 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
 794                         };
 795
 796                         emmc_cmd: emmc-cmd {
 797                                 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
 798                         };
 799
 800                         emmc_pwr: emmc-pwr {
 801                                 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
 802                         };
 803
 804                         emmc_bus1: emmc-bus1 {
 805                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
 806                         };
 807
 808                         emmc_bus4: emmc-bus4 {
 809                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
 810                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
 811                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
 812                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>;
 813                         };
 814
 815                         emmc_bus8: emmc-bus8 {
 816                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
 817                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
 818                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
 819                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>,
 820                                                 <1 22 RK_FUNC_2 &pcfg_pull_up>,
 821                                                 <1 23 RK_FUNC_2 &pcfg_pull_up>,
 822                                                 <1 24 RK_FUNC_2 &pcfg_pull_up>,
 823                                                 <1 25 RK_FUNC_2 &pcfg_pull_up>;
 824                         };
 825                 };
 826
 827                 gmac {
 828                         rgmii_pins: rgmii-pins {
 829                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
 830                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
 831                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
 832                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
 833                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
 834                                                 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
 835                                                 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
 836                                                 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
 837                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
 838                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
 839                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
 840                                                 <3 17 RK_FUNC_1 &pcfg_pull_none>,
 841                                                 <3 18 RK_FUNC_1 &pcfg_pull_none>,
 842                                                 <3 25 RK_FUNC_1 &pcfg_pull_none>,
 843                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>;
 844                         };
 845
 846                         rmii_pins: rmii-pins {
 847                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
 848                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
 849                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
 850                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
 851                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
 852                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
 853                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
 854                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
 855                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>,
 856                                                 <3 21 RK_FUNC_1 &pcfg_pull_none>;
 857                         };
 858                 };
 859
 860                 i2c0 {
 861                         i2c0_xfer: i2c0-xfer {
 862                                 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
 863                                                 <0 7 RK_FUNC_1 &pcfg_pull_none>;
 864                         };
 865                 };
 866
 867                 i2c1 {
 868                         i2c1_xfer: i2c1-xfer {
 869                                 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
 870                                                 <2 22 RK_FUNC_1 &pcfg_pull_none>;
 871                         };
 872                 };
 873
 874                 i2c2 {
 875                         i2c2_xfer: i2c2-xfer {
 876                                 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
 877                                                 <3 31 RK_FUNC_2 &pcfg_pull_none>;
 878                         };
 879                 };
 880
 881                 i2c3 {
 882                         i2c3_xfer: i2c3-xfer {
 883                                 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
 884                                                 <1 17 RK_FUNC_1 &pcfg_pull_none>;
 885                         };
 886                 };
 887
 888                 i2c4 {
 889                         i2c4_xfer: i2c4-xfer {
 890                                 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
 891                                                 <3 25 RK_FUNC_2 &pcfg_pull_none>;
 892                         };
 893                 };
 894
 895                 i2c5 {
 896                         i2c5_xfer: i2c5-xfer {
 897                                 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
 898                                                 <3 27 RK_FUNC_2 &pcfg_pull_none>;
 899                         };
 900                 };
 901
 902                 pwm0 {
 903                         pwm0_pin: pwm0-pin {
 904                                 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
 905                         };
 906                 };
 907
 908                 pwm1 {
 909                         pwm1_pin: pwm1-pin {
 910                                 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
 911                         };
 912                 };
 913
 914                 pwm3 {
 915                         pwm3_pin: pwm3-pin {
 916                                 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
 917                         };
 918                 };
 919
 920                 sdio0 {
 921                         sdio0_bus1: sdio0-bus1 {
 922                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
 923                         };
 924
 925                         sdio0_bus4: sdio0-bus4 {
 926                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
 927                                                 <2 29 RK_FUNC_1 &pcfg_pull_up>,
 928                                                 <2 30 RK_FUNC_1 &pcfg_pull_up>,
 929                                                 <2 31 RK_FUNC_1 &pcfg_pull_up>;
 930                         };
 931
 932                         sdio0_cmd: sdio0-cmd {
 933                                 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
 934                         };
 935
 936                         sdio0_clk: sdio0-clk {
 937                                 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
 938                         };
 939
 940                         sdio0_cd: sdio0-cd {
 941                                 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
 942                         };
 943
 944                         sdio0_wp: sdio0-wp {
 945                                 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
 946                         };
 947
 948                         sdio0_pwr: sdio0-pwr {
 949                                 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
 950                         };
 951
 952                         sdio0_bkpwr: sdio0-bkpwr {
 953                                 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
 954                         };
 955
 956                         sdio0_int: sdio0-int {
 957                                 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
 958                         };
 959                 };
 960
 961                 sdmmc {
 962                         sdmmc_clk: sdmmc-clk {
 963                                 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
 964                         };
 965
 966                         sdmmc_cmd: sdmmc-cmd {
 967                                 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
 968                         };
 969
 970                         sdmmc_cd: sdmmc-cd {
 971                                 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
 972                         };
 973
 974                         sdmmc_bus1: sdmmc-bus1 {
 975                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
 976                         };
 977
 978                         sdmmc_bus4: sdmmc-bus4 {
 979                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
 980                                                 <2 6 RK_FUNC_1 &pcfg_pull_up>,
 981                                                 <2 7 RK_FUNC_1 &pcfg_pull_up>,
 982                                                 <2 8 RK_FUNC_1 &pcfg_pull_up>;
 983                         };
 984                 };
 985
 986                 spi0 {
 987                         spi0_clk: spi0-clk {
 988                                 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
 989                         };
 990                         spi0_cs0: spi0-cs0 {
 991                                 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
 992                         };
 993                         spi0_cs1: spi0-cs1 {
 994                                 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
 995                         };
 996                         spi0_tx: spi0-tx {
 997                                 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
 998                         };
 999                         spi0_rx: spi0-rx {
1000                                 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
1001                         };
1002                 };
1003
1004                 spi1 {
1005                         spi1_clk: spi1-clk {
1006                                 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
1007                         };
1008                         spi1_cs0: spi1-cs0 {
1009                                 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
1010                         };
1011                         spi1_cs1: spi1-cs1 {
1012                                 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1013                         };
1014                         spi1_rx: spi1-rx {
1015                                 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1016                         };
1017                         spi1_tx: spi1-tx {
1018                                 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1019                         };
1020                 };
1021
1022                 spi2 {
1023                         spi2_clk: spi2-clk {
1024                                 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1025                         };
1026                         spi2_cs0: spi2-cs0 {
1027                                 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1028                         };
1029                         spi2_rx: spi2-rx {
1030                                 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1031                         };
1032                         spi2_tx: spi2-tx {
1033                                 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1034                         };
1035                 };
1036
1037                 tsadc {
1038                         otp_gpio: otp-gpio {
1039                                 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
1040                         };
1041
1042                         otp_out: otp-out {
1043                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_none>;
1044                         };
1045                 };
1046
1047                 uart0 {
1048                         uart0_xfer: uart0-xfer {
1049                                 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1050                                                 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1051                         };
1052
1053                         uart0_cts: uart0-cts {
1054                                 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1055                         };
1056
1057                         uart0_rts: uart0-rts {
1058                                 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1059                         };
1060                 };
1061
1062                 uart1 {
1063                         uart1_xfer: uart1-xfer {
1064                                 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1065                                                 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1066                         };
1067
1068                         uart1_cts: uart1-cts {
1069                                 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1070                         };
1071
1072                         uart1_rts: uart1-rts {
1073                                 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1074                         };
1075                 };
1076
1077                 uart2 {
1078                         uart2_xfer: uart2-xfer {
1079                                 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1080                                                 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1081                         };
1082                         /* no rts / cts for uart2 */
1083                 };
1084
1085                 uart3 {
1086                         uart3_xfer: uart3-xfer {
1087                                 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1088                                                 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1089                         };
1090
1091                         uart3_cts: uart3-cts {
1092                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1093                         };
1094
1095                         uart3_rts: uart3-rts {
1096                                 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1097                         };
1098                 };
1099
1100                 uart4 {
1101                         uart4_xfer: uart4-xfer {
1102                                 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1103                                                 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1104                         };
1105
1106                         uart4_cts: uart4-cts {
1107                                 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1108                         };
1109
1110                         uart4_rts: uart4-rts {
1111                                 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
1112                         };
1113                 };
1114         };
1115 };