arch/arm/dts/dra72-evm.dts

   1 /*
   2  * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 /dts-v1/;
   9
  10 #include "dra72x.dtsi"
  11 #include <dt-bindings/gpio/gpio.h>
  12
  13 / {
  14         model = "TI DRA722";
  15         compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
  16
  17         chosen {
  18                 stdout-path = &uart1;
  19                 tick-timer = &timer2;
  20         };
  21
  22         memory {
  23                 device_type = "memory";
  24                 reg = <0x80000000 0x40000000>; /* 1024 MB */
  25         };
  26
  27         aliases {
  28                 display0 = &hdmi0;
  29         };
  30
  31         evm_3v3: fixedregulator-evm_3v3 {
  32                 compatible = "regulator-fixed";
  33                 regulator-name = "evm_3v3";
  34                 regulator-min-microvolt = <3300000>;
  35                 regulator-max-microvolt = <3300000>;
  36         };
  37
  38         evm_3v3_sd: fixedregulator-sd {
  39                 compatible = "regulator-fixed";
  40                 regulator-name = "evm_3v3_sd";
  41                 regulator-min-microvolt = <3300000>;
  42                 regulator-max-microvolt = <3300000>;
  43                 enable-active-high;
  44                 gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
  45         };
  46
  47         extcon_usb1: extcon_usb1 {
  48                 compatible = "linux,extcon-usb-gpio";
  49                 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
  50         };
  51
  52         extcon_usb2: extcon_usb2 {
  53                 compatible = "linux,extcon-usb-gpio";
  54                 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
  55         };
  56
  57         hdmi0: connector {
  58                 compatible = "hdmi-connector";
  59                 label = "hdmi";
  60
  61                 type = "a";
  62
  63                 port {
  64                         hdmi_connector_in: endpoint {
  65                                 remote-endpoint = <&tpd12s015_out>;
  66                         };
  67                 };
  68         };
  69
  70         tpd12s015: encoder {
  71                 compatible = "ti,tpd12s015";
  72
  73                 pinctrl-names = "default";
  74                 pinctrl-0 = <&tpd12s015_pins>;
  75
  76                 gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
  77                         <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
  78                         <&gpio7 12 GPIO_ACTIVE_HIGH>;   /* gpio7_12/sp1_cs2, HPD */
  79
  80                 ports {
  81                         #address-cells = <1>;
  82                         #size-cells = <0>;
  83
  84                         port@0 {
  85                                 reg = <0>;
  86
  87                                 tpd12s015_in: endpoint {
  88                                         remote-endpoint = <&hdmi_out>;
  89                                 };
  90                         };
  91
  92                         port@1 {
  93                                 reg = <1>;
  94
  95                                 tpd12s015_out: endpoint {
  96                                         remote-endpoint = <&hdmi_connector_in>;
  97                                 };
  98                         };
  99                 };
 100         };
 101 };
 102
 103 &dra7_pmx_core {
 104         i2c1_pins: pinmux_i2c1_pins {
 105                 pinctrl-single,pins = <
 106                         0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
 107                         0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
 108                 >;
 109         };
 110
 111         i2c5_pins: pinmux_i2c5_pins {
 112                 pinctrl-single,pins = <
 113                         0x2b4 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
 114                         0x2b8 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
 115                 >;
 116         };
 117
 118         nand_default: nand_default {
 119                 pinctrl-single,pins = <
 120                         0x0     (PIN_INPUT  | MUX_MODE0) /* gpmc_ad0 */
 121                         0x4     (PIN_INPUT  | MUX_MODE0) /* gpmc_ad1 */
 122                         0x8     (PIN_INPUT  | MUX_MODE0) /* gpmc_ad2 */
 123                         0xc     (PIN_INPUT  | MUX_MODE0) /* gpmc_ad3 */
 124                         0x10    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad4 */
 125                         0x14    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad5 */
 126                         0x18    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad6 */
 127                         0x1c    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad7 */
 128                         0x20    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad8 */
 129                         0x24    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad9 */
 130                         0x28    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad10 */
 131                         0x2c    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad11 */
 132                         0x30    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad12 */
 133                         0x34    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad13 */
 134                         0x38    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad14 */
 135                         0x3c    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad15 */
 136                         0xb4    (PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */
 137                         0xc4    (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
 138                         0xcc    (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
 139                         0xc8    (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
 140                         0xd0    (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */
 141                         0xd8    (PIN_INPUT  | MUX_MODE0) /* gpmc_wait0 */
 142                 >;
 143         };
 144
 145         usb1_pins: pinmux_usb1_pins {
 146                 pinctrl-single,pins = <
 147                         0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
 148                 >;
 149         };
 150
 151         usb2_pins: pinmux_usb2_pins {
 152                 pinctrl-single,pins = <
 153                         0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
 154                 >;
 155         };
 156
 157         tps65917_pins_default: tps65917_pins_default {
 158                 pinctrl-single,pins = <
 159                         0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
 160                 >;
 161         };
 162
 163         mmc1_pins_default: mmc1_pins_default {
 164                 pinctrl-single,pins = <
 165                         0x36c (PIN_INPUT | MUX_MODE14)  /* mmc1sdcd.gpio219 */
 166                         0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
 167                         0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
 168                         0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
 169                         0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
 170                         0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
 171                         0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
 172                 >;
 173         };
 174
 175         mmc2_pins_default: mmc2_pins_default {
 176                 pinctrl-single,pins = <
 177                         0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
 178                         0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
 179                         0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
 180                         0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
 181                         0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
 182                         0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
 183                         0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
 184                         0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
 185                         0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
 186                         0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
 187                 >;
 188         };
 189
 190         dcan1_pins_default: dcan1_pins_default {
 191                 pinctrl-single,pins = <
 192                         0x3d0   (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
 193                         0x418   (PULL_UP | MUX_MODE1)   /* wakeup0.dcan1_rx */
 194                 >;
 195         };
 196
 197         dcan1_pins_sleep: dcan1_pins_sleep {
 198                 pinctrl-single,pins = <
 199                         0x3d0   (MUX_MODE15 | PULL_UP)  /* dcan1_tx.off */
 200                         0x418   (MUX_MODE15 | PULL_UP)  /* wakeup0.off */
 201                 >;
 202         };
 203
 204         qspi1_pins: pinmux_qspi1_pins {
 205                 pinctrl-single,pins = <
 206                         0x74 (PIN_OUTPUT | MUX_MODE1)   /* gpmc_a13.qspi1_rtclk */
 207                         0x78 (PIN_INPUT | MUX_MODE1)    /* gpmc_a14.qspi1_d3 */
 208                         0x7c (PIN_INPUT | MUX_MODE1)    /* gpmc_a15.qspi1_d2 */
 209                         0x80 (PIN_INPUT | MUX_MODE1)    /* gpmc_a16.qspi1_d1 */
 210                         0x84 (PIN_INPUT | MUX_MODE1)    /* gpmc_a17.qspi1_d0 */
 211                         0x88 (PIN_OUTPUT | MUX_MODE1)   /* qpmc_a18.qspi1_sclk */
 212                         0xb8 (PIN_OUTPUT | MUX_MODE1)   /* gpmc_cs2.qspi1_cs0 */
 213                 >;
 214         };
 215
 216         hdmi_pins: pinmux_hdmi_pins {
 217                 pinctrl-single,pins = <
 218                         0x408 (PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
 219                         0x40c (PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
 220                 >;
 221         };
 222
 223         tpd12s015_pins: pinmux_tpd12s015_pins {
 224                 pinctrl-single,pins = <
 225                         0x3b8 (PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */
 226                 >;
 227         };
 228 };
 229
 230 &i2c1 {
 231         status = "okay";
 232         pinctrl-names = "default";
 233         pinctrl-0 = <&i2c1_pins>;
 234         clock-frequency = <400000>;
 235
 236         tps65917: tps65917@58 {
 237                 compatible = "ti,tps65917";
 238                 reg = <0x58>;
 239
 240                 pinctrl-names = "default";
 241                 pinctrl-0 = <&tps65917_pins_default>;
 242
 243                 interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>;  /* IRQ_SYS_1N */
 244                 interrupt-controller;
 245                 #interrupt-cells = <2>;
 246
 247                 ti,system-power-controller;
 248
 249                 tps65917_pmic {
 250                         compatible = "ti,tps65917-pmic";
 251
 252                         regulators {
 253                                 smps1_reg: smps1 {
 254                                         /* VDD_MPU */
 255                                         regulator-name = "smps1";
 256                                         regulator-min-microvolt = <850000>;
 257                                         regulator-max-microvolt = <1250000>;
 258                                         regulator-always-on;
 259                                         regulator-boot-on;
 260                                 };
 261
 262                                 smps2_reg: smps2 {
 263                                         /* VDD_CORE */
 264                                         regulator-name = "smps2";
 265                                         regulator-min-microvolt = <850000>;
 266                                         regulator-max-microvolt = <1060000>;
 267                                         regulator-boot-on;
 268                                         regulator-always-on;
 269                                 };
 270
 271                                 smps3_reg: smps3 {
 272                                         /* VDD_GPU IVA DSPEVE */
 273                                         regulator-name = "smps3";
 274                                         regulator-min-microvolt = <850000>;
 275                                         regulator-max-microvolt = <1250000>;
 276                                         regulator-boot-on;
 277                                         regulator-always-on;
 278                                 };
 279
 280                                 smps4_reg: smps4 {
 281                                         /* VDDS1V8 */
 282                                         regulator-name = "smps4";
 283                                         regulator-min-microvolt = <1800000>;
 284                                         regulator-max-microvolt = <1800000>;
 285                                         regulator-always-on;
 286                                         regulator-boot-on;
 287                                 };
 288
 289                                 smps5_reg: smps5 {
 290                                         /* VDD_DDR */
 291                                         regulator-name = "smps5";
 292                                         regulator-min-microvolt = <1350000>;
 293                                         regulator-max-microvolt = <1350000>;
 294                                         regulator-boot-on;
 295                                         regulator-always-on;
 296                                 };
 297
 298                                 ldo1_reg: ldo1 {
 299                                         /* LDO1_OUT --> SDIO  */
 300                                         regulator-name = "ldo1";
 301                                         regulator-min-microvolt = <1800000>;
 302                                         regulator-max-microvolt = <3300000>;
 303                                         regulator-boot-on;
 304                                 };
 305
 306                                 ldo2_reg: ldo2 {
 307                                         /* LDO2_OUT --> TP1017 (UNUSED)  */
 308                                         regulator-name = "ldo2";
 309                                         regulator-min-microvolt = <1800000>;
 310                                         regulator-max-microvolt = <3300000>;
 311                                 };
 312
 313                                 ldo3_reg: ldo3 {
 314                                         /* VDDA_1V8_PHY */
 315                                         regulator-name = "ldo3";
 316                                         regulator-min-microvolt = <1800000>;
 317                                         regulator-max-microvolt = <1800000>;
 318                                         regulator-boot-on;
 319                                         regulator-always-on;
 320                                 };
 321
 322                                 ldo5_reg: ldo5 {
 323                                         /* VDDA_1V8_PLL */
 324                                         regulator-name = "ldo5";
 325                                         regulator-min-microvolt = <1800000>;
 326                                         regulator-max-microvolt = <1800000>;
 327                                         regulator-always-on;
 328                                         regulator-boot-on;
 329                                 };
 330
 331                                 ldo4_reg: ldo4 {
 332                                         /* VDDA_3V_USB: VDDA_USBHS33 */
 333                                         regulator-name = "ldo4";
 334                                         regulator-min-microvolt = <3300000>;
 335                                         regulator-max-microvolt = <3300000>;
 336                                         regulator-boot-on;
 337                                 };
 338                         };
 339                 };
 340
 341                 tps65917_power_button {
 342                         compatible = "ti,palmas-pwrbutton";
 343                         interrupt-parent = <&tps65917>;
 344                         interrupts = <1 IRQ_TYPE_NONE>;
 345                         wakeup-source;
 346                         ti,palmas-long-press-seconds = <6>;
 347                 };
 348         };
 349
 350         pcf_gpio_21: gpio@21 {
 351                 compatible = "ti,pcf8575";
 352                 reg = <0x21>;
 353                 lines-initial-states = <0x1408>;
 354                 gpio-controller;
 355                 #gpio-cells = <2>;
 356                 interrupt-parent = <&gpio6>;
 357                 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
 358                 interrupt-controller;
 359                 #interrupt-cells = <2>;
 360                 u-boot,i2c-offset-len = <0>;
 361         };
 362 };
 363
 364 &i2c5 {
 365         status = "okay";
 366         pinctrl-names = "default";
 367         pinctrl-0 = <&i2c5_pins>;
 368         clock-frequency = <400000>;
 369
 370         pcf_hdmi: pcf8575@26 {
 371                 compatible = "nxp,pcf8575";
 372                 reg = <0x26>;
 373                 gpio-controller;
 374                 #gpio-cells = <2>;
 375                 /*
 376                  * initial state is used here to keep the mdio interface
 377                  * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
 378                  * VIN2_S0 driven high otherwise Ethernet stops working
 379                  * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
 380                  */
 381                 lines-initial-states = <0x0f2b>;
 382                 u-boot,i2c-offset-len = <0>;
 383         };
 384 };
 385
 386 &uart1 {
 387         status = "okay";
 388 };
 389
 390 &elm {
 391         status = "okay";
 392 };
 393
 394 &gpmc {
 395         status = "okay";
 396         pinctrl-names = "default";
 397         pinctrl-0 = <&nand_default>;
 398         ranges = <0 0 0 0x01000000>;    /* minimum GPMC partition = 16MB */
 399         nand@0,0 {
 400                 /* To use NAND, DIP switch SW5 must be set like so:
 401                  * SW5.1 (NAND_SELn) = ON (LOW)
 402                  * SW5.9 (GPMC_WPN) = OFF (HIGH)
 403                  */
 404                 reg = <0 0 4>;          /* device IO registers */
 405                 ti,nand-ecc-opt = "bch8";
 406                 ti,elm-id = <&elm>;
 407                 nand-bus-width = <16>;
 408                 gpmc,device-width = <2>;
 409                 gpmc,sync-clk-ps = <0>;
 410                 gpmc,cs-on-ns = <0>;
 411                 gpmc,cs-rd-off-ns = <80>;
 412                 gpmc,cs-wr-off-ns = <80>;
 413                 gpmc,adv-on-ns = <0>;
 414                 gpmc,adv-rd-off-ns = <60>;
 415                 gpmc,adv-wr-off-ns = <60>;
 416                 gpmc,we-on-ns = <10>;
 417                 gpmc,we-off-ns = <50>;
 418                 gpmc,oe-on-ns = <4>;
 419                 gpmc,oe-off-ns = <40>;
 420                 gpmc,access-ns = <40>;
 421                 gpmc,wr-access-ns = <80>;
 422                 gpmc,rd-cycle-ns = <80>;
 423                 gpmc,wr-cycle-ns = <80>;
 424                 gpmc,bus-turnaround-ns = <0>;
 425                 gpmc,cycle2cycle-delay-ns = <0>;
 426                 gpmc,clk-activation-ns = <0>;
 427                 gpmc,wait-monitoring-ns = <0>;
 428                 gpmc,wr-data-mux-bus-ns = <0>;
 429                 /* MTD partition table */
 430                 /* All SPL-* partitions are sized to minimal length
 431                  * which can be independently programmable. For
 432                  * NAND flash this is equal to size of erase-block */
 433                 #address-cells = <1>;
 434                 #size-cells = <1>;
 435                 partition@0 {
 436                         label = "NAND.SPL";
 437                         reg = <0x00000000 0x000020000>;
 438                 };
 439                 partition@1 {
 440                         label = "NAND.SPL.backup1";
 441                         reg = <0x00020000 0x00020000>;
 442                 };
 443                 partition@2 {
 444                         label = "NAND.SPL.backup2";
 445                         reg = <0x00040000 0x00020000>;
 446                 };
 447                 partition@3 {
 448                         label = "NAND.SPL.backup3";
 449                         reg = <0x00060000 0x00020000>;
 450                 };
 451                 partition@4 {
 452                         label = "NAND.u-boot-spl-os";
 453                         reg = <0x00080000 0x00040000>;
 454                 };
 455                 partition@5 {
 456                         label = "NAND.u-boot";
 457                         reg = <0x000c0000 0x00100000>;
 458                 };
 459                 partition@6 {
 460                         label = "NAND.u-boot-env";
 461                         reg = <0x001c0000 0x00020000>;
 462                 };
 463                 partition@7 {
 464                         label = "NAND.u-boot-env.backup1";
 465                         reg = <0x001e0000 0x00020000>;
 466                 };
 467                 partition@8 {
 468                         label = "NAND.kernel";
 469                         reg = <0x00200000 0x00800000>;
 470                 };
 471                 partition@9 {
 472                         label = "NAND.file-system";
 473                         reg = <0x00a00000 0x0f600000>;
 474                 };
 475         };
 476 };
 477
 478 &usb2_phy1 {
 479         phy-supply = <&ldo4_reg>;
 480 };
 481
 482 &usb2_phy2 {
 483         phy-supply = <&ldo4_reg>;
 484 };
 485
 486 &omap_dwc3_1 {
 487         extcon = <&extcon_usb1>;
 488 };
 489
 490 &omap_dwc3_2 {
 491         extcon = <&extcon_usb2>;
 492 };
 493
 494 &usb1 {
 495         dr_mode = "peripheral";
 496         pinctrl-names = "default";
 497         pinctrl-0 = <&usb1_pins>;
 498 };
 499
 500 &usb2 {
 501         dr_mode = "host";
 502         pinctrl-names = "default";
 503         pinctrl-0 = <&usb2_pins>;
 504 };
 505
 506 &mmc1 {
 507         status = "okay";
 508         pinctrl-names = "default";
 509         pinctrl-0 = <&mmc1_pins_default>;
 510
 511         vmmc_aux-supply = <&ldo1_reg>;
 512         vmmc-supply = <&evm_3v3_sd>;
 513         bus-width = <4>;
 514         /*
 515          * SDCD signal is not being used here - using the fact that GPIO mode
 516          * is a viable alternative
 517          */
 518         cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
 519 };
 520
 521 &mmc2 {
 522         /* SW5-3 in ON position */
 523         status = "okay";
 524         pinctrl-names = "default";
 525         pinctrl-0 = <&mmc2_pins_default>;
 526
 527         vmmc-supply = <&evm_3v3>;
 528         bus-width = <8>;
 529         ti,non-removable;
 530 };
 531
 532 &dra7_pmx_core {
 533         cpsw_default: cpsw_default {
 534                 pinctrl-single,pins = <
 535                         /* Slave 2 */
 536                         0x198 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d12.rgmii1_txc */
 537                         0x19c (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d13.rgmii1_tctl */
 538                         0x1a0 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d14.rgmii1_td3 */
 539                         0x1a4 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d15.rgmii1_td2 */
 540                         0x1a8 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d16.rgmii1_td1 */
 541                         0x1ac (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d17.rgmii1_td0 */
 542                         0x1b0 (PIN_INPUT | MUX_MODE3)   /* vin2a_d18.rgmii1_rclk */
 543                         0x1b4 (PIN_INPUT | MUX_MODE3)   /* vin2a_d19.rgmii1_rctl */
 544                         0x1b8 (PIN_INPUT | MUX_MODE3)   /* vin2a_d20.rgmii1_rd3 */
 545                         0x1bc (PIN_INPUT | MUX_MODE3)   /* vin2a_d21.rgmii1_rd2 */
 546                         0x1c0 (PIN_INPUT | MUX_MODE3)   /* vin2a_d22.rgmii1_rd1 */
 547                         0x1c4 (PIN_INPUT | MUX_MODE3)   /* vin2a_d23.rgmii1_rd0 */
 548                 >;
 549
 550         };
 551
 552         cpsw_sleep: cpsw_sleep {
 553                 pinctrl-single,pins = <
 554                         /* Slave 2 */
 555                         0x198 (MUX_MODE15)
 556                         0x19c (MUX_MODE15)
 557                         0x1a0 (MUX_MODE15)
 558                         0x1a4 (MUX_MODE15)
 559                         0x1a8 (MUX_MODE15)
 560                         0x1ac (MUX_MODE15)
 561                         0x1b0 (MUX_MODE15)
 562                         0x1b4 (MUX_MODE15)
 563                         0x1b8 (MUX_MODE15)
 564                         0x1bc (MUX_MODE15)
 565                         0x1c0 (MUX_MODE15)
 566                         0x1c4 (MUX_MODE15)
 567                 >;
 568         };
 569
 570         davinci_mdio_default: davinci_mdio_default {
 571                 pinctrl-single,pins = <
 572                         /* MDIO */
 573                         0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0)   /* mdio_d.mdio_d */
 574                         0x240 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mdio_clk.mdio_clk */
 575                 >;
 576         };
 577
 578         davinci_mdio_sleep: davinci_mdio_sleep {
 579                 pinctrl-single,pins = <
 580                         0x23c (MUX_MODE15)
 581                         0x240 (MUX_MODE15)
 582                 >;
 583         };
 584 };
 585
 586 &mac {
 587         status = "okay";
 588         pinctrl-names = "default", "sleep";
 589         pinctrl-0 = <&cpsw_default>;
 590         pinctrl-1 = <&cpsw_sleep>;
 591         mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_HIGH>;
 592 };
 593
 594 &cpsw_emac1 {
 595         phy_id = <&davinci_mdio>, <3>;
 596         phy-mode = "rgmii";
 597 };
 598
 599 &davinci_mdio {
 600         pinctrl-names = "default", "sleep";
 601         pinctrl-0 = <&davinci_mdio_default>;
 602         pinctrl-1 = <&davinci_mdio_sleep>;
 603 };
 604
 605 &dcan1 {
 606         status = "ok";
 607         pinctrl-names = "default", "sleep", "active";
 608         pinctrl-0 = <&dcan1_pins_sleep>;
 609         pinctrl-1 = <&dcan1_pins_sleep>;
 610         pinctrl-2 = <&dcan1_pins_default>;
 611 };
 612
 613 &qspi {
 614         status = "okay";
 615         pinctrl-names = "default";
 616         pinctrl-0 = <&qspi1_pins>;
 617
 618         spi-max-frequency = <76800000>;
 619         m25p80@0 {
 620                 compatible = "s25fl256s1","spi-flash";
 621                 spi-max-frequency = <64000000>;
 622                 reg = <0>;
 623                 spi-tx-bus-width = <1>;
 624                 spi-rx-bus-width = <4>;
 625                 #address-cells = <1>;
 626                 #size-cells = <1>;
 627
 628                 /* MTD partition table.
 629                  * The ROM checks the first four physical blocks
 630                  * for a valid file to boot and the flash here is
 631                  * 64KiB block size.
 632                  */
 633                 partition@0 {
 634                         label = "QSPI.SPL";
 635                         reg = <0x00000000 0x000010000>;
 636                 };
 637                 partition@1 {
 638                         label = "QSPI.SPL.backup1";
 639                         reg = <0x00010000 0x00010000>;
 640                 };
 641                 partition@2 {
 642                         label = "QSPI.SPL.backup2";
 643                         reg = <0x00020000 0x00010000>;
 644                 };
 645                 partition@3 {
 646                         label = "QSPI.SPL.backup3";
 647                         reg = <0x00030000 0x00010000>;
 648                 };
 649                 partition@4 {
 650                         label = "QSPI.u-boot";
 651                         reg = <0x00040000 0x00100000>;
 652                 };
 653                 partition@5 {
 654                         label = "QSPI.u-boot-spl-os";
 655                         reg = <0x00140000 0x00080000>;
 656                 };
 657                 partition@6 {
 658                         label = "QSPI.u-boot-env";
 659                         reg = <0x001c0000 0x00010000>;
 660                 };
 661                 partition@7 {
 662                         label = "QSPI.u-boot-env.backup1";
 663                         reg = <0x001d0000 0x0010000>;
 664                 };
 665                 partition@8 {
 666                         label = "QSPI.kernel";
 667                         reg = <0x001e0000 0x0800000>;
 668                 };
 669                 partition@9 {
 670                         label = "QSPI.file-system";
 671                         reg = <0x009e0000 0x01620000>;
 672                 };
 673         };
 674 };
 675
 676 &dss {
 677         status = "ok";
 678
 679         vdda_video-supply = <&ldo5_reg>;
 680 };
 681
 682 &hdmi {
 683         status = "ok";
 684         vdda-supply = <&ldo3_reg>;
 685
 686         pinctrl-names = "default";
 687         pinctrl-0 = <&hdmi_pins>;
 688
 689         port {
 690                 hdmi_out: endpoint {
 691                         remote-endpoint = <&tpd12s015_in>;
 692                 };
 693         };
 694 };