2 * armboot - Startup Code for XScale
4 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
5 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
6 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
7 * Copyright (C) 2001 Alex Zuepke <azu@sysgo.de>
8 * Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net>
9 * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
10 * Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/arch/pxa-regs.h>
37 #ifdef CONFIG_PRELOADER
54 .word 0x12345678 /* now 16*4=64 */
56 ldr pc, _undefined_instruction
57 ldr pc, _software_interrupt
58 ldr pc, _prefetch_abort
64 _undefined_instruction: .word undefined_instruction
65 _software_interrupt: .word software_interrupt
66 _prefetch_abort: .word prefetch_abort
67 _data_abort: .word data_abort
68 _not_used: .word not_used
71 #endif /* CONFIG_PRELOADER */
73 .balignl 16,0xdeadbeef
77 * Startup Code (reset vector)
79 * do important init only if we don't start from RAM!
80 * - relocate armboot to RAM
82 * - jump to second stage
87 .word CONFIG_SYS_TEXT_BASE
89 #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
96 * These are defined in the board-specific linker script.
106 #ifdef CONFIG_USE_IRQ
107 /* IRQ stack memory (calculated at run-time) */
108 .globl IRQ_STACK_START
112 /* IRQ stack memory (calculated at run-time) */
113 .globl FIQ_STACK_START
116 #endif /* CONFIG_USE_IRQ */
118 #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
119 /* IRQ stack memory (calculated at run-time) + 8 bytes */
120 .globl IRQ_STACK_START_IN
124 .globl _datarel_start
126 .word __datarel_start
128 .globl _datarelrolocal_start
129 _datarelrolocal_start:
130 .word __datarelrolocal_start
132 .globl _datarellocal_start
134 .word __datarellocal_start
136 .globl _datarelro_start
138 .word __datarelro_start
149 * the actual reset code
154 * set the cpu to SVC32 mode
162 * we do sys-critical inits only at reboot,
163 * not when booting from ram!
165 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
169 /* Set stackpointer in internal RAM to call board_init_f */
171 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
175 /*------------------------------------------------------------------------------*/
178 * void relocate_code (addr_sp, gd, addr_moni)
180 * This "function" does not return, instead it continues in RAM
181 * after relocating the monitor code.
186 mov r4, r0 /* save addr_sp */
187 mov r5, r1 /* save addr of gd */
188 mov r6, r2 /* save addr of destination */
189 mov r7, r2 /* save addr of destination */
191 /* Set up the stack */
198 sub r2, r3, r2 /* r2 <- size of armboot */
199 add r2, r0, r2 /* r2 <- source end address */
203 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
205 ldmia r0!, {r9-r10} /* copy from source address [r0] */
206 stmia r6!, {r9-r10} /* copy to target address [r1] */
207 cmp r0, r2 /* until source end address [r2] */
210 #ifndef CONFIG_PRELOADER
211 /* fix got entries */
212 ldr r1, _TEXT_BASE /* Text base */
213 mov r0, r7 /* reloc addr */
214 ldr r2, _got_start /* addr in Flash */
215 ldr r3, _got_end /* addr in Flash */
230 #endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
233 #ifndef CONFIG_PRELOADER
236 ldr r3, _TEXT_BASE /* Text base */
237 mov r4, r7 /* reloc addr */
242 mov r2, #0x00000000 /* clear */
244 clbss_l:str r2, [r0] /* clear loop... */
251 * We are done. Do not return, instead branch to second part of board
252 * initialization, now running from RAM.
254 #ifdef CONFIG_ONENAND_IPL
255 ldr pc, _start_oneboot
257 _start_oneboot: .word start_oneboot
260 ldr r2, _board_init_r
262 add r2, r2, r7 /* position from board_init_r in RAM */
263 /* setup parameters for board_init_r */
264 mov r0, r5 /* gd_t */
265 mov r1, r7 /* dest_addr */
270 _board_init_r: .word board_init_r
273 #else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
275 /****************************************************************************/
277 /* the actual reset code */
279 /****************************************************************************/
282 mrs r0,cpsr /* set the CPU to SVC32 mode */
283 bic r0,r0,#0x1f /* (superviser mode, M=10011) */
288 * we do sys-critical inits only at reboot,
289 * not when booting from RAM!
291 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
292 bl cpu_init_crit /* we do sys-critical inits */
293 #endif /* !CONFIG_SKIP_LOWLEVEL_INIT */
295 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
296 relocate: /* relocate U-Boot to RAM */
297 adr r0, _start /* r0 <- current position of code */
298 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
299 #ifndef CONFIG_PRELOADER
300 cmp r0, r1 /* don't reloc during debug */
304 ldr r2, _armboot_start
306 sub r2, r3, r2 /* r2 <- size of armboot */
307 add r2, r0, r2 /* r2 <- source end address */
310 ldmia r0!, {r3-r10} /* copy from source address [r0] */
311 stmia r1!, {r3-r10} /* copy to target address [r1] */
312 cmp r0, r2 /* until source end address [r2] */
314 #endif /* !CONFIG_SKIP_RELOCATE_UBOOT */
316 /* Set up the stack */
318 ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
319 #ifdef CONFIG_PRELOADER
320 sub sp, r0, #128 /* leave 32 words for abort-stack */
322 sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
323 sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
324 #ifdef CONFIG_USE_IRQ
325 sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
326 #endif /* CONFIG_USE_IRQ */
327 sub sp, r0, #12 /* leave 3 words for abort-stack */
328 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
332 ldr r0, _bss_start /* find start of bss segment */
333 ldr r1, _bss_end /* stop here */
334 mov r2, #0x00000000 /* clear */
336 #ifndef CONFIG_PRELOADER
337 clbss_l:str r2, [r0] /* clear loop... */
343 ldr pc, _start_armboot
345 #ifdef CONFIG_ONENAND_IPL
346 _start_armboot: .word start_oneboot
348 _start_armboot: .word start_armboot
350 #endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
352 /****************************************************************************/
354 /* CPU_init_critical registers */
356 /* - setup important registers */
357 /* - setup memory timing */
359 /****************************************************************************/
360 /* mk@tbd: Fix this! */
369 /* Interrupt-Controller base address */
370 IC_BASE: .word 0x40d00000
373 /* Reset-Controller */
374 RST_BASE: .word 0x40f00030
377 /* Operating System Timer */
378 OSTIMER_BASE: .word 0x40a00000
384 /* Clock Manager Registers */
385 #ifdef CONFIG_CPU_MONAHANS
386 # ifndef CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
387 # error "You have to define CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO!!"
388 # endif /* !CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO */
389 # ifndef CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO
390 # define CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO 0x1
391 # endif /* !CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO */
392 #else /* !CONFIG_CPU_MONAHANS */
393 #ifdef CONFIG_SYS_CPUSPEED
394 CC_BASE: .word 0x41300000
396 cpuspeed: .word CONFIG_SYS_CPUSPEED
397 #else /* !CONFIG_SYS_CPUSPEED */
398 #error "You have to define CONFIG_SYS_CPUSPEED!!"
399 #endif /* CONFIG_SYS_CPUSPEED */
400 #endif /* CONFIG_CPU_MONAHANS */
402 /* takes care the CP15 update has taken place */
404 mrc p15,0,\reg,c2,c0,0
412 #ifndef CONFIG_CPU_MONAHANS
416 #else /* CONFIG_CPU_MONAHANS */
417 /* Step 1 - Enable CP6 permission */
418 mrc p15, 0, r1, c15, c1, 0 @ read CPAR
420 mcr p15, 0, r1, c15, c1, 0
423 /* Step 2 - Mask ICMR & ICMR2 */
425 mcr p6, 0, r1, c1, c0, 0 @ ICMR
426 mcr p6, 0, r1, c7, c0, 0 @ ICMR2
428 /* turn off all clocks but the ones we will definitly require */
430 ldr r2, =(CKENA_22_FFUART | CKENA_10_SRAM | CKENA_9_SMC | CKENA_8_DMC)
433 ldr r2, =(CKENB_6_IRQ)
435 #endif /* !CONFIG_CPU_MONAHANS */
437 /* set clock speed */
438 #ifdef CONFIG_CPU_MONAHANS
440 ldr r1, =(((CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO<<8) & ACCR_XN_MASK) | (CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO & ACCR_XL_MASK))
442 #else /* !CONFIG_CPU_MONAHANS */
443 #ifdef CONFIG_SYS_CPUSPEED
448 mcr p14, 0, r0, c6, c0, 0
452 #endif /* CONFIG_SYS_CPUSPEED */
453 #endif /* CONFIG_CPU_MONAHANS */
456 * before relocating, we have to setup RAM timing
457 * because memory timing is board-dependend, you will
458 * find a lowlevel_init.S in your board directory.
464 /* Memory interfaces are working. Disable MMU and enable I-cache. */
465 /* mk: hmm, this is not in the monahans docs, leave it now but
466 * check here if it doesn't work :-) */
468 ldr r0, =0x2001 /* enable access to all coproc. */
469 mcr p15, 0, r0, c15, c1, 0
472 mcr p15, 0, r0, c7, c10, 4 /* drain the write & fill buffers */
475 mcr p15, 0, r0, c7, c7, 0 /* flush Icache, Dcache and BTB */
478 mcr p15, 0, r0, c8, c7, 0 /* flush instuction and data TLBs */
481 /* Enable the Icache */
483 mrc p15, 0, r0, c1, c0, 0
485 mcr p15, 0, r0, c1, c0, 0
490 #ifndef CONFIG_PRELOADER
491 /****************************************************************************/
493 /* Interrupt handling */
495 /****************************************************************************/
497 /* IRQ stack frame */
499 #define S_FRAME_SIZE 72
521 #define MODE_SVC 0x13
523 /* use bad_save_user_regs for abort/prefetch/undef/swi ... */
525 .macro bad_save_user_regs
526 sub sp, sp, #S_FRAME_SIZE
527 stmia sp, {r0 - r12} /* Calling r0-r12 */
530 #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
531 ldr r2, _armboot_start
532 sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
533 sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
535 ldr r2, IRQ_STACK_START_IN
537 ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
538 add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
542 stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
547 /* use irq_save_user_regs / irq_restore_user_regs for */
548 /* IRQ/FIQ handling */
550 .macro irq_save_user_regs
551 sub sp, sp, #S_FRAME_SIZE
552 stmia sp, {r0 - r12} /* Calling r0-r12 */
554 stmdb r8, {sp, lr}^ /* Calling SP, LR */
555 str lr, [r8, #0] /* Save calling PC */
557 str r6, [r8, #4] /* Save CPSR */
558 str r0, [r8, #8] /* Save OLD_R0 */
562 .macro irq_restore_user_regs
563 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
565 ldr lr, [sp, #S_PC] @ Get PC
566 add sp, sp, #S_FRAME_SIZE
567 subs pc, lr, #4 @ return & move spsr_svc into cpsr
571 #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
572 ldr r13, _armboot_start @ setup our mode stack
573 sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
574 sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
576 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
579 str lr, [r13] @ save caller lr / spsr
583 mov r13, #MODE_SVC @ prepare SVC-Mode
589 .macro get_irq_stack @ setup IRQ stack
590 ldr sp, IRQ_STACK_START
593 .macro get_fiq_stack @ setup FIQ stack
594 ldr sp, FIQ_STACK_START
596 #endif /* CONFIG_PRELOADER */
599 /****************************************************************************/
601 /* exception handlers */
603 /****************************************************************************/
605 #ifdef CONFIG_PRELOADER
608 ldr sp, _TEXT_BASE /* use 32 words abort stack */
609 bl hang /* hang and never return */
610 #else /* !CONFIG_PRELOADER */
612 undefined_instruction:
615 bl do_undefined_instruction
621 bl do_software_interrupt
641 #ifdef CONFIG_USE_IRQ
648 irq_restore_user_regs
653 irq_save_user_regs /* someone ought to write a more */
654 bl do_fiq /* effiction fiq_save_user_regs */
655 irq_restore_user_regs
657 #else /* !CONFIG_USE_IRQ */
670 #endif /* CONFIG_PRELOADER */
671 #endif /* CONFIG_USE_IRQ */
673 /****************************************************************************/
675 /* Reset function: the PXA250 doesn't have a reset function, so we have to */
676 /* perform a watchdog timeout for a soft reset. */
678 /****************************************************************************/
683 /* FIXME: this code is PXA250 specific. How is this handled on */
684 /* other XScale processors? */
688 /* We set OWE:WME (watchdog enable) and wait until timeout happens */
692 orr r1, r1, #0x0001 /* bit0: WME */
695 /* OS timer does only wrap every 1165 seconds, so we have to set */
696 /* the match register as well. */
698 ldr r1, [r0, #OSCR] /* read OS timer */
699 add r1, r1, #0x800 /* let OSMR3 match after */
700 add r1, r1, #0x800 /* 4096*(1/3.6864MHz)=1ms */