1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2014 Freescale Semiconductor, Inc.
11 #include <asm/arch/clock.h>
13 #include <asm/arch/immap_ls102xa.h>
14 #include <asm/cache.h>
15 #include <asm/system.h>
18 #include <fsl_esdhc.h>
24 #define DCSR_RCPM2_BLOCK_OFFSET 0x223000
25 #define DCSR_RCPM2_CPMFSMCR0 0x400
26 #define DCSR_RCPM2_CPMFSMSR0 0x404
27 #define DCSR_RCPM2_CPMFSMCR1 0x414
28 #define DCSR_RCPM2_CPMFSMSR1 0x418
29 #define CPMFSMSR_FSM_STATE_MASK 0x7f
31 DECLARE_GLOBAL_DATA_PTR;
33 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
36 * Bit[1] of the descriptor indicates the descriptor type,
37 * and bit[0] indicates whether the descriptor is valid.
39 #define PMD_TYPE_TABLE 0x3
40 #define PMD_TYPE_SECT 0x1
43 #define PMD_ATTRINDX(t) ((t) << 2)
46 #define PMD_SECT_AF (1 << 10)
48 #define BLOCK_SIZE_L1 (1UL << 30)
49 #define BLOCK_SIZE_L2 (1UL << 21)
52 #define TTBCR_EAE (1 << 31)
53 #define TTBCR_T0SZ(x) ((x) << 0)
54 #define TTBCR_T1SZ(x) ((x) << 16)
55 #define TTBCR_USING_TTBR0 (TTBCR_T0SZ(0) | TTBCR_T1SZ(0))
56 #define TTBCR_IRGN0_NC (0 << 8)
57 #define TTBCR_IRGN0_WBWA (1 << 8)
58 #define TTBCR_IRGN0_WT (2 << 8)
59 #define TTBCR_IRGN0_WBNWA (3 << 8)
60 #define TTBCR_IRGN0_MASK (3 << 8)
61 #define TTBCR_ORGN0_NC (0 << 10)
62 #define TTBCR_ORGN0_WBWA (1 << 10)
63 #define TTBCR_ORGN0_WT (2 << 10)
64 #define TTBCR_ORGN0_WBNWA (3 << 10)
65 #define TTBCR_ORGN0_MASK (3 << 10)
66 #define TTBCR_SHARED_NON (0 << 12)
67 #define TTBCR_SHARED_OUTER (2 << 12)
68 #define TTBCR_SHARED_INNER (3 << 12)
69 #define TTBCR_EPD0 (0 << 7)
70 #define TTBCR (TTBCR_SHARED_NON | \
77 * Memory region attributes for LPAE (defined in pgtable):
82 * UNCACHED 000 00000000
83 * BUFFERABLE 001 01000100
85 * WRITETHROUGH 010 10101010
86 * WRITEBACK 011 11101110
87 * DEV_CACHED 011 11101110
88 * DEV_SHARED 100 00000100
89 * DEV_NONSHARED 100 00000100
92 * WRITEALLOC 111 11111111
94 #define MT_MAIR0 0xeeaa4400
95 #define MT_MAIR1 0xff000004
96 #define MT_STRONLY_ORDER 0
97 #define MT_NORMAL_NC 1
98 #define MT_DEVICE_MEM 4
101 /* The phy_addr must be aligned to 4KB */
102 static inline void set_pgtable(u32 *page_table, u32 index, u32 phy_addr)
104 u32 value = phy_addr | PMD_TYPE_TABLE;
106 page_table[2 * index] = value;
107 page_table[2 * index + 1] = 0;
110 /* The phy_addr must be aligned to 4KB */
111 static inline void set_pgsection(u32 *page_table, u32 index, u64 phy_addr,
116 value = phy_addr | PMD_TYPE_SECT | PMD_SECT_AF;
117 value |= PMD_ATTRINDX(memory_type);
118 page_table[2 * index] = value & 0xFFFFFFFF;
119 page_table[2 * index + 1] = (value >> 32) & 0xFFFFFFFF;
123 * Start MMU after DDR is available, we create MMU table in DRAM.
124 * The base address of TTLB is gd->arch.tlb_addr. We use two
125 * levels of translation tables here to cover 40-bit address space.
127 * The TTLBs are located at PHY 2G~4G.
134 * |-------| <---- 0x24000000
135 * |///////| ===> 192MB VA map for PCIe1 with offset 0x40_0000_0000
136 * |-------| <---- 0x300000000
138 * |-------| <---- 0x34000000
139 * |///////| ===> 192MB VA map for PCIe2 with offset 0x48_0000_0000
140 * |-------| <---- 0x40000000
142 * |-------| <---- 0x80000000 DDR0 space start
144 *.|\\\\\\\| ===> 2GB VA map for 2GB DDR0 Memory space
146 * ------- <---- 4GB DDR0 space end
148 static void mmu_setup(void)
150 u32 *level0_table = (u32 *)gd->arch.tlb_addr;
151 u32 *level1_table = (u32 *)(gd->arch.tlb_addr + 0x1000);
156 /* Level 0 Table 2-3 are used to map DDR */
157 set_pgsection(level0_table, 3, 3 * BLOCK_SIZE_L1, MT_NORMAL);
158 set_pgsection(level0_table, 2, 2 * BLOCK_SIZE_L1, MT_NORMAL);
159 /* Level 0 Table 1 is used to map device */
160 set_pgsection(level0_table, 1, 1 * BLOCK_SIZE_L1, MT_DEVICE_MEM);
161 /* Level 0 Table 0 is used to map device including PCIe MEM */
162 set_pgtable(level0_table, 0, (u32)level1_table);
164 /* Level 1 has 512 entries */
165 for (i = 0; i < 512; i++) {
166 /* Mapping for PCIe 1 */
167 if (va_start >= CONFIG_SYS_PCIE1_VIRT_ADDR &&
168 va_start < (CONFIG_SYS_PCIE1_VIRT_ADDR +
169 CONFIG_SYS_PCIE_MMAP_SIZE))
170 set_pgsection(level1_table, i,
171 CONFIG_SYS_PCIE1_PHYS_BASE + va_start,
173 /* Mapping for PCIe 2 */
174 else if (va_start >= CONFIG_SYS_PCIE2_VIRT_ADDR &&
175 va_start < (CONFIG_SYS_PCIE2_VIRT_ADDR +
176 CONFIG_SYS_PCIE_MMAP_SIZE))
177 set_pgsection(level1_table, i,
178 CONFIG_SYS_PCIE2_PHYS_BASE + va_start,
181 set_pgsection(level1_table, i,
184 va_start += BLOCK_SIZE_L2;
187 asm volatile("dsb sy;isb");
188 asm volatile("mcr p15, 0, %0, c2, c0, 2" /* Write RT to TTBCR */
189 : : "r" (TTBCR) : "memory");
190 asm volatile("mcrr p15, 0, %0, %1, c2" /* TTBR 0 */
191 : : "r" ((u32)level0_table), "r" (0) : "memory");
192 asm volatile("mcr p15, 0, %0, c10, c2, 0" /* write MAIR 0 */
193 : : "r" (MT_MAIR0) : "memory");
194 asm volatile("mcr p15, 0, %0, c10, c2, 1" /* write MAIR 1 */
195 : : "r" (MT_MAIR1) : "memory");
197 /* Set the access control to all-supervisor */
198 asm volatile("mcr p15, 0, %0, c3, c0, 0"
207 * This function is called from lib/board.c. It recreates MMU
208 * table in main memory. MMU and i/d-cache are enabled here.
210 void enable_caches(void)
212 /* Invalidate all TLB */
213 mmu_page_table_flush(gd->arch.tlb_addr,
214 gd->arch.tlb_addr + gd->arch.tlb_size);
215 /* Set up and enable mmu */
218 /* Invalidate & Enable d-cache */
219 invalidate_dcache_all();
220 set_cr(get_cr() | CR_C);
222 #endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
227 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
229 return in_be32(&gur->svr);
232 #if defined(CONFIG_DISPLAY_CPUINFO)
233 int print_cpuinfo(void)
235 char buf1[32], buf2[32];
236 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
237 unsigned int svr, major, minor, ver, i;
239 svr = in_be32(&gur->svr);
240 major = SVR_MAJ(svr);
241 minor = SVR_MIN(svr);
243 puts("CPU: Freescale LayerScape ");
245 ver = SVR_SOC_VER(svr);
247 case SOC_VER_SLS1020:
264 if (IS_E_PROCESSOR(svr) && (ver != SOC_VER_SLS1020))
267 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
269 puts("Clock Configuration:");
271 printf("\n CPU0(ARMV7):%-4s MHz, ", strmhz(buf1, gd->cpu_clk));
272 printf("\n Bus:%-4s MHz, ", strmhz(buf1, gd->bus_clk));
273 printf("DDR:%-4s MHz (%s MT/s data rate), ",
274 strmhz(buf1, gd->mem_clk/2), strmhz(buf2, gd->mem_clk));
277 /* Display the RCW, so that no one gets confused as to what RCW
278 * we're actually using for this boot.
280 puts("Reset Configuration Word (RCW):");
281 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
282 u32 rcw = in_be32(&gur->rcwsr[i]);
285 printf("\n %08x:", i * 4);
286 printf(" %08x", rcw);
294 #ifdef CONFIG_FSL_ESDHC
295 int cpu_mmc_init(bd_t *bis)
297 return fsl_esdhc_mmc_init(bis);
301 int cpu_eth_init(bd_t *bis)
303 #if defined(CONFIG_TSEC_ENET) && !defined(CONFIG_DM_ETH)
304 tsec_standard_init(bis);
310 int arch_cpu_init(void)
312 void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
314 (void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
315 struct ccsr_scfg *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
319 * The RCPM FSM state may not be reset after power-on.
322 state = in_be32(rcpm2_base + DCSR_RCPM2_CPMFSMSR0) &
323 CPMFSMSR_FSM_STATE_MASK;
325 out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR0, 0x80);
326 out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR0, 0x0);
329 state = in_be32(rcpm2_base + DCSR_RCPM2_CPMFSMSR1) &
330 CPMFSMSR_FSM_STATE_MASK;
332 out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR1, 0x80);
333 out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR1, 0x0);
337 * After wakeup from deep sleep, Clear EPU registers
338 * as early as possible to prevent from possible issue.
339 * It's also safe to clear at normal boot.
341 fsl_epu_clean(epu_base);
343 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR);
348 #ifdef CONFIG_ARMV7_NONSEC
349 /* Set the address at which the secondary core starts from.*/
350 void smp_set_core_boot_addr(unsigned long addr, int corenr)
352 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
354 out_be32(&gur->scratchrw[0], addr);
357 /* Release the secondary core from holdoff state and kick it */
358 void smp_kick_all_cpus(void)
360 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
362 out_be32(&gur->brrl, 0x2);
365 * LS1 STANDBYWFE is not captured outside the ARM module in the soc.
366 * So add a delay to wait bootrom execute WFE.
374 void reset_cpu(ulong addr)
376 struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
378 clrbits_be16(&wdog->wcr, WCR_SRS);
382 * Let the watchdog trigger
387 void arch_preboot_os(void)
391 /* Disable PL1 Physical Timer */
392 asm("mrc p15, 0, %0, c14, c2, 1" : "=r" (ctrl));
393 ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
394 asm("mcr p15, 0, %0, c14, c2, 1" : : "r" (ctrl));