1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2009 DENX Software Engineering
4 * Author: John Rigby <jrigby@gmail.com>
6 * Based on mx27/generic.c:
7 * Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
8 * Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
12 #include <clock_legacy.h>
18 #include <asm/arch-imx/cpu.h>
19 #include <asm/arch/imx-regs.h>
20 #include <asm/arch/clock.h>
22 #ifdef CONFIG_FSL_ESDHC_IMX
23 #include <fsl_esdhc_imx.h>
25 DECLARE_GLOBAL_DATA_PTR;
29 * get the system pll clock in Hz
31 * mfi + mfn / (mfd +1)
32 * f = 2 * f_ref * --------------------
35 static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
37 unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT)
39 int mfn = (pll >> CCM_PLL_MFN_SHIFT)
41 unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT)
43 unsigned int pd = (pll >> CCM_PLL_PD_SHIFT)
46 mfi = mfi <= 5 ? 5 : mfi;
47 mfn = mfn >= 512 ? mfn - 1024 : mfn;
51 return lldiv(2 * (u64) f_ref * (mfi * mfd + mfn),
55 static ulong imx_get_mpllclk(void)
57 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
58 ulong fref = MXC_HCLK;
60 return imx_decode_pll(readl(&ccm->mpctl), fref);
63 static ulong imx_get_upllclk(void)
65 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
66 ulong fref = MXC_HCLK;
68 return imx_decode_pll(readl(&ccm->upctl), fref);
71 static ulong imx_get_armclk(void)
73 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
74 ulong cctl = readl(&ccm->cctl);
75 ulong fref = imx_get_mpllclk();
78 if (cctl & CCM_CCTL_ARM_SRC)
79 fref = lldiv((u64) fref * 3, 4);
81 div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT)
82 & CCM_CCTL_ARM_DIV_MASK) + 1;
87 static ulong imx_get_ahbclk(void)
89 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
90 ulong cctl = readl(&ccm->cctl);
91 ulong fref = imx_get_armclk();
94 div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT)
95 & CCM_CCTL_AHB_DIV_MASK) + 1;
100 static ulong imx_get_ipgclk(void)
102 return imx_get_ahbclk() / 2;
105 static ulong imx_get_perclk(int clk)
107 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
108 ulong fref = readl(&ccm->mcr) & (1 << clk) ? imx_get_upllclk() :
112 div = readl(&ccm->pcdr[CCM_PERCLK_REG(clk)]);
113 div = ((div >> CCM_PERCLK_SHIFT(clk)) & CCM_PERCLK_MASK) + 1;
118 int imx_set_perclk(enum mxc_clock clk, bool from_upll, unsigned int freq)
120 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
121 ulong fref = from_upll ? imx_get_upllclk() : imx_get_ahbclk();
122 ulong div = (fref + freq - 1) / freq;
124 if (clk > MXC_UART_CLK || !div || --div > CCM_PERCLK_MASK)
127 clrsetbits_le32(&ccm->pcdr[CCM_PERCLK_REG(clk)],
128 CCM_PERCLK_MASK << CCM_PERCLK_SHIFT(clk),
129 div << CCM_PERCLK_SHIFT(clk));
131 setbits_le32(&ccm->mcr, 1 << clk);
133 clrbits_le32(&ccm->mcr, 1 << clk);
137 unsigned int mxc_get_clock(enum mxc_clock clk)
139 if (clk >= MXC_CLK_NUM)
143 return imx_get_armclk();
145 return imx_get_ahbclk();
149 return imx_get_ipgclk();
151 return imx_get_perclk(clk);
155 u32 get_cpu_rev(void)
158 u32 system_rev = 0x25000;
160 /* read SREV register from IIM module */
161 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
162 srev = readl(&iim->iim_srev);
166 system_rev |= CHIP_REV_1_0;
169 system_rev |= CHIP_REV_1_1;
172 system_rev |= CHIP_REV_1_2;
175 system_rev |= 0x8000;
182 #if defined(CONFIG_DISPLAY_CPUINFO)
183 static char *get_reset_cause(void)
185 /* read RCSR register from CCM module */
186 struct ccm_regs *ccm =
187 (struct ccm_regs *)IMX_CCM_BASE;
189 u32 cause = readl(&ccm->rcsr) & 0x0f;
195 else if ((cause & 2) == 2)
197 else if ((cause & 4) == 4)
199 else if ((cause & 8) == 8)
202 return "unknown reset";
206 int print_cpuinfo(void)
209 u32 cpurev = get_cpu_rev();
211 printf("CPU: Freescale i.MX25 rev%d.%d%s at %s MHz\n",
212 (cpurev & 0xF0) >> 4, (cpurev & 0x0F),
213 ((cpurev & 0x8000) ? " unknown" : ""),
214 strmhz(buf, imx_get_armclk()));
215 printf("Reset cause: %s\n", get_reset_cause());
220 #if defined(CONFIG_FEC_MXC)
222 * Initializes on-chip ethernet controllers.
223 * to override, implement board_eth_init()
225 int cpu_eth_init(bd_t *bis)
227 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
230 val = readl(&ccm->cgr0);
232 writel(val, &ccm->cgr0);
233 return fecmxc_initialize(bis);
239 #ifdef CONFIG_FSL_ESDHC_IMX
240 #if CONFIG_SYS_FSL_ESDHC_ADDR == IMX_MMC_SDHC2_BASE
241 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
243 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
249 #ifdef CONFIG_FSL_ESDHC_IMX
251 * Initializes on-chip MMC controllers.
252 * to override, implement board_mmc_init()
254 int cpu_mmc_init(bd_t *bis)
256 return fsl_esdhc_mmc_init(bis);
260 #ifdef CONFIG_FEC_MXC
261 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
264 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
265 struct fuse_bank *bank = &iim->bank[0];
266 struct fuse_bank0_regs *fuse =
267 (struct fuse_bank0_regs *)bank->fuse_regs;
269 for (i = 0; i < 6; i++)
270 mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
272 #endif /* CONFIG_FEC_MXC */