1 // SPDX-License-Identifier: GPL-2.0+
4 * Sascha Hauer, Pengutronix
6 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
10 #include <clock_legacy.h>
14 #include <linux/errno.h>
15 #include <asm/arch/imx-regs.h>
16 #include <asm/arch/crm_regs.h>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/sys_proto.h>
19 #ifdef CONFIG_FSL_ESDHC_IMX
20 #include <fsl_esdhc_imx.h>
25 #define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel))
26 #define CLK_CODE_ARM(c) (((c) >> 16) & 0xFF)
27 #define CLK_CODE_AHB(c) (((c) >> 8) & 0xFF)
28 #define CLK_CODE_PATH(c) ((c) & 0xFF)
30 #define CCM_GET_DIVIDER(x, m, o) (((x) & (m)) >> (o))
32 #ifdef CONFIG_FSL_ESDHC_IMX
33 DECLARE_GLOBAL_DATA_PTR;
36 static int g_clk_mux_auto[8] = {
37 CLK_CODE(1, 3, 0), CLK_CODE(1, 2, 1), CLK_CODE(2, 1, 1), -1,
38 CLK_CODE(1, 6, 0), CLK_CODE(1, 4, 1), CLK_CODE(2, 2, 1), -1,
41 static int g_clk_mux_consumer[16] = {
42 CLK_CODE(1, 4, 0), CLK_CODE(1, 3, 1), CLK_CODE(1, 3, 1), -1,
43 -1, -1, CLK_CODE(4, 1, 0), CLK_CODE(1, 5, 0),
44 CLK_CODE(1, 8, 1), CLK_CODE(1, 6, 1), CLK_CODE(2, 4, 0), -1,
45 -1, -1, CLK_CODE(4, 2, 0), -1,
48 static int hsp_div_table[3][16] = {
49 {4, 3, 2, -1, -1, -1, 1, 5, 4, 3, 2, -1, -1, -1, 1, -1},
50 {-1, -1, -1, -1, -1, -1, -1, -1, 8, 6, 4, -1, -1, -1, 2, -1},
51 {3, -1, -1, -1, -1, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1},
57 struct iim_regs *iim =
58 (struct iim_regs *)IIM_BASE_ADDR;
59 reg = readl(&iim->iim_srev);
61 reg = readw(ROMPATCH_REV);
67 return 0x35000 + (reg & 0xFF);
70 static u32 get_arm_div(u32 pdr0, u32 *fi, u32 *fd)
73 if (pdr0 & MXC_CCM_PDR0_AUTO_CON) {
74 pclk_mux = g_clk_mux_consumer +
75 ((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >>
76 MXC_CCM_PDR0_CON_MUX_DIV_OFFSET);
78 pclk_mux = g_clk_mux_auto +
79 ((pdr0 & MXC_CCM_PDR0_AUTO_MUX_DIV_MASK) >>
80 MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET);
83 if ((*pclk_mux) == -1)
87 if (!CLK_CODE_PATH(*pclk_mux)) {
89 return CLK_CODE_ARM(*pclk_mux);
91 if (pdr0 & MXC_CCM_PDR0_AUTO_CON) {
99 return CLK_CODE_ARM(*pclk_mux);
102 static int get_ahb_div(u32 pdr0)
106 pclk_mux = g_clk_mux_consumer +
107 ((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >>
108 MXC_CCM_PDR0_CON_MUX_DIV_OFFSET);
110 if ((*pclk_mux) == -1)
113 return CLK_CODE_AHB(*pclk_mux);
116 static u32 decode_pll(u32 reg, u32 infreq)
118 u32 mfi = (reg >> 10) & 0xf;
119 s32 mfn = reg & 0x3ff;
120 u32 mfd = (reg >> 16) & 0x3ff;
121 u32 pd = (reg >> 26) & 0xf;
123 mfi = mfi <= 5 ? 5 : mfi;
124 mfn = mfn >= 512 ? mfn - 1024 : mfn;
128 return lldiv(2 * (u64)infreq * (mfi * mfd + mfn),
132 static u32 get_mcu_main_clk(void)
134 u32 arm_div = 0, fi = 0, fd = 0;
135 struct ccm_regs *ccm =
136 (struct ccm_regs *)IMX_CCM_BASE;
137 arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd);
138 fi *= decode_pll(readl(&ccm->mpctl), MXC_HCLK);
139 return fi / (arm_div * fd);
142 static u32 get_ipg_clk(void)
144 u32 freq = get_mcu_main_clk();
145 struct ccm_regs *ccm =
146 (struct ccm_regs *)IMX_CCM_BASE;
147 u32 pdr0 = readl(&ccm->pdr0);
149 return freq / (get_ahb_div(pdr0) * 2);
152 static u32 get_ipg_per_clk(void)
154 u32 freq = get_mcu_main_clk();
155 struct ccm_regs *ccm =
156 (struct ccm_regs *)IMX_CCM_BASE;
157 u32 pdr0 = readl(&ccm->pdr0);
158 u32 pdr4 = readl(&ccm->pdr4);
160 if (pdr0 & MXC_CCM_PDR0_PER_SEL) {
161 div = CCM_GET_DIVIDER(pdr4,
162 MXC_CCM_PDR4_PER0_PODF_MASK,
163 MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1;
165 div = CCM_GET_DIVIDER(pdr0,
166 MXC_CCM_PDR0_PER_PODF_MASK,
167 MXC_CCM_PDR0_PER_PODF_OFFSET) + 1;
168 div *= get_ahb_div(pdr0);
173 u32 imx_get_uartclk(void)
176 struct ccm_regs *ccm =
177 (struct ccm_regs *)IMX_CCM_BASE;
178 u32 pdr4 = readl(&ccm->pdr4);
180 if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U)
181 freq = get_mcu_main_clk();
183 freq = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
184 freq /= CCM_GET_DIVIDER(pdr4,
185 MXC_CCM_PDR4_UART_PODF_MASK,
186 MXC_CCM_PDR4_UART_PODF_OFFSET) + 1;
190 unsigned int mxc_get_main_clock(enum mxc_main_clock clk)
192 u32 nfc_pdf, hsp_podf;
193 u32 pll, ret_val = 0, usb_podf;
194 struct ccm_regs *ccm =
195 (struct ccm_regs *)IMX_CCM_BASE;
197 u32 reg = readl(&ccm->pdr0);
198 u32 reg4 = readl(&ccm->pdr4);
204 ret_val = get_mcu_main_clk();
207 ret_val = get_mcu_main_clk();
210 if (reg & CLKMODE_CONSUMER) {
211 hsp_podf = (reg >> 20) & 0x3;
212 pll = get_mcu_main_clk();
213 hsp_podf = hsp_div_table[hsp_podf][(reg>>16)&0xF];
215 ret_val = pll / hsp_podf;
217 puts("mismatch HSP with ARM clock setting\n");
221 ret_val = get_mcu_main_clk();
225 ret_val = get_ipg_clk();
228 ret_val = get_ipg_per_clk();
231 nfc_pdf = (reg4 >> 28) & 0xF;
232 pll = get_mcu_main_clk();
234 ret_val = pll / (nfc_pdf + 1);
237 usb_podf = (reg4 >> 22) & 0x3F;
239 pll = get_mcu_main_clk();
241 pll = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
243 ret_val = pll / (usb_podf + 1);
246 printf("Unknown clock: %d\n", clk);
252 unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk)
254 u32 ret_val = 0, pdf, pre_pdf, clk_sel;
255 struct ccm_regs *ccm =
256 (struct ccm_regs *)IMX_CCM_BASE;
257 u32 mpdr2 = readl(&ccm->pdr2);
258 u32 mpdr3 = readl(&ccm->pdr3);
259 u32 mpdr4 = readl(&ccm->pdr4);
265 clk_sel = mpdr3 & (1 << 14);
266 pdf = (mpdr4 >> 10) & 0x3F;
267 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
268 decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
271 pre_pdf = (mpdr2 >> 24) & 0x7;
273 clk_sel = mpdr2 & (1 << 6);
274 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
275 decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
276 ((pre_pdf + 1) * (pdf + 1));
279 pre_pdf = (mpdr2 >> 27) & 0x7;
280 pdf = (mpdr2 >> 8) & 0x3F;
281 clk_sel = mpdr2 & (1 << 6);
282 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
283 decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
284 ((pre_pdf + 1) * (pdf + 1));
287 clk_sel = mpdr2 & (1 << 7);
288 pdf = (mpdr2 >> 16) & 0x3F;
289 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
290 decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
293 pre_pdf = readl(&ccm->pdr1);
294 clk_sel = (pre_pdf & 0x80);
295 pdf = (pre_pdf >> 22) & 0x3F;
296 pre_pdf = (pre_pdf >> 28) & 0x7;
297 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
298 decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
299 ((pre_pdf + 1) * (pdf + 1));
302 clk_sel = mpdr3 & 0x40;
304 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
305 decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
308 clk_sel = mpdr3 & 0x40;
309 pdf = (mpdr3 >> 8) & 0x3F;
310 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
311 decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
314 clk_sel = mpdr3 & 0x40;
315 pdf = (mpdr3 >> 16) & 0x3F;
316 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
317 decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
320 clk_sel = mpdr3 & 0x400000;
321 pre_pdf = (mpdr3 >> 29) & 0x7;
322 pdf = (mpdr3 >> 23) & 0x3F;
323 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
324 decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
325 ((pre_pdf + 1) * (pdf + 1));
328 printf("%s(): This clock: %d not supported yet\n",
336 unsigned int mxc_get_clock(enum mxc_clock clk)
340 return get_mcu_main_clk();
344 return get_ipg_clk();
347 return get_ipg_per_clk();
349 return imx_get_uartclk();
351 return mxc_get_peri_clock(ESDHC1_CLK);
353 return mxc_get_peri_clock(ESDHC2_CLK);
355 return mxc_get_peri_clock(ESDHC3_CLK);
357 return mxc_get_main_clock(USB_CLK);
359 return get_ipg_clk();
361 return get_ipg_clk();
366 #ifdef CONFIG_FEC_MXC
368 * The MX35 has no fuse for MAC, return a NULL MAC
370 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
375 u32 imx_get_fecclk(void)
377 return mxc_get_clock(MXC_IPG_CLK);
381 int do_mx35_showclocks(cmd_tbl_t *cmdtp,
382 int flag, int argc, char * const argv[])
384 u32 cpufreq = get_mcu_main_clk();
385 printf("mx35 cpu clock: %dMHz\n", cpufreq / 1000000);
386 printf("ipg clock : %dHz\n", get_ipg_clk());
387 printf("ipg per clock : %dHz\n", get_ipg_per_clk());
388 printf("uart clock : %dHz\n", mxc_get_clock(MXC_UART_CLK));
394 clocks, CONFIG_SYS_MAXARGS, 1, do_mx35_showclocks,
399 #if defined(CONFIG_DISPLAY_CPUINFO)
400 static char *get_reset_cause(void)
402 /* read RCSR register from CCM module */
403 struct ccm_regs *ccm =
404 (struct ccm_regs *)IMX_CCM_BASE;
406 u32 cause = readl(&ccm->rcsr) & 0x0F;
418 return "unknown reset";
422 int print_cpuinfo(void)
424 u32 srev = get_cpu_rev();
426 printf("CPU: Freescale i.MX35 rev %d.%d at %d MHz.\n",
427 (srev & 0xF0) >> 4, (srev & 0x0F),
428 get_mcu_main_clk() / 1000000);
430 printf("Reset cause: %s\n", get_reset_cause());
437 * Initializes on-chip ethernet controllers.
438 * to override, implement board_eth_init()
440 int cpu_eth_init(bd_t *bis)
444 #if defined(CONFIG_FEC_MXC)
445 rc = fecmxc_initialize(bis);
451 #ifdef CONFIG_FSL_ESDHC_IMX
453 * Initializes on-chip MMC controllers.
454 * to override, implement board_mmc_init()
456 int cpu_mmc_init(bd_t *bis)
458 return fsl_esdhc_mmc_init(bis);
464 #ifdef CONFIG_FSL_ESDHC_IMX
465 #if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
466 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
467 #elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
468 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
470 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
476 #define RCSR_MEM_CTL_WEIM 0
477 #define RCSR_MEM_CTL_NAND 1
478 #define RCSR_MEM_CTL_ATA 2
479 #define RCSR_MEM_CTL_EXPANSION 3
480 #define RCSR_MEM_TYPE_NOR 0
481 #define RCSR_MEM_TYPE_ONENAND 2
482 #define RCSR_MEM_TYPE_SD 0
483 #define RCSR_MEM_TYPE_I2C 2
484 #define RCSR_MEM_TYPE_SPI 3
486 u32 spl_boot_device(void)
488 struct ccm_regs *ccm =
489 (struct ccm_regs *)IMX_CCM_BASE;
491 u32 rcsr = readl(&ccm->rcsr);
492 u32 mem_type, mem_ctl;
494 /* In external mode, no boot device is returned */
495 if ((rcsr >> 10) & 0x03)
496 return BOOT_DEVICE_NONE;
498 mem_ctl = (rcsr >> 25) & 0x03;
499 mem_type = (rcsr >> 23) & 0x03;
502 case RCSR_MEM_CTL_WEIM:
504 case RCSR_MEM_TYPE_NOR:
505 return BOOT_DEVICE_NOR;
506 case RCSR_MEM_TYPE_ONENAND:
507 return BOOT_DEVICE_ONENAND;
509 return BOOT_DEVICE_NONE;
511 case RCSR_MEM_CTL_NAND:
512 return BOOT_DEVICE_NAND;
513 case RCSR_MEM_CTL_EXPANSION:
515 case RCSR_MEM_TYPE_SD:
516 return BOOT_DEVICE_MMC1;
517 case RCSR_MEM_TYPE_I2C:
518 return BOOT_DEVICE_I2C;
519 case RCSR_MEM_TYPE_SPI:
520 return BOOT_DEVICE_SPI;
522 return BOOT_DEVICE_NONE;
526 return BOOT_DEVICE_NONE;