2 * linux/arch/arm/common/timer-sp.c
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include <linux/clocksource.h>
22 #include <linux/clockchips.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
27 #include <asm/hardware/arm_timer.h>
30 * These timers are currently always setup to be clocked at 1MHz.
32 #define TIMER_FREQ_KHZ (1000)
33 #define TIMER_RELOAD (TIMER_FREQ_KHZ * 1000 / HZ)
35 static void __iomem *clksrc_base;
37 static cycle_t sp804_read(struct clocksource *cs)
39 return ~readl(clksrc_base + TIMER_VALUE);
42 static struct clocksource clocksource_sp804 = {
46 .mask = CLOCKSOURCE_MASK(32),
48 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
51 void __init sp804_clocksource_init(void __iomem *base)
53 struct clocksource *cs = &clocksource_sp804;
57 /* setup timer 0 as free-running clocksource */
58 writel(0, clksrc_base + TIMER_CTRL);
59 writel(0xffffffff, clksrc_base + TIMER_LOAD);
60 writel(0xffffffff, clksrc_base + TIMER_VALUE);
61 writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
62 clksrc_base + TIMER_CTRL);
64 cs->mult = clocksource_khz2mult(TIMER_FREQ_KHZ, cs->shift);
65 clocksource_register(cs);
69 static void __iomem *clkevt_base;
72 * IRQ handler for the timer
74 static irqreturn_t sp804_timer_interrupt(int irq, void *dev_id)
76 struct clock_event_device *evt = dev_id;
78 /* clear the interrupt */
79 writel(1, clkevt_base + TIMER_INTCLR);
81 evt->event_handler(evt);
86 static void sp804_set_mode(enum clock_event_mode mode,
87 struct clock_event_device *evt)
89 unsigned long ctrl = TIMER_CTRL_32BIT | TIMER_CTRL_IE;
91 writel(ctrl, clkevt_base + TIMER_CTRL);
94 case CLOCK_EVT_MODE_PERIODIC:
95 writel(TIMER_RELOAD, clkevt_base + TIMER_LOAD);
96 ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
99 case CLOCK_EVT_MODE_ONESHOT:
100 /* period set, and timer enabled in 'next_event' hook */
101 ctrl |= TIMER_CTRL_ONESHOT;
104 case CLOCK_EVT_MODE_UNUSED:
105 case CLOCK_EVT_MODE_SHUTDOWN:
110 writel(ctrl, clkevt_base + TIMER_CTRL);
113 static int sp804_set_next_event(unsigned long next,
114 struct clock_event_device *evt)
116 unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
118 writel(next, clkevt_base + TIMER_LOAD);
119 writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
124 static struct clock_event_device sp804_clockevent = {
127 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
128 .set_mode = sp804_set_mode,
129 .set_next_event = sp804_set_next_event,
131 .cpumask = cpu_all_mask,
134 static struct irqaction sp804_timer_irq = {
136 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
137 .handler = sp804_timer_interrupt,
138 .dev_id = &sp804_clockevent,
141 void __init sp804_clockevents_init(void __iomem *base, unsigned int timer_irq)
143 struct clock_event_device *evt = &sp804_clockevent;
147 evt->irq = timer_irq;
148 evt->mult = div_sc(TIMER_FREQ_KHZ, NSEC_PER_MSEC, evt->shift);
149 evt->max_delta_ns = clockevent_delta2ns(0xffffffff, evt);
150 evt->min_delta_ns = clockevent_delta2ns(0xf, evt);
152 setup_irq(timer_irq, &sp804_timer_irq);
153 clockevents_register_device(evt);