2 * linux/arch/arm/common/gic.c
4 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * Interrupt architecture for the GIC:
12 * o There is one Interrupt Distributor, which receives interrupts
13 * from system devices and sends them to the Interrupt Controllers.
15 * o There is one CPU Interface per CPU, which sends interrupts sent
16 * by the Distributor, and interrupts generated locally, to the
17 * associated CPU. The base address of the CPU interface is usually
18 * aliased so that the same address points to different chips depending
19 * on the CPU it is accessed from.
21 * Note that IRQs 0-31 are special - they are local to each CPU.
22 * As such, the enable set/clear, pending set/clear and active bit
23 * registers are banked per-cpu for these sources.
25 #include <linux/init.h>
26 #include <linux/kernel.h>
27 #include <linux/list.h>
28 #include <linux/smp.h>
29 #include <linux/cpumask.h>
33 #include <asm/mach/irq.h>
34 #include <asm/hardware/gic.h>
36 static DEFINE_SPINLOCK(irq_controller_lock);
38 /* Address of GIC 0 CPU interface */
39 void __iomem *gic_cpu_base_addr __read_mostly;
41 struct gic_chip_data {
42 unsigned int irq_offset;
43 void __iomem *dist_base;
44 void __iomem *cpu_base;
48 * Supported arch specific GIC irq extension.
49 * Default make them NULL.
51 struct irq_chip gic_arch_extn = {
55 .irq_retrigger = NULL,
64 static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly;
66 static inline void __iomem *gic_dist_base(struct irq_data *d)
68 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
69 return gic_data->dist_base;
72 static inline void __iomem *gic_cpu_base(struct irq_data *d)
74 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
75 return gic_data->cpu_base;
78 static inline unsigned int gic_irq(struct irq_data *d)
80 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
81 return d->irq - gic_data->irq_offset;
85 * Routines to acknowledge, disable and enable interrupts
87 static void gic_mask_irq(struct irq_data *d)
89 u32 mask = 1 << (d->irq % 32);
91 spin_lock(&irq_controller_lock);
92 writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);
93 if (gic_arch_extn.irq_mask)
94 gic_arch_extn.irq_mask(d);
95 spin_unlock(&irq_controller_lock);
98 static void gic_unmask_irq(struct irq_data *d)
100 u32 mask = 1 << (d->irq % 32);
102 spin_lock(&irq_controller_lock);
103 if (gic_arch_extn.irq_unmask)
104 gic_arch_extn.irq_unmask(d);
105 writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4);
106 spin_unlock(&irq_controller_lock);
109 static void gic_eoi_irq(struct irq_data *d)
111 if (gic_arch_extn.irq_eoi) {
112 spin_lock(&irq_controller_lock);
113 gic_arch_extn.irq_eoi(d);
114 spin_unlock(&irq_controller_lock);
117 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
120 static int gic_set_type(struct irq_data *d, unsigned int type)
122 void __iomem *base = gic_dist_base(d);
123 unsigned int gicirq = gic_irq(d);
124 u32 enablemask = 1 << (gicirq % 32);
125 u32 enableoff = (gicirq / 32) * 4;
126 u32 confmask = 0x2 << ((gicirq % 16) * 2);
127 u32 confoff = (gicirq / 16) * 4;
128 bool enabled = false;
131 /* Interrupt configuration for SGIs can't be changed */
135 if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
138 spin_lock(&irq_controller_lock);
140 if (gic_arch_extn.irq_set_type)
141 gic_arch_extn.irq_set_type(d, type);
143 val = readl_relaxed(base + GIC_DIST_CONFIG + confoff);
144 if (type == IRQ_TYPE_LEVEL_HIGH)
146 else if (type == IRQ_TYPE_EDGE_RISING)
150 * As recommended by the spec, disable the interrupt before changing
153 if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
154 writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);
158 writel_relaxed(val, base + GIC_DIST_CONFIG + confoff);
161 writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);
163 spin_unlock(&irq_controller_lock);
168 static int gic_retrigger(struct irq_data *d)
170 if (gic_arch_extn.irq_retrigger)
171 return gic_arch_extn.irq_retrigger(d);
177 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
180 void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
181 unsigned int shift = (d->irq % 4) * 8;
182 unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
185 if (cpu >= 8 || cpu >= nr_cpu_ids)
188 mask = 0xff << shift;
189 bit = 1 << (cpu + shift);
191 spin_lock(&irq_controller_lock);
192 val = readl_relaxed(reg) & ~mask;
193 writel_relaxed(val | bit, reg);
194 spin_unlock(&irq_controller_lock);
196 return IRQ_SET_MASK_OK;
201 static int gic_set_wake(struct irq_data *d, unsigned int on)
205 if (gic_arch_extn.irq_set_wake)
206 ret = gic_arch_extn.irq_set_wake(d, on);
212 #define gic_set_wake NULL
215 static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
217 struct gic_chip_data *chip_data = irq_get_handler_data(irq);
218 struct irq_chip *chip = irq_get_chip(irq);
219 unsigned int cascade_irq, gic_irq;
220 unsigned long status;
222 chained_irq_enter(chip, desc);
224 spin_lock(&irq_controller_lock);
225 status = readl_relaxed(chip_data->cpu_base + GIC_CPU_INTACK);
226 spin_unlock(&irq_controller_lock);
228 gic_irq = (status & 0x3ff);
232 cascade_irq = gic_irq + chip_data->irq_offset;
233 if (unlikely(gic_irq < 32 || gic_irq > 1020 || cascade_irq >= NR_IRQS))
234 do_bad_IRQ(cascade_irq, desc);
236 generic_handle_irq(cascade_irq);
239 chained_irq_exit(chip, desc);
242 static struct irq_chip gic_chip = {
244 .irq_mask = gic_mask_irq,
245 .irq_unmask = gic_unmask_irq,
246 .irq_eoi = gic_eoi_irq,
247 .irq_set_type = gic_set_type,
248 .irq_retrigger = gic_retrigger,
250 .irq_set_affinity = gic_set_affinity,
252 .irq_set_wake = gic_set_wake,
255 void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
257 if (gic_nr >= MAX_GIC_NR)
259 if (irq_set_handler_data(irq, &gic_data[gic_nr]) != 0)
261 irq_set_chained_handler(irq, gic_handle_cascade_irq);
264 static void __init gic_dist_init(struct gic_chip_data *gic,
265 unsigned int irq_start)
267 unsigned int gic_irqs, irq_limit, i;
268 void __iomem *base = gic->dist_base;
269 u32 cpumask = 1 << smp_processor_id();
271 cpumask |= cpumask << 8;
272 cpumask |= cpumask << 16;
274 writel_relaxed(0, base + GIC_DIST_CTRL);
277 * Find out how many interrupts are supported.
278 * The GIC only supports up to 1020 interrupt sources.
280 gic_irqs = readl_relaxed(base + GIC_DIST_CTR) & 0x1f;
281 gic_irqs = (gic_irqs + 1) * 32;
286 * Set all global interrupts to be level triggered, active low.
288 for (i = 32; i < gic_irqs; i += 16)
289 writel_relaxed(0, base + GIC_DIST_CONFIG + i * 4 / 16);
292 * Set all global interrupts to this CPU only.
294 for (i = 32; i < gic_irqs; i += 4)
295 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
298 * Set priority on all global interrupts.
300 for (i = 32; i < gic_irqs; i += 4)
301 writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
304 * Disable all interrupts. Leave the PPI and SGIs alone
305 * as these enables are banked registers.
307 for (i = 32; i < gic_irqs; i += 32)
308 writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
311 * Limit number of interrupts registered to the platform maximum
313 irq_limit = gic->irq_offset + gic_irqs;
314 if (WARN_ON(irq_limit > NR_IRQS))
318 * Setup the Linux IRQ subsystem.
320 for (i = irq_start; i < irq_limit; i++) {
321 irq_set_chip_and_handler(i, &gic_chip, handle_fasteoi_irq);
322 irq_set_chip_data(i, gic);
323 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
326 writel_relaxed(1, base + GIC_DIST_CTRL);
329 static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
331 void __iomem *dist_base = gic->dist_base;
332 void __iomem *base = gic->cpu_base;
336 * Deal with the banked PPI and SGI interrupts - disable all
337 * PPI interrupts, ensure all SGI interrupts are enabled.
339 writel_relaxed(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
340 writel_relaxed(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
343 * Set priority on PPI and SGI interrupts
345 for (i = 0; i < 32; i += 4)
346 writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
348 writel_relaxed(0xf0, base + GIC_CPU_PRIMASK);
349 writel_relaxed(1, base + GIC_CPU_CTRL);
352 void __init gic_init(unsigned int gic_nr, unsigned int irq_start,
353 void __iomem *dist_base, void __iomem *cpu_base)
355 struct gic_chip_data *gic;
357 BUG_ON(gic_nr >= MAX_GIC_NR);
359 gic = &gic_data[gic_nr];
360 gic->dist_base = dist_base;
361 gic->cpu_base = cpu_base;
362 gic->irq_offset = (irq_start - 1) & ~31;
365 gic_cpu_base_addr = cpu_base;
367 gic_dist_init(gic, irq_start);
371 void __cpuinit gic_secondary_init(unsigned int gic_nr)
373 BUG_ON(gic_nr >= MAX_GIC_NR);
375 gic_cpu_init(&gic_data[gic_nr]);
378 void __cpuinit gic_enable_ppi(unsigned int irq)
382 local_irq_save(flags);
383 irq_set_status_flags(irq, IRQ_NOPROBE);
384 gic_unmask_irq(irq_get_irq_data(irq));
385 local_irq_restore(flags);
389 void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
391 unsigned long map = *cpus_addr(*mask);
394 * Ensure that stores to Normal memory are visible to the
395 * other CPUs before issuing the IPI.
399 /* this always happens on GIC0 */
400 writel_relaxed(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT);