arch/arm/boot/dts/vf610-twr.dts

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9
  10 /dts-v1/;
  11 #include "vf610.dtsi"
  12
  13 / {
  14         model = "VF610 Tower Board";
  15         compatible = "fsl,vf610-twr", "fsl,vf610";
  16
  17         chosen {
  18                 bootargs = "console=ttyLP1,115200";
  19         };
  20
  21         memory {
  22                 reg = <0x80000000 0x8000000>;
  23         };
  24
  25         clocks {
  26                 audio_ext {
  27                         compatible = "fixed-clock";
  28                         #clock-cells = <0>;
  29                         clock-frequency = <24576000>;
  30                 };
  31
  32                 enet_ext {
  33                         compatible = "fixed-clock";
  34                         #clock-cells = <0>;
  35                         clock-frequency = <50000000>;
  36                 };
  37         };
  38
  39         regulators {
  40                 compatible = "simple-bus";
  41                 #address-cells = <1>;
  42                 #size-cells = <0>;
  43
  44                 reg_3p3v: regulator@0 {
  45                         compatible = "regulator-fixed";
  46                         reg = <0>;
  47                         regulator-name = "3P3V";
  48                         regulator-min-microvolt = <3300000>;
  49                         regulator-max-microvolt = <3300000>;
  50                         regulator-always-on;
  51                 };
  52
  53                 reg_vcc_3v3_mcu: regulator@1 {
  54                         compatible = "regulator-fixed";
  55                         reg = <1>;
  56                         regulator-name = "vcc_3v3_mcu";
  57                         regulator-min-microvolt = <3300000>;
  58                         regulator-max-microvolt = <3300000>;
  59                 };
  60         };
  61
  62         sound {
  63                 compatible = "simple-audio-card";
  64                 simple-audio-card,format = "i2s";
  65                 simple-audio-card,widgets =
  66                         "Microphone", "Microphone Jack",
  67                         "Headphone", "Headphone Jack",
  68                         "Speaker", "Speaker Ext",
  69                         "Line", "Line In Jack";
  70                 simple-audio-card,routing =
  71                         "MIC_IN", "Microphone Jack",
  72                         "Microphone Jack", "Mic Bias",
  73                         "LINE_IN", "Line In Jack",
  74                         "Headphone Jack", "HP_OUT",
  75                         "Speaker Ext", "LINE_OUT";
  76
  77                 simple-audio-card,cpu {
  78                         sound-dai = <&sai2>;
  79                         master-clkdir-out;
  80                         frame-master;
  81                         bitclock-master;
  82                 };
  83
  84                 simple-audio-card,codec {
  85                         sound-dai = <&codec>;
  86                         frame-master;
  87                         bitclock-master;
  88                 };
  89         };
  90 };
  91
  92 &adc0 {
  93         pinctrl-names = "default";
  94         pinctrl-0 = <&pinctrl_adc0_ad5>;
  95         vref-supply = <&reg_vcc_3v3_mcu>;
  96         status = "okay";
  97 };
  98
  99 &dspi0 {
 100         bus-num = <0>;
 101         pinctrl-names = "default";
 102         pinctrl-0 = <&pinctrl_dspi0>;
 103         status = "okay";
 104
 105         sflash: at26df081a@0 {
 106                 #address-cells = <1>;
 107                 #size-cells = <1>;
 108                 compatible = "atmel,at26df081a";
 109                 spi-max-frequency = <16000000>;
 110                 spi-cpol;
 111                 spi-cpha;
 112                 reg = <0>;
 113         };
 114 };
 115
 116 &fec0 {
 117         phy-mode = "rmii";
 118         pinctrl-names = "default";
 119         pinctrl-0 = <&pinctrl_fec0>;
 120         status = "okay";
 121 };
 122
 123 &fec1 {
 124         phy-mode = "rmii";
 125         pinctrl-names = "default";
 126         pinctrl-0 = <&pinctrl_fec1>;
 127         status = "okay";
 128 };
 129
 130 &i2c0 {
 131         clock-frequency = <100000>;
 132         pinctrl-names = "default";
 133         pinctrl-0 = <&pinctrl_i2c0>;
 134         status = "okay";
 135
 136         codec: sgtl5000@0a {
 137                #sound-dai-cells = <0>;
 138                compatible = "fsl,sgtl5000";
 139                reg = <0x0a>;
 140                VDDA-supply = <&reg_3p3v>;
 141                VDDIO-supply = <&reg_3p3v>;
 142                clocks = <&clks VF610_CLK_SAI2>;
 143        };
 144 };
 145
 146 &iomuxc {
 147         vf610-twr {
 148                 pinctrl_adc0_ad5: adc0ad5grp {
 149                         fsl,pins = <
 150                                 VF610_PAD_PTC30__ADC0_SE5               0xa1
 151                         >;
 152                 };
 153
 154                 pinctrl_dspi0: dspi0grp {
 155                         fsl,pins = <
 156                                 VF610_PAD_PTB19__DSPI0_CS0              0x1182
 157                                 VF610_PAD_PTB20__DSPI0_SIN              0x1181
 158                                 VF610_PAD_PTB21__DSPI0_SOUT             0x1182
 159                                 VF610_PAD_PTB22__DSPI0_SCK              0x1182
 160                         >;
 161                 };
 162
 163                 pinctrl_fec0: fec0grp {
 164                         fsl,pins = <
 165                                 VF610_PAD_PTA6__RMII_CLKIN              0x30d1
 166                                 VF610_PAD_PTC0__ENET_RMII0_MDC          0x30d3
 167                                 VF610_PAD_PTC1__ENET_RMII0_MDIO         0x30d1
 168                                 VF610_PAD_PTC2__ENET_RMII0_CRS          0x30d1
 169                                 VF610_PAD_PTC3__ENET_RMII0_RXD1         0x30d1
 170                                 VF610_PAD_PTC4__ENET_RMII0_RXD0         0x30d1
 171                                 VF610_PAD_PTC5__ENET_RMII0_RXER         0x30d1
 172                                 VF610_PAD_PTC6__ENET_RMII0_TXD1         0x30d2
 173                                 VF610_PAD_PTC7__ENET_RMII0_TXD0         0x30d2
 174                                 VF610_PAD_PTC8__ENET_RMII0_TXEN         0x30d2
 175                         >;
 176                 };
 177
 178                 pinctrl_fec1: fec1grp {
 179                         fsl,pins = <
 180                                 VF610_PAD_PTC9__ENET_RMII1_MDC          0x30d2
 181                                 VF610_PAD_PTC10__ENET_RMII1_MDIO        0x30d3
 182                                 VF610_PAD_PTC11__ENET_RMII1_CRS         0x30d1
 183                                 VF610_PAD_PTC12__ENET_RMII_RXD1         0x30d1
 184                                 VF610_PAD_PTC13__ENET_RMII1_RXD0        0x30d1
 185                                 VF610_PAD_PTC14__ENET_RMII1_RXER        0x30d1
 186                                 VF610_PAD_PTC15__ENET_RMII1_TXD1        0x30d2
 187                                 VF610_PAD_PTC16__ENET_RMII1_TXD0        0x30d2
 188                                 VF610_PAD_PTC17__ENET_RMII1_TXEN        0x30d2
 189                         >;
 190                 };
 191
 192                 pinctrl_i2c0: i2c0grp {
 193                         fsl,pins = <
 194                                 VF610_PAD_PTB14__I2C0_SCL               0x30d3
 195                                 VF610_PAD_PTB15__I2C0_SDA               0x30d3
 196                         >;
 197                 };
 198
 199                 pinctrl_sai2: sai2grp {
 200                         fsl,pins = <
 201                                 VF610_PAD_PTA16__SAI2_TX_BCLK           0x02ed
 202                                 VF610_PAD_PTA18__SAI2_TX_DATA           0x02ee
 203                                 VF610_PAD_PTA19__SAI2_TX_SYNC           0x02ed
 204                                 VF610_PAD_PTA21__SAI2_RX_BCLK           0x02ed
 205                                 VF610_PAD_PTA22__SAI2_RX_DATA           0x02ed
 206                                 VF610_PAD_PTA23__SAI2_RX_SYNC           0x02ed
 207                                 VF610_PAD_PTB18__EXT_AUDIO_MCLK         0x02ed
 208                         >;
 209                 };
 210
 211                 pinctrl_uart1: uart1grp {
 212                         fsl,pins = <
 213                                 VF610_PAD_PTB4__UART1_TX                0x21a2
 214                                 VF610_PAD_PTB5__UART1_RX                0x21a1
 215                         >;
 216                 };
 217         };
 218 };
 219
 220 &sai2 {
 221         #sound-dai-cells = <0>;
 222         pinctrl-names = "default";
 223         pinctrl-0 = <&pinctrl_sai2>;
 224         status = "okay";
 225 };
 226
 227 &uart1 {
 228         pinctrl-names = "default";
 229         pinctrl-0 = <&pinctrl_uart1>;
 230         status = "okay";
 231 };