arch/arm/boot/dts/tegra20.dtsi

   1 /include/ "skeleton.dtsi"
   2
   3 / {
   4         compatible = "nvidia,tegra20";
   5         interrupt-parent = <&intc>;
   6
   7         aliases {
   8                 serial0 = &uarta;
   9                 serial1 = &uartb;
  10                 serial2 = &uartc;
  11                 serial3 = &uartd;
  12                 serial4 = &uarte;
  13         };
  14
  15         host1x {
  16                 compatible = "nvidia,tegra20-host1x", "simple-bus";
  17                 reg = <0x50000000 0x00024000>;
  18                 interrupts = <0 65 0x04   /* mpcore syncpt */
  19                               0 67 0x04>; /* mpcore general */
  20                 clocks = <&tegra_car 28>;
  21
  22                 #address-cells = <1>;
  23                 #size-cells = <1>;
  24
  25                 ranges = <0x54000000 0x54000000 0x04000000>;
  26
  27                 mpe {
  28                         compatible = "nvidia,tegra20-mpe";
  29                         reg = <0x54040000 0x00040000>;
  30                         interrupts = <0 68 0x04>;
  31                         clocks = <&tegra_car 60>;
  32                 };
  33
  34                 vi {
  35                         compatible = "nvidia,tegra20-vi";
  36                         reg = <0x54080000 0x00040000>;
  37                         interrupts = <0 69 0x04>;
  38                         clocks = <&tegra_car 100>;
  39                 };
  40
  41                 epp {
  42                         compatible = "nvidia,tegra20-epp";
  43                         reg = <0x540c0000 0x00040000>;
  44                         interrupts = <0 70 0x04>;
  45                         clocks = <&tegra_car 19>;
  46                 };
  47
  48                 isp {
  49                         compatible = "nvidia,tegra20-isp";
  50                         reg = <0x54100000 0x00040000>;
  51                         interrupts = <0 71 0x04>;
  52                         clocks = <&tegra_car 23>;
  53                 };
  54
  55                 gr2d {
  56                         compatible = "nvidia,tegra20-gr2d";
  57                         reg = <0x54140000 0x00040000>;
  58                         interrupts = <0 72 0x04>;
  59                         clocks = <&tegra_car 21>;
  60                 };
  61
  62                 gr3d {
  63                         compatible = "nvidia,tegra20-gr3d";
  64                         reg = <0x54180000 0x00040000>;
  65                         clocks = <&tegra_car 24>;
  66                 };
  67
  68                 dc@54200000 {
  69                         compatible = "nvidia,tegra20-dc";
  70                         reg = <0x54200000 0x00040000>;
  71                         interrupts = <0 73 0x04>;
  72                         clocks = <&tegra_car 27>, <&tegra_car 121>;
  73                         clock-names = "disp1", "parent";
  74
  75                         rgb {
  76                                 status = "disabled";
  77                         };
  78                 };
  79
  80                 dc@54240000 {
  81                         compatible = "nvidia,tegra20-dc";
  82                         reg = <0x54240000 0x00040000>;
  83                         interrupts = <0 74 0x04>;
  84                         clocks = <&tegra_car 26>, <&tegra_car 121>;
  85                         clock-names = "disp2", "parent";
  86
  87                         rgb {
  88                                 status = "disabled";
  89                         };
  90                 };
  91
  92                 hdmi {
  93                         compatible = "nvidia,tegra20-hdmi";
  94                         reg = <0x54280000 0x00040000>;
  95                         interrupts = <0 75 0x04>;
  96                         clocks = <&tegra_car 51>, <&tegra_car 117>;
  97                         clock-names = "hdmi", "parent";
  98                         status = "disabled";
  99                 };
 100
 101                 tvo {
 102                         compatible = "nvidia,tegra20-tvo";
 103                         reg = <0x542c0000 0x00040000>;
 104                         interrupts = <0 76 0x04>;
 105                         clocks = <&tegra_car 102>;
 106                         status = "disabled";
 107                 };
 108
 109                 dsi {
 110                         compatible = "nvidia,tegra20-dsi";
 111                         reg = <0x54300000 0x00040000>;
 112                         clocks = <&tegra_car 48>;
 113                         status = "disabled";
 114                 };
 115         };
 116
 117         timer@50004600 {
 118                 compatible = "arm,cortex-a9-twd-timer";
 119                 reg = <0x50040600 0x20>;
 120                 interrupts = <1 13 0x304>;
 121         };
 122
 123         cache-controller@50043000 {
 124                 compatible = "arm,pl310-cache";
 125                 reg = <0x50043000 0x1000>;
 126                 arm,data-latency = <5 5 2>;
 127                 arm,tag-latency = <4 4 2>;
 128                 cache-unified;
 129                 cache-level = <2>;
 130         };
 131
 132         intc: interrupt-controller {
 133                 compatible = "arm,cortex-a9-gic";
 134                 reg = <0x50041000 0x1000
 135                        0x50040100 0x0100>;
 136                 interrupt-controller;
 137                 #interrupt-cells = <3>;
 138         };
 139
 140         timer@60005000 {
 141                 compatible = "nvidia,tegra20-timer";
 142                 reg = <0x60005000 0x60>;
 143                 interrupts = <0 0 0x04
 144                               0 1 0x04
 145                               0 41 0x04
 146                               0 42 0x04>;
 147         };
 148
 149         tegra_car: clock {
 150                 compatible = "nvidia,tegra20-car";
 151                 reg = <0x60006000 0x1000>;
 152                 #clock-cells = <1>;
 153         };
 154
 155         apbdma: dma {
 156                 compatible = "nvidia,tegra20-apbdma";
 157                 reg = <0x6000a000 0x1200>;
 158                 interrupts = <0 104 0x04
 159                               0 105 0x04
 160                               0 106 0x04
 161                               0 107 0x04
 162                               0 108 0x04
 163                               0 109 0x04
 164                               0 110 0x04
 165                               0 111 0x04
 166                               0 112 0x04
 167                               0 113 0x04
 168                               0 114 0x04
 169                               0 115 0x04
 170                               0 116 0x04
 171                               0 117 0x04
 172                               0 118 0x04
 173                               0 119 0x04>;
 174                 clocks = <&tegra_car 34>;
 175         };
 176
 177         ahb {
 178                 compatible = "nvidia,tegra20-ahb";
 179                 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
 180         };
 181
 182         gpio: gpio {
 183                 compatible = "nvidia,tegra20-gpio";
 184                 reg = <0x6000d000 0x1000>;
 185                 interrupts = <0 32 0x04
 186                               0 33 0x04
 187                               0 34 0x04
 188                               0 35 0x04
 189                               0 55 0x04
 190                               0 87 0x04
 191                               0 89 0x04>;
 192                 #gpio-cells = <2>;
 193                 gpio-controller;
 194                 #interrupt-cells = <2>;
 195                 interrupt-controller;
 196         };
 197
 198         pinmux: pinmux {
 199                 compatible = "nvidia,tegra20-pinmux";
 200                 reg = <0x70000014 0x10   /* Tri-state registers */
 201                        0x70000080 0x20   /* Mux registers */
 202                        0x700000a0 0x14   /* Pull-up/down registers */
 203                        0x70000868 0xa8>; /* Pad control registers */
 204         };
 205
 206         das {
 207                 compatible = "nvidia,tegra20-das";
 208                 reg = <0x70000c00 0x80>;
 209         };
 210
 211         tegra_i2s1: i2s@70002800 {
 212                 compatible = "nvidia,tegra20-i2s";
 213                 reg = <0x70002800 0x200>;
 214                 interrupts = <0 13 0x04>;
 215                 nvidia,dma-request-selector = <&apbdma 2>;
 216                 clocks = <&tegra_car 11>;
 217                 status = "disabled";
 218         };
 219
 220         tegra_i2s2: i2s@70002a00 {
 221                 compatible = "nvidia,tegra20-i2s";
 222                 reg = <0x70002a00 0x200>;
 223                 interrupts = <0 3 0x04>;
 224                 nvidia,dma-request-selector = <&apbdma 1>;
 225                 clocks = <&tegra_car 18>;
 226                 status = "disabled";
 227         };
 228
 229         /*
 230          * There are two serial driver i.e. 8250 based simple serial
 231          * driver and APB DMA based serial driver for higher baudrate
 232          * and performace. To enable the 8250 based driver, the compatible
 233          * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
 234          * driver, the comptible is "nvidia,tegra20-hsuart".
 235          */
 236         uarta: serial@70006000 {
 237                 compatible = "nvidia,tegra20-uart";
 238                 reg = <0x70006000 0x40>;
 239                 reg-shift = <2>;
 240                 interrupts = <0 36 0x04>;
 241                 nvidia,dma-request-selector = <&apbdma 8>;
 242                 clocks = <&tegra_car 6>;
 243                 status = "disabled";
 244         };
 245
 246         uartb: serial@70006040 {
 247                 compatible = "nvidia,tegra20-uart";
 248                 reg = <0x70006040 0x40>;
 249                 reg-shift = <2>;
 250                 interrupts = <0 37 0x04>;
 251                 nvidia,dma-request-selector = <&apbdma 9>;
 252                 clocks = <&tegra_car 96>;
 253                 status = "disabled";
 254         };
 255
 256         uartc: serial@70006200 {
 257                 compatible = "nvidia,tegra20-uart";
 258                 reg = <0x70006200 0x100>;
 259                 reg-shift = <2>;
 260                 interrupts = <0 46 0x04>;
 261                 nvidia,dma-request-selector = <&apbdma 10>;
 262                 clocks = <&tegra_car 55>;
 263                 status = "disabled";
 264         };
 265
 266         uartd: serial@70006300 {
 267                 compatible = "nvidia,tegra20-uart";
 268                 reg = <0x70006300 0x100>;
 269                 reg-shift = <2>;
 270                 interrupts = <0 90 0x04>;
 271                 nvidia,dma-request-selector = <&apbdma 19>;
 272                 clocks = <&tegra_car 65>;
 273                 status = "disabled";
 274         };
 275
 276         uarte: serial@70006400 {
 277                 compatible = "nvidia,tegra20-uart";
 278                 reg = <0x70006400 0x100>;
 279                 reg-shift = <2>;
 280                 interrupts = <0 91 0x04>;
 281                 nvidia,dma-request-selector = <&apbdma 20>;
 282                 clocks = <&tegra_car 66>;
 283                 status = "disabled";
 284         };
 285
 286         pwm: pwm {
 287                 compatible = "nvidia,tegra20-pwm";
 288                 reg = <0x7000a000 0x100>;
 289                 #pwm-cells = <2>;
 290                 clocks = <&tegra_car 17>;
 291         };
 292
 293         rtc {
 294                 compatible = "nvidia,tegra20-rtc";
 295                 reg = <0x7000e000 0x100>;
 296                 interrupts = <0 2 0x04>;
 297         };
 298
 299         i2c@7000c000 {
 300                 compatible = "nvidia,tegra20-i2c";
 301                 reg = <0x7000c000 0x100>;
 302                 interrupts = <0 38 0x04>;
 303                 #address-cells = <1>;
 304                 #size-cells = <0>;
 305                 clocks = <&tegra_car 12>, <&tegra_car 124>;
 306                 clock-names = "div-clk", "fast-clk";
 307                 status = "disabled";
 308         };
 309
 310         spi@7000c380 {
 311                 compatible = "nvidia,tegra20-sflash";
 312                 reg = <0x7000c380 0x80>;
 313                 interrupts = <0 39 0x04>;
 314                 nvidia,dma-request-selector = <&apbdma 11>;
 315                 #address-cells = <1>;
 316                 #size-cells = <0>;
 317                 clocks = <&tegra_car 43>;
 318                 status = "disabled";
 319         };
 320
 321         i2c@7000c400 {
 322                 compatible = "nvidia,tegra20-i2c";
 323                 reg = <0x7000c400 0x100>;
 324                 interrupts = <0 84 0x04>;
 325                 #address-cells = <1>;
 326                 #size-cells = <0>;
 327                 clocks = <&tegra_car 54>, <&tegra_car 124>;
 328                 clock-names = "div-clk", "fast-clk";
 329                 status = "disabled";
 330         };
 331
 332         i2c@7000c500 {
 333                 compatible = "nvidia,tegra20-i2c";
 334                 reg = <0x7000c500 0x100>;
 335                 interrupts = <0 92 0x04>;
 336                 #address-cells = <1>;
 337                 #size-cells = <0>;
 338                 clocks = <&tegra_car 67>, <&tegra_car 124>;
 339                 clock-names = "div-clk", "fast-clk";
 340                 status = "disabled";
 341         };
 342
 343         i2c@7000d000 {
 344                 compatible = "nvidia,tegra20-i2c-dvc";
 345                 reg = <0x7000d000 0x200>;
 346                 interrupts = <0 53 0x04>;
 347                 #address-cells = <1>;
 348                 #size-cells = <0>;
 349                 clocks = <&tegra_car 47>, <&tegra_car 124>;
 350                 clock-names = "div-clk", "fast-clk";
 351                 status = "disabled";
 352         };
 353
 354         spi@7000d400 {
 355                 compatible = "nvidia,tegra20-slink";
 356                 reg = <0x7000d400 0x200>;
 357                 interrupts = <0 59 0x04>;
 358                 nvidia,dma-request-selector = <&apbdma 15>;
 359                 #address-cells = <1>;
 360                 #size-cells = <0>;
 361                 clocks = <&tegra_car 41>;
 362                 status = "disabled";
 363         };
 364
 365         spi@7000d600 {
 366                 compatible = "nvidia,tegra20-slink";
 367                 reg = <0x7000d600 0x200>;
 368                 interrupts = <0 82 0x04>;
 369                 nvidia,dma-request-selector = <&apbdma 16>;
 370                 #address-cells = <1>;
 371                 #size-cells = <0>;
 372                 clocks = <&tegra_car 44>;
 373                 status = "disabled";
 374         };
 375
 376         spi@7000d800 {
 377                 compatible = "nvidia,tegra20-slink";
 378                 reg = <0x7000d480 0x200>;
 379                 interrupts = <0 83 0x04>;
 380                 nvidia,dma-request-selector = <&apbdma 17>;
 381                 #address-cells = <1>;
 382                 #size-cells = <0>;
 383                 clocks = <&tegra_car 46>;
 384                 status = "disabled";
 385         };
 386
 387         spi@7000da00 {
 388                 compatible = "nvidia,tegra20-slink";
 389                 reg = <0x7000da00 0x200>;
 390                 interrupts = <0 93 0x04>;
 391                 nvidia,dma-request-selector = <&apbdma 18>;
 392                 #address-cells = <1>;
 393                 #size-cells = <0>;
 394                 clocks = <&tegra_car 68>;
 395                 status = "disabled";
 396         };
 397
 398         pmc {
 399                 compatible = "nvidia,tegra20-pmc";
 400                 reg = <0x7000e400 0x400>;
 401         };
 402
 403         memory-controller@7000f000 {
 404                 compatible = "nvidia,tegra20-mc";
 405                 reg = <0x7000f000 0x024
 406                        0x7000f03c 0x3c4>;
 407                 interrupts = <0 77 0x04>;
 408         };
 409
 410         gart {
 411                 compatible = "nvidia,tegra20-gart";
 412                 reg = <0x7000f024 0x00000018    /* controller registers */
 413                        0x58000000 0x02000000>;  /* GART aperture */
 414         };
 415
 416         memory-controller@7000f400 {
 417                 compatible = "nvidia,tegra20-emc";
 418                 reg = <0x7000f400 0x200>;
 419                 #address-cells = <1>;
 420                 #size-cells = <0>;
 421         };
 422
 423         phy1: usb-phy@c5000400 {
 424                 compatible = "nvidia,tegra20-usb-phy";
 425                 reg = <0xc5000400 0x3c00>;
 426                 phy_type = "utmi";
 427                 nvidia,has-legacy-mode;
 428                 clocks = <&tegra_car 22>, <&tegra_car 127>;
 429                 clock-names = "phy", "pll_u";
 430         };
 431
 432         phy2: usb-phy@c5004400 {
 433                 compatible = "nvidia,tegra20-usb-phy";
 434                 reg = <0xc5004400 0x3c00>;
 435                 phy_type = "ulpi";
 436                 clocks = <&tegra_car 94>, <&tegra_car 127>;
 437                 clock-names = "phy", "pll_u";
 438         };
 439
 440         phy3: usb-phy@c5008400 {
 441                 compatible = "nvidia,tegra20-usb-phy";
 442                 reg = <0xc5008400 0x3C00>;
 443                 phy_type = "utmi";
 444                 clocks = <&tegra_car 22>, <&tegra_car 127>;
 445                 clock-names = "phy", "pll_u";
 446         };
 447
 448         usb@c5000000 {
 449                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 450                 reg = <0xc5000000 0x4000>;
 451                 interrupts = <0 20 0x04>;
 452                 phy_type = "utmi";
 453                 nvidia,has-legacy-mode;
 454                 clocks = <&tegra_car 22>;
 455                 nvidia,needs-double-reset;
 456                 nvidia,phy = <&phy1>;
 457                 status = "disabled";
 458         };
 459
 460         usb@c5004000 {
 461                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 462                 reg = <0xc5004000 0x4000>;
 463                 interrupts = <0 21 0x04>;
 464                 phy_type = "ulpi";
 465                 clocks = <&tegra_car 58>;
 466                 nvidia,phy = <&phy2>;
 467                 status = "disabled";
 468         };
 469
 470         usb@c5008000 {
 471                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 472                 reg = <0xc5008000 0x4000>;
 473                 interrupts = <0 97 0x04>;
 474                 phy_type = "utmi";
 475                 clocks = <&tegra_car 59>;
 476                 nvidia,phy = <&phy3>;
 477                 status = "disabled";
 478         };
 479
 480         sdhci@c8000000 {
 481                 compatible = "nvidia,tegra20-sdhci";
 482                 reg = <0xc8000000 0x200>;
 483                 interrupts = <0 14 0x04>;
 484                 clocks = <&tegra_car 14>;
 485                 status = "disabled";
 486         };
 487
 488         sdhci@c8000200 {
 489                 compatible = "nvidia,tegra20-sdhci";
 490                 reg = <0xc8000200 0x200>;
 491                 interrupts = <0 15 0x04>;
 492                 clocks = <&tegra_car 9>;
 493                 status = "disabled";
 494         };
 495
 496         sdhci@c8000400 {
 497                 compatible = "nvidia,tegra20-sdhci";
 498                 reg = <0xc8000400 0x200>;
 499                 interrupts = <0 19 0x04>;
 500                 clocks = <&tegra_car 69>;
 501                 status = "disabled";
 502         };
 503
 504         sdhci@c8000600 {
 505                 compatible = "nvidia,tegra20-sdhci";
 506                 reg = <0xc8000600 0x200>;
 507                 interrupts = <0 31 0x04>;
 508                 clocks = <&tegra_car 15>;
 509                 status = "disabled";
 510         };
 511
 512         cpus {
 513                 #address-cells = <1>;
 514                 #size-cells = <0>;
 515
 516                 cpu@0 {
 517                         device_type = "cpu";
 518                         compatible = "arm,cortex-a9";
 519                         reg = <0>;
 520                 };
 521
 522                 cpu@1 {
 523                         device_type = "cpu";
 524                         compatible = "arm,cortex-a9";
 525                         reg = <1>;
 526                 };
 527         };
 528
 529         pmu {
 530                 compatible = "arm,cortex-a9-pmu";
 531                 interrupts = <0 56 0x04
 532                               0 57 0x04>;
 533         };
 534 };