1 #include <dt-bindings/clock/tegra124-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
4 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include "skeleton.dtsi"
10 compatible = "nvidia,tegra124";
11 interrupt-parent = <&gic>;
15 pcie-controller@0,01003000 {
16 compatible = "nvidia,tegra124-pcie";
18 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
19 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
20 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
21 reg-names = "pads", "afi", "cs";
22 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
23 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
24 interrupt-names = "intr", "msi";
26 #interrupt-cells = <1>;
27 interrupt-map-mask = <0 0 0 0>;
28 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
30 bus-range = <0x00 0xff>;
34 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
35 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
36 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
37 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
38 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
40 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
41 <&tegra_car TEGRA124_CLK_AFI>,
42 <&tegra_car TEGRA124_CLK_PLL_E>,
43 <&tegra_car TEGRA124_CLK_CML0>;
44 clock-names = "pex", "afi", "pll_e", "cml";
45 resets = <&tegra_car 70>,
48 reset-names = "pex", "afi", "pcie_x";
51 phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>;
56 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
57 reg = <0x000800 0 0 0 0>;
64 nvidia,num-lanes = <2>;
69 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
70 reg = <0x001000 0 0 0 0>;
77 nvidia,num-lanes = <1>;
82 compatible = "nvidia,tegra124-host1x", "simple-bus";
83 reg = <0x0 0x50000000 0x0 0x00034000>;
84 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
85 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
86 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
87 resets = <&tegra_car 28>;
88 reset-names = "host1x";
93 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
96 compatible = "nvidia,tegra124-dc";
97 reg = <0x0 0x54200000 0x0 0x00040000>;
98 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
99 clocks = <&tegra_car TEGRA124_CLK_DISP1>,
100 <&tegra_car TEGRA124_CLK_PLL_P>;
101 clock-names = "dc", "parent";
102 resets = <&tegra_car 27>;
109 compatible = "nvidia,tegra124-dc";
110 reg = <0x0 0x54240000 0x0 0x00040000>;
111 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
112 clocks = <&tegra_car TEGRA124_CLK_DISP2>,
113 <&tegra_car TEGRA124_CLK_PLL_P>;
114 clock-names = "dc", "parent";
115 resets = <&tegra_car 26>;
122 compatible = "nvidia,tegra124-hdmi";
123 reg = <0x0 0x54280000 0x0 0x00040000>;
124 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
125 clocks = <&tegra_car TEGRA124_CLK_HDMI>,
126 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
127 clock-names = "hdmi", "parent";
128 resets = <&tegra_car 51>;
129 reset-names = "hdmi";
134 compatible = "nvidia,tegra124-sor";
135 reg = <0x0 0x54540000 0x0 0x00040000>;
136 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
137 clocks = <&tegra_car TEGRA124_CLK_SOR0>,
138 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
139 <&tegra_car TEGRA124_CLK_PLL_DP>,
140 <&tegra_car TEGRA124_CLK_CLK_M>;
141 clock-names = "sor", "parent", "dp", "safe";
142 resets = <&tegra_car 182>;
147 dpaux: dpaux@0,545c0000 {
148 compatible = "nvidia,tegra124-dpaux";
149 reg = <0x0 0x545c0000 0x0 0x00040000>;
150 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
151 clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
152 <&tegra_car TEGRA124_CLK_PLL_DP>;
153 clock-names = "dpaux", "parent";
154 resets = <&tegra_car 181>;
155 reset-names = "dpaux";
160 gic: interrupt-controller@0,50041000 {
161 compatible = "arm,cortex-a15-gic";
162 #interrupt-cells = <3>;
163 interrupt-controller;
164 reg = <0x0 0x50041000 0x0 0x1000>,
165 <0x0 0x50042000 0x0 0x1000>,
166 <0x0 0x50044000 0x0 0x2000>,
167 <0x0 0x50046000 0x0 0x2000>;
168 interrupts = <GIC_PPI 9
169 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
173 compatible = "nvidia,gk20a";
174 reg = <0x0 0x57000000 0x0 0x01000000>,
175 <0x0 0x58000000 0x0 0x01000000>;
176 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
177 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
178 interrupt-names = "stall", "nonstall";
179 clocks = <&tegra_car TEGRA124_CLK_GPU>,
180 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
181 clock-names = "gpu", "pwr";
182 resets = <&tegra_car 184>;
188 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
189 reg = <0x0 0x60005000 0x0 0x400>;
190 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
191 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
192 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
193 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
194 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
196 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
199 tegra_car: clock@0,60006000 {
200 compatible = "nvidia,tegra124-car";
201 reg = <0x0 0x60006000 0x0 0x1000>;
206 flow-controller@0,60007000 {
207 compatible = "nvidia,tegra124-flowctrl";
208 reg = <0x0 0x60007000 0x0 0x1000>;
211 gpio: gpio@0,6000d000 {
212 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
213 reg = <0x0 0x6000d000 0x0 0x1000>;
214 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
221 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
224 #interrupt-cells = <2>;
225 interrupt-controller;
228 apbdma: dma@0,60020000 {
229 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
230 reg = <0x0 0x60020000 0x0 0x1400>;
231 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
232 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
233 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
234 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
235 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
236 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
237 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
238 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
239 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
240 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
241 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
242 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
243 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
244 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
245 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
246 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
247 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
248 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
249 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
250 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
251 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
255 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
257 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
258 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
259 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
260 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
261 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
262 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
263 clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
264 resets = <&tegra_car 34>;
270 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
271 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
272 <0x0 0x7000E864 0x0 0x04>; /* Strapping options */
275 pinmux: pinmux@0,70000868 {
276 compatible = "nvidia,tegra124-pinmux";
277 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
278 <0x0 0x70003000 0x0 0x434>, /* Mux registers */
279 <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
283 * There are two serial driver i.e. 8250 based simple serial
284 * driver and APB DMA based serial driver for higher baudrate
285 * and performace. To enable the 8250 based driver, the compatible
286 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
287 * the APB DMA based serial driver, the comptible is
288 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
291 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
292 reg = <0x0 0x70006000 0x0 0x40>;
294 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
295 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
296 resets = <&tegra_car 6>;
297 reset-names = "serial";
298 dmas = <&apbdma 8>, <&apbdma 8>;
299 dma-names = "rx", "tx";
304 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
305 reg = <0x0 0x70006040 0x0 0x40>;
307 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
308 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
309 resets = <&tegra_car 7>;
310 reset-names = "serial";
311 dmas = <&apbdma 9>, <&apbdma 9>;
312 dma-names = "rx", "tx";
317 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
318 reg = <0x0 0x70006200 0x0 0x40>;
320 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
321 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
322 resets = <&tegra_car 55>;
323 reset-names = "serial";
324 dmas = <&apbdma 10>, <&apbdma 10>;
325 dma-names = "rx", "tx";
330 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
331 reg = <0x0 0x70006300 0x0 0x40>;
333 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
335 resets = <&tegra_car 65>;
336 reset-names = "serial";
337 dmas = <&apbdma 19>, <&apbdma 19>;
338 dma-names = "rx", "tx";
342 pwm: pwm@0,7000a000 {
343 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
344 reg = <0x0 0x7000a000 0x0 0x100>;
346 clocks = <&tegra_car TEGRA124_CLK_PWM>;
347 resets = <&tegra_car 17>;
353 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
354 reg = <0x0 0x7000c000 0x0 0x100>;
355 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
356 #address-cells = <1>;
358 clocks = <&tegra_car TEGRA124_CLK_I2C1>;
359 clock-names = "div-clk";
360 resets = <&tegra_car 12>;
362 dmas = <&apbdma 21>, <&apbdma 21>;
363 dma-names = "rx", "tx";
368 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
369 reg = <0x0 0x7000c400 0x0 0x100>;
370 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
371 #address-cells = <1>;
373 clocks = <&tegra_car TEGRA124_CLK_I2C2>;
374 clock-names = "div-clk";
375 resets = <&tegra_car 54>;
377 dmas = <&apbdma 22>, <&apbdma 22>;
378 dma-names = "rx", "tx";
383 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
384 reg = <0x0 0x7000c500 0x0 0x100>;
385 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
386 #address-cells = <1>;
388 clocks = <&tegra_car TEGRA124_CLK_I2C3>;
389 clock-names = "div-clk";
390 resets = <&tegra_car 67>;
392 dmas = <&apbdma 23>, <&apbdma 23>;
393 dma-names = "rx", "tx";
398 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
399 reg = <0x0 0x7000c700 0x0 0x100>;
400 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
401 #address-cells = <1>;
403 clocks = <&tegra_car TEGRA124_CLK_I2C4>;
404 clock-names = "div-clk";
405 resets = <&tegra_car 103>;
407 dmas = <&apbdma 26>, <&apbdma 26>;
408 dma-names = "rx", "tx";
413 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
414 reg = <0x0 0x7000d000 0x0 0x100>;
415 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
416 #address-cells = <1>;
418 clocks = <&tegra_car TEGRA124_CLK_I2C5>;
419 clock-names = "div-clk";
420 resets = <&tegra_car 47>;
422 dmas = <&apbdma 24>, <&apbdma 24>;
423 dma-names = "rx", "tx";
428 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
429 reg = <0x0 0x7000d100 0x0 0x100>;
430 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
431 #address-cells = <1>;
433 clocks = <&tegra_car TEGRA124_CLK_I2C6>;
434 clock-names = "div-clk";
435 resets = <&tegra_car 166>;
437 dmas = <&apbdma 30>, <&apbdma 30>;
438 dma-names = "rx", "tx";
443 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
444 reg = <0x0 0x7000d400 0x0 0x200>;
445 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
446 #address-cells = <1>;
448 clocks = <&tegra_car TEGRA124_CLK_SBC1>;
450 resets = <&tegra_car 41>;
452 dmas = <&apbdma 15>, <&apbdma 15>;
453 dma-names = "rx", "tx";
458 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
459 reg = <0x0 0x7000d600 0x0 0x200>;
460 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
461 #address-cells = <1>;
463 clocks = <&tegra_car TEGRA124_CLK_SBC2>;
465 resets = <&tegra_car 44>;
467 dmas = <&apbdma 16>, <&apbdma 16>;
468 dma-names = "rx", "tx";
473 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
474 reg = <0x0 0x7000d800 0x0 0x200>;
475 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
476 #address-cells = <1>;
478 clocks = <&tegra_car TEGRA124_CLK_SBC3>;
480 resets = <&tegra_car 46>;
482 dmas = <&apbdma 17>, <&apbdma 17>;
483 dma-names = "rx", "tx";
488 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
489 reg = <0x0 0x7000da00 0x0 0x200>;
490 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
491 #address-cells = <1>;
493 clocks = <&tegra_car TEGRA124_CLK_SBC4>;
495 resets = <&tegra_car 68>;
497 dmas = <&apbdma 18>, <&apbdma 18>;
498 dma-names = "rx", "tx";
503 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
504 reg = <0x0 0x7000dc00 0x0 0x200>;
505 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
506 #address-cells = <1>;
508 clocks = <&tegra_car TEGRA124_CLK_SBC5>;
510 resets = <&tegra_car 104>;
512 dmas = <&apbdma 27>, <&apbdma 27>;
513 dma-names = "rx", "tx";
518 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
519 reg = <0x0 0x7000de00 0x0 0x200>;
520 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
521 #address-cells = <1>;
523 clocks = <&tegra_car TEGRA124_CLK_SBC6>;
525 resets = <&tegra_car 105>;
527 dmas = <&apbdma 28>, <&apbdma 28>;
528 dma-names = "rx", "tx";
533 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
534 reg = <0x0 0x7000e000 0x0 0x100>;
535 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
536 clocks = <&tegra_car TEGRA124_CLK_RTC>;
540 compatible = "nvidia,tegra124-pmc";
541 reg = <0x0 0x7000e400 0x0 0x400>;
542 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
543 clock-names = "pclk", "clk32k_in";
547 compatible = "nvidia,tegra124-efuse";
548 reg = <0x0 0x7000f800 0x0 0x400>;
549 clocks = <&tegra_car TEGRA124_CLK_FUSE>;
550 clock-names = "fuse";
551 resets = <&tegra_car 39>;
552 reset-names = "fuse";
555 mc: memory-controller@0,70019000 {
556 compatible = "nvidia,tegra124-mc";
557 reg = <0x0 0x70019000 0x0 0x1000>;
558 clocks = <&tegra_car TEGRA124_CLK_MC>;
561 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
567 compatible = "nvidia,tegra124-ahci";
569 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
570 <0x0 0x70020000 0x0 0x7000>; /* SATA */
572 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
574 clocks = <&tegra_car TEGRA124_CLK_SATA>,
575 <&tegra_car TEGRA124_CLK_SATA_OOB>,
576 <&tegra_car TEGRA124_CLK_CML1>,
577 <&tegra_car TEGRA124_CLK_PLL_E>;
578 clock-names = "sata", "sata-oob", "cml1", "pll_e";
580 resets = <&tegra_car 124>,
583 reset-names = "sata", "sata-oob", "sata-cold";
585 phys = <&padctl TEGRA_XUSB_PADCTL_SATA>;
586 phy-names = "sata-phy";
592 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
593 reg = <0x0 0x70030000 0x0 0x10000>;
594 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
595 clocks = <&tegra_car TEGRA124_CLK_HDA>,
596 <&tegra_car TEGRA124_CLK_HDA2HDMI>,
597 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
598 clock-names = "hda", "hda2hdmi", "hdacodec_2x";
599 resets = <&tegra_car 125>, /* hda */
600 <&tegra_car 128>, /* hda2hdmi */
601 <&tegra_car 111>; /* hda2codec_2x */
602 reset-names = "hda", "hda2hdmi", "hdacodec_2x";
606 padctl: padctl@0,7009f000 {
607 compatible = "nvidia,tegra124-xusb-padctl";
608 reg = <0x0 0x7009f000 0x0 0x1000>;
609 resets = <&tegra_car 142>;
610 reset-names = "padctl";
616 compatible = "nvidia,tegra124-sdhci";
617 reg = <0x0 0x700b0000 0x0 0x200>;
618 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
619 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
620 resets = <&tegra_car 14>;
621 reset-names = "sdhci";
626 compatible = "nvidia,tegra124-sdhci";
627 reg = <0x0 0x700b0200 0x0 0x200>;
628 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
629 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
630 resets = <&tegra_car 9>;
631 reset-names = "sdhci";
636 compatible = "nvidia,tegra124-sdhci";
637 reg = <0x0 0x700b0400 0x0 0x200>;
638 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
639 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
640 resets = <&tegra_car 69>;
641 reset-names = "sdhci";
646 compatible = "nvidia,tegra124-sdhci";
647 reg = <0x0 0x700b0600 0x0 0x200>;
648 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
649 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
650 resets = <&tegra_car 15>;
651 reset-names = "sdhci";
656 compatible = "nvidia,tegra124-ahub";
657 reg = <0x0 0x70300000 0x0 0x200>,
658 <0x0 0x70300800 0x0 0x800>,
659 <0x0 0x70300200 0x0 0x600>;
660 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
661 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
662 <&tegra_car TEGRA124_CLK_APBIF>;
663 clock-names = "d_audio", "apbif";
664 resets = <&tegra_car 106>, /* d_audio */
665 <&tegra_car 107>, /* apbif */
666 <&tegra_car 30>, /* i2s0 */
667 <&tegra_car 11>, /* i2s1 */
668 <&tegra_car 18>, /* i2s2 */
669 <&tegra_car 101>, /* i2s3 */
670 <&tegra_car 102>, /* i2s4 */
671 <&tegra_car 108>, /* dam0 */
672 <&tegra_car 109>, /* dam1 */
673 <&tegra_car 110>, /* dam2 */
674 <&tegra_car 10>, /* spdif */
675 <&tegra_car 153>, /* amx */
676 <&tegra_car 185>, /* amx1 */
677 <&tegra_car 154>, /* adx */
678 <&tegra_car 180>, /* adx1 */
679 <&tegra_car 186>, /* afc0 */
680 <&tegra_car 187>, /* afc1 */
681 <&tegra_car 188>, /* afc2 */
682 <&tegra_car 189>, /* afc3 */
683 <&tegra_car 190>, /* afc4 */
684 <&tegra_car 191>; /* afc5 */
685 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
686 "i2s3", "i2s4", "dam0", "dam1", "dam2",
687 "spdif", "amx", "amx1", "adx", "adx1",
688 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
689 dmas = <&apbdma 1>, <&apbdma 1>,
690 <&apbdma 2>, <&apbdma 2>,
691 <&apbdma 3>, <&apbdma 3>,
692 <&apbdma 4>, <&apbdma 4>,
693 <&apbdma 6>, <&apbdma 6>,
694 <&apbdma 7>, <&apbdma 7>,
695 <&apbdma 12>, <&apbdma 12>,
696 <&apbdma 13>, <&apbdma 13>,
697 <&apbdma 14>, <&apbdma 14>,
698 <&apbdma 29>, <&apbdma 29>;
699 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
700 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
701 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
704 #address-cells = <2>;
707 tegra_i2s0: i2s@0,70301000 {
708 compatible = "nvidia,tegra124-i2s";
709 reg = <0x0 0x70301000 0x0 0x100>;
710 nvidia,ahub-cif-ids = <4 4>;
711 clocks = <&tegra_car TEGRA124_CLK_I2S0>;
712 resets = <&tegra_car 30>;
717 tegra_i2s1: i2s@0,70301100 {
718 compatible = "nvidia,tegra124-i2s";
719 reg = <0x0 0x70301100 0x0 0x100>;
720 nvidia,ahub-cif-ids = <5 5>;
721 clocks = <&tegra_car TEGRA124_CLK_I2S1>;
722 resets = <&tegra_car 11>;
727 tegra_i2s2: i2s@0,70301200 {
728 compatible = "nvidia,tegra124-i2s";
729 reg = <0x0 0x70301200 0x0 0x100>;
730 nvidia,ahub-cif-ids = <6 6>;
731 clocks = <&tegra_car TEGRA124_CLK_I2S2>;
732 resets = <&tegra_car 18>;
737 tegra_i2s3: i2s@0,70301300 {
738 compatible = "nvidia,tegra124-i2s";
739 reg = <0x0 0x70301300 0x0 0x100>;
740 nvidia,ahub-cif-ids = <7 7>;
741 clocks = <&tegra_car TEGRA124_CLK_I2S3>;
742 resets = <&tegra_car 101>;
747 tegra_i2s4: i2s@0,70301400 {
748 compatible = "nvidia,tegra124-i2s";
749 reg = <0x0 0x70301400 0x0 0x100>;
750 nvidia,ahub-cif-ids = <8 8>;
751 clocks = <&tegra_car TEGRA124_CLK_I2S4>;
752 resets = <&tegra_car 102>;
759 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
760 reg = <0x0 0x7d000000 0x0 0x4000>;
761 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
763 clocks = <&tegra_car TEGRA124_CLK_USBD>;
764 resets = <&tegra_car 22>;
766 nvidia,phy = <&phy1>;
770 phy1: usb-phy@0,7d000000 {
771 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
772 reg = <0x0 0x7d000000 0x0 0x4000>,
773 <0x0 0x7d000000 0x0 0x4000>;
775 clocks = <&tegra_car TEGRA124_CLK_USBD>,
776 <&tegra_car TEGRA124_CLK_PLL_U>,
777 <&tegra_car TEGRA124_CLK_USBD>;
778 clock-names = "reg", "pll_u", "utmi-pads";
779 resets = <&tegra_car 59>, <&tegra_car 22>;
780 reset-names = "usb", "utmi-pads";
781 nvidia,hssync-start-delay = <0>;
782 nvidia,idle-wait-delay = <17>;
783 nvidia,elastic-limit = <16>;
784 nvidia,term-range-adj = <6>;
785 nvidia,xcvr-setup = <9>;
786 nvidia,xcvr-lsfslew = <0>;
787 nvidia,xcvr-lsrslew = <3>;
788 nvidia,hssquelch-level = <2>;
789 nvidia,hsdiscon-level = <5>;
790 nvidia,xcvr-hsslew = <12>;
795 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
796 reg = <0x0 0x7d004000 0x0 0x4000>;
797 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
799 clocks = <&tegra_car TEGRA124_CLK_USB2>;
800 resets = <&tegra_car 58>;
802 nvidia,phy = <&phy2>;
806 phy2: usb-phy@0,7d004000 {
807 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
808 reg = <0x0 0x7d004000 0x0 0x4000>,
809 <0x0 0x7d000000 0x0 0x4000>;
811 clocks = <&tegra_car TEGRA124_CLK_USB2>,
812 <&tegra_car TEGRA124_CLK_PLL_U>,
813 <&tegra_car TEGRA124_CLK_USBD>;
814 clock-names = "reg", "pll_u", "utmi-pads";
815 resets = <&tegra_car 22>, <&tegra_car 22>;
816 reset-names = "usb", "utmi-pads";
817 nvidia,hssync-start-delay = <0>;
818 nvidia,idle-wait-delay = <17>;
819 nvidia,elastic-limit = <16>;
820 nvidia,term-range-adj = <6>;
821 nvidia,xcvr-setup = <9>;
822 nvidia,xcvr-lsfslew = <0>;
823 nvidia,xcvr-lsrslew = <3>;
824 nvidia,hssquelch-level = <2>;
825 nvidia,hsdiscon-level = <5>;
826 nvidia,xcvr-hsslew = <12>;
827 nvidia,has-utmi-pad-registers;
832 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
833 reg = <0x0 0x7d008000 0x0 0x4000>;
834 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
836 clocks = <&tegra_car TEGRA124_CLK_USB3>;
837 resets = <&tegra_car 59>;
839 nvidia,phy = <&phy3>;
843 phy3: usb-phy@0,7d008000 {
844 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
845 reg = <0x0 0x7d008000 0x0 0x4000>,
846 <0x0 0x7d000000 0x0 0x4000>;
848 clocks = <&tegra_car TEGRA124_CLK_USB3>,
849 <&tegra_car TEGRA124_CLK_PLL_U>,
850 <&tegra_car TEGRA124_CLK_USBD>;
851 clock-names = "reg", "pll_u", "utmi-pads";
852 resets = <&tegra_car 58>, <&tegra_car 22>;
853 reset-names = "usb", "utmi-pads";
854 nvidia,hssync-start-delay = <0>;
855 nvidia,idle-wait-delay = <17>;
856 nvidia,elastic-limit = <16>;
857 nvidia,term-range-adj = <6>;
858 nvidia,xcvr-setup = <9>;
859 nvidia,xcvr-lsfslew = <0>;
860 nvidia,xcvr-lsrslew = <3>;
861 nvidia,hssquelch-level = <2>;
862 nvidia,hsdiscon-level = <5>;
863 nvidia,xcvr-hsslew = <12>;
868 #address-cells = <1>;
873 compatible = "arm,cortex-a15";
879 compatible = "arm,cortex-a15";
885 compatible = "arm,cortex-a15";
891 compatible = "arm,cortex-a15";
897 compatible = "arm,armv7-timer";
898 interrupts = <GIC_PPI 13
899 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
901 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
903 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
905 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;