arch/arm/boot/dts/stih415-pinctrl.dtsi

   1 /*
   2  * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
   3  * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * publishhed by the Free Software Foundation.
   8  */
   9 #include "st-pincfg.h"
  10 / {
  11
  12         aliases {
  13                 gpio0   = &PIO0;
  14                 gpio1   = &PIO1;
  15                 gpio2   = &PIO2;
  16                 gpio3   = &PIO3;
  17                 gpio4   = &PIO4;
  18                 gpio5   = &PIO5;
  19                 gpio6   = &PIO6;
  20                 gpio7   = &PIO7;
  21                 gpio8   = &PIO8;
  22                 gpio9   = &PIO9;
  23                 gpio10  = &PIO10;
  24                 gpio11  = &PIO11;
  25                 gpio12  = &PIO12;
  26                 gpio13  = &PIO13;
  27                 gpio14  = &PIO14;
  28                 gpio15  = &PIO15;
  29                 gpio16  = &PIO16;
  30                 gpio17  = &PIO17;
  31                 gpio18  = &PIO18;
  32                 gpio19  = &PIO100;
  33                 gpio20  = &PIO101;
  34                 gpio21  = &PIO102;
  35                 gpio22  = &PIO103;
  36                 gpio23  = &PIO104;
  37                 gpio24  = &PIO105;
  38                 gpio25  = &PIO106;
  39                 gpio26  = &PIO107;
  40         };
  41
  42         soc {
  43                 pin-controller-sbc {
  44                         #address-cells  = <1>;
  45                         #size-cells     = <1>;
  46                         compatible      = "st,stih415-sbc-pinctrl";
  47                         st,syscfg       = <&syscfg_sbc>;
  48                         ranges          = <0 0xfe610000 0x5000>;
  49
  50                         PIO0: gpio@fe610000 {
  51                                 gpio-controller;
  52                                 #gpio-cells     = <1>;
  53                                 reg             = <0 0x100>;
  54                                 st,bank-name    = "PIO0";
  55                         };
  56                         PIO1: gpio@fe611000 {
  57                                 gpio-controller;
  58                                 #gpio-cells     = <1>;
  59                                 reg             = <0x1000 0x100>;
  60                                 st,bank-name    = "PIO1";
  61                         };
  62                         PIO2: gpio@fe612000 {
  63                                 gpio-controller;
  64                                 #gpio-cells     = <1>;
  65                                 reg             = <0x2000 0x100>;
  66                                 st,bank-name    = "PIO2";
  67                         };
  68                         PIO3: gpio@fe613000 {
  69                                 gpio-controller;
  70                                 #gpio-cells     = <1>;
  71                                 reg             = <0x3000 0x100>;
  72                                 st,bank-name    = "PIO3";
  73                         };
  74                         PIO4: gpio@fe614000 {
  75                                 gpio-controller;
  76                                 #gpio-cells     = <1>;
  77                                 reg             = <0x4000 0x100>;
  78                                 st,bank-name    = "PIO4";
  79                         };
  80
  81                         sbc_serial1 {
  82                                 pinctrl_sbc_serial1:sbc_serial1 {
  83                                         st,pins {
  84                                                 tx      = <&PIO2 6 ALT3 OUT>;
  85                                                 rx      = <&PIO2 7 ALT3 IN>;
  86                                         };
  87                                 };
  88                         };
  89
  90                         sbc_i2c0 {
  91                                 pinctrl_sbc_i2c0_default: sbc_i2c0-default {
  92                                         st,pins {
  93                                                 sda = <&PIO4 6 ALT1 BIDIR>;
  94                                                 scl = <&PIO4 5 ALT1 BIDIR>;
  95                                         };
  96                                 };
  97                         };
  98
  99                         sbc_i2c1 {
 100                                 pinctrl_sbc_i2c1_default: sbc_i2c1-default {
 101                                         st,pins {
 102                                                 sda = <&PIO3 2 ALT2 BIDIR>;
 103                                                 scl = <&PIO3 1 ALT2 BIDIR>;
 104                                         };
 105                                 };
 106                         };
 107                 };
 108
 109                 pin-controller-front {
 110                         #address-cells  = <1>;
 111                         #size-cells     = <1>;
 112                         compatible      = "st,stih415-front-pinctrl";
 113                         st,syscfg       = <&syscfg_front>;
 114                         ranges          = <0 0xfee00000 0x8000>;
 115
 116                         PIO5: gpio@fee00000 {
 117                                 gpio-controller;
 118                                 #gpio-cells     = <1>;
 119                                 reg             = <0 0x100>;
 120                                 st,bank-name    = "PIO5";
 121                         };
 122                         PIO6: gpio@fee01000 {
 123                                 gpio-controller;
 124                                 #gpio-cells     = <1>;
 125                                 reg             = <0x1000 0x100>;
 126                                 st,bank-name    = "PIO6";
 127                         };
 128                         PIO7: gpio@fee02000 {
 129                                 gpio-controller;
 130                                 #gpio-cells     = <1>;
 131                                 reg             = <0x2000 0x100>;
 132                                 st,bank-name    = "PIO7";
 133                         };
 134                         PIO8: gpio@fee03000 {
 135                                 gpio-controller;
 136                                 #gpio-cells     = <1>;
 137                                 reg             = <0x3000 0x100>;
 138                                 st,bank-name    = "PIO8";
 139                         };
 140                         PIO9: gpio@fee04000 {
 141                                 gpio-controller;
 142                                 #gpio-cells     = <1>;
 143                                 reg             = <0x4000 0x100>;
 144                                 st,bank-name    = "PIO9";
 145                         };
 146                         PIO10: gpio@fee05000 {
 147                                 gpio-controller;
 148                                 #gpio-cells     = <1>;
 149                                 reg             = <0x5000 0x100>;
 150                                 st,bank-name    = "PIO10";
 151                         };
 152                         PIO11: gpio@fee06000 {
 153                                 gpio-controller;
 154                                 #gpio-cells     = <1>;
 155                                 reg             = <0x6000 0x100>;
 156                                 st,bank-name    = "PIO11";
 157                         };
 158                         PIO12: gpio@fee07000 {
 159                                 gpio-controller;
 160                                 #gpio-cells     = <1>;
 161                                 reg             = <0x7000 0x100>;
 162                                 st,bank-name    = "PIO12";
 163                         };
 164
 165                         i2c0 {
 166                                 pinctrl_i2c0_default: i2c0-default {
 167                                         st,pins {
 168                                                 sda = <&PIO9 3 ALT1 BIDIR>;
 169                                                 scl = <&PIO9 2 ALT1 BIDIR>;
 170                                         };
 171                                 };
 172                         };
 173
 174                         i2c1 {
 175                                 pinctrl_i2c1_default: i2c1-default {
 176                                         st,pins {
 177                                                 sda = <&PIO12 1 ALT1 BIDIR>;
 178                                                 scl = <&PIO12 0 ALT1 BIDIR>;
 179                                         };
 180                                 };
 181                         };
 182                 };
 183
 184                 pin-controller-rear {
 185                         #address-cells  = <1>;
 186                         #size-cells     = <1>;
 187                         compatible      = "st,stih415-rear-pinctrl";
 188                         st,syscfg       = <&syscfg_rear>;
 189                         ranges          = <0 0xfe820000 0x8000>;
 190
 191                         PIO13: gpio@fe820000 {
 192                                 gpio-controller;
 193                                 #gpio-cells     = <1>;
 194                                 reg             = <0 0x100>;
 195                                 st,bank-name    = "PIO13";
 196                         };
 197                         PIO14: gpio@fe821000 {
 198                                 gpio-controller;
 199                                 #gpio-cells     = <1>;
 200                                 reg             = <0x1000 0x100>;
 201                                 st,bank-name    = "PIO14";
 202                         };
 203                         PIO15: gpio@fe822000 {
 204                                 gpio-controller;
 205                                 #gpio-cells     = <1>;
 206                                 reg             = <0x2000 0x100>;
 207                                 st,bank-name    = "PIO15";
 208                         };
 209                         PIO16: gpio@fe823000 {
 210                                 gpio-controller;
 211                                 #gpio-cells     = <1>;
 212                                 reg             = <0x3000 0x100>;
 213                                 st,bank-name    = "PIO16";
 214                         };
 215                         PIO17: gpio@fe824000 {
 216                                 gpio-controller;
 217                                 #gpio-cells     = <1>;
 218                                 reg             = <0x4000 0x100>;
 219                                 st,bank-name    = "PIO17";
 220                         };
 221                         PIO18: gpio@fe825000 {
 222                                 gpio-controller;
 223                                 #gpio-cells     = <1>;
 224                                 reg             = <0x5000 0x100>;
 225                                 st,bank-name    = "PIO18";
 226                         };
 227
 228                         serial2 {
 229                                 pinctrl_serial2: serial2-0 {
 230                                         st,pins {
 231                                                 tx      = <&PIO17 4 ALT2 OUT>;
 232                                                 rx      = <&PIO17 5 ALT2 IN>;
 233                                         };
 234                                 };
 235                         };
 236                 };
 237
 238                 pin-controller-left {
 239                         #address-cells  = <1>;
 240                         #size-cells     = <1>;
 241                         compatible      = "st,stih415-left-pinctrl";
 242                         st,syscfg       = <&syscfg_left>;
 243                         ranges          = <0 0xfd6b0000 0x3000>;
 244
 245                         PIO100: gpio@fd6b0000 {
 246                                 gpio-controller;
 247                                 #gpio-cells     = <1>;
 248                                 reg             = <0 0x100>;
 249                                 st,bank-name    = "PIO100";
 250                         };
 251                         PIO101: gpio@fd6b1000 {
 252                                 gpio-controller;
 253                                 #gpio-cells     = <1>;
 254                                 reg             = <0x1000 0x100>;
 255                                 st,bank-name    = "PIO101";
 256                         };
 257                         PIO102: gpio@fd6b2000 {
 258                                 gpio-controller;
 259                                 #gpio-cells     = <1>;
 260                                 reg             = <0x2000 0x100>;
 261                                 st,bank-name    = "PIO102";
 262                         };
 263                 };
 264
 265                 pin-controller-right {
 266                         #address-cells  = <1>;
 267                         #size-cells     = <1>;
 268                         compatible      = "st,stih415-right-pinctrl";
 269                         st,syscfg       = <&syscfg_right>;
 270                         ranges          = <0 0xfd330000 0x5000>;
 271
 272                         PIO103: gpio@fd330000 {
 273                                 gpio-controller;
 274                                 #gpio-cells     = <1>;
 275                                 reg             = <0 0x100>;
 276                                 st,bank-name    = "PIO103";
 277                         };
 278                         PIO104: gpio@fd331000 {
 279                                 gpio-controller;
 280                                 #gpio-cells     = <1>;
 281                                 reg             = <0x1000 0x100>;
 282                                 st,bank-name    = "PIO104";
 283                         };
 284                         PIO105: gpio@fd332000 {
 285                                 gpio-controller;
 286                                 #gpio-cells     = <1>;
 287                                 reg             = <0x2000 0x100>;
 288                                 st,bank-name    = "PIO105";
 289                         };
 290                         PIO106: gpio@fd333000 {
 291                                 gpio-controller;
 292                                 #gpio-cells     = <1>;
 293                                 reg             = <0x3000 0x100>;
 294                                 st,bank-name    = "PIO106";
 295                         };
 296                         PIO107: gpio@fd334000 {
 297                                 gpio-controller;
 298                                 #gpio-cells     = <1>;
 299                                 reg             = <0x4000 0x100>;
 300                                 st,bank-name    = "PIO107";
 301                         };
 302                 };
 303         };
 304 };