arch/arm/boot/dts/omap5.dtsi

   1 /*
   2  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include <dt-bindings/pinctrl/omap.h>
  13
  14 #include "skeleton.dtsi"
  15
  16 / {
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         compatible = "ti,omap5";
  21         interrupt-parent = <&gic>;
  22
  23         aliases {
  24                 i2c0 = &i2c1;
  25                 i2c1 = &i2c2;
  26                 i2c2 = &i2c3;
  27                 i2c3 = &i2c4;
  28                 i2c4 = &i2c5;
  29                 serial0 = &uart1;
  30                 serial1 = &uart2;
  31                 serial2 = &uart3;
  32                 serial3 = &uart4;
  33                 serial4 = &uart5;
  34                 serial5 = &uart6;
  35         };
  36
  37         cpus {
  38                 #address-cells = <1>;
  39                 #size-cells = <0>;
  40
  41                 cpu0: cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a15";
  44                         reg = <0x0>;
  45
  46                         operating-points = <
  47                                 /* kHz    uV */
  48                                 500000  880000
  49                                 1000000 1060000
  50                                 1500000 1250000
  51                         >;
  52
  53                         clocks = <&dpll_mpu_ck>;
  54                         clock-names = "cpu";
  55
  56                         clock-latency = <300000>; /* From omap-cpufreq driver */
  57
  58                         /* cooling options */
  59                         cooling-min-level = <0>;
  60                         cooling-max-level = <2>;
  61                         #cooling-cells = <2>; /* min followed by max */
  62                 };
  63                 cpu@1 {
  64                         device_type = "cpu";
  65                         compatible = "arm,cortex-a15";
  66                         reg = <0x1>;
  67                 };
  68         };
  69
  70         thermal-zones {
  71                 #include "omap4-cpu-thermal.dtsi"
  72                 #include "omap5-gpu-thermal.dtsi"
  73                 #include "omap5-core-thermal.dtsi"
  74         };
  75
  76         timer {
  77                 compatible = "arm,armv7-timer";
  78                 /* PPI secure/nonsecure IRQ */
  79                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  80                              <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  81                              <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  82                              <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
  83         };
  84
  85         gic: interrupt-controller@48211000 {
  86                 compatible = "arm,cortex-a15-gic";
  87                 interrupt-controller;
  88                 #interrupt-cells = <3>;
  89                 reg = <0x48211000 0x1000>,
  90                       <0x48212000 0x1000>,
  91                       <0x48214000 0x2000>,
  92                       <0x48216000 0x2000>;
  93         };
  94
  95         /*
  96          * The soc node represents the soc top level view. It is uses for IPs
  97          * that are not memory mapped in the MPU view or for the MPU itself.
  98          */
  99         soc {
 100                 compatible = "ti,omap-infra";
 101                 mpu {
 102                         compatible = "ti,omap5-mpu";
 103                         ti,hwmods = "mpu";
 104                 };
 105         };
 106
 107         /*
 108          * XXX: Use a flat representation of the OMAP3 interconnect.
 109          * The real OMAP interconnect network is quite complex.
 110          * Since that will not bring real advantage to represent that in DT for
 111          * the moment, just use a fake OCP bus entry to represent the whole bus
 112          * hierarchy.
 113          */
 114         ocp {
 115                 compatible = "ti,omap4-l3-noc", "simple-bus";
 116                 #address-cells = <1>;
 117                 #size-cells = <1>;
 118                 ranges;
 119                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
 120                 reg = <0x44000000 0x2000>,
 121                       <0x44800000 0x3000>,
 122                       <0x45000000 0x4000>;
 123                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 124                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 125
 126                 prm: prm@4ae06000 {
 127                         compatible = "ti,omap5-prm";
 128                         reg = <0x4ae06000 0x3000>;
 129
 130                         prm_clocks: clocks {
 131                                 #address-cells = <1>;
 132                                 #size-cells = <0>;
 133                         };
 134
 135                         prm_clockdomains: clockdomains {
 136                         };
 137                 };
 138
 139                 cm_core_aon: cm_core_aon@4a004000 {
 140                         compatible = "ti,omap5-cm-core-aon";
 141                         reg = <0x4a004000 0x2000>;
 142
 143                         cm_core_aon_clocks: clocks {
 144                                 #address-cells = <1>;
 145                                 #size-cells = <0>;
 146                         };
 147
 148                         cm_core_aon_clockdomains: clockdomains {
 149                         };
 150                 };
 151
 152                 scrm: scrm@4ae0a000 {
 153                         compatible = "ti,omap5-scrm";
 154                         reg = <0x4ae0a000 0x2000>;
 155
 156                         scrm_clocks: clocks {
 157                                 #address-cells = <1>;
 158                                 #size-cells = <0>;
 159                         };
 160
 161                         scrm_clockdomains: clockdomains {
 162                         };
 163                 };
 164
 165                 cm_core: cm_core@4a008000 {
 166                         compatible = "ti,omap5-cm-core";
 167                         reg = <0x4a008000 0x3000>;
 168
 169                         cm_core_clocks: clocks {
 170                                 #address-cells = <1>;
 171                                 #size-cells = <0>;
 172                         };
 173
 174                         cm_core_clockdomains: clockdomains {
 175                         };
 176                 };
 177
 178                 counter32k: counter@4ae04000 {
 179                         compatible = "ti,omap-counter32k";
 180                         reg = <0x4ae04000 0x40>;
 181                         ti,hwmods = "counter_32k";
 182                 };
 183
 184                 omap5_pmx_core: pinmux@4a002840 {
 185                         compatible = "ti,omap4-padconf", "pinctrl-single";
 186                         reg = <0x4a002840 0x01b6>;
 187                         #address-cells = <1>;
 188                         #size-cells = <0>;
 189                         pinctrl-single,register-width = <16>;
 190                         pinctrl-single,function-mask = <0x7fff>;
 191                 };
 192                 omap5_pmx_wkup: pinmux@4ae0c840 {
 193                         compatible = "ti,omap4-padconf", "pinctrl-single";
 194                         reg = <0x4ae0c840 0x0038>;
 195                         #address-cells = <1>;
 196                         #size-cells = <0>;
 197                         pinctrl-single,register-width = <16>;
 198                         pinctrl-single,function-mask = <0x7fff>;
 199                 };
 200
 201                 sdma: dma-controller@4a056000 {
 202                         compatible = "ti,omap4430-sdma";
 203                         reg = <0x4a056000 0x1000>;
 204                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 205                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 206                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 207                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 208                         #dma-cells = <1>;
 209                         #dma-channels = <32>;
 210                         #dma-requests = <127>;
 211                 };
 212
 213                 gpio1: gpio@4ae10000 {
 214                         compatible = "ti,omap4-gpio";
 215                         reg = <0x4ae10000 0x200>;
 216                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 217                         ti,hwmods = "gpio1";
 218                         ti,gpio-always-on;
 219                         gpio-controller;
 220                         #gpio-cells = <2>;
 221                         interrupt-controller;
 222                         #interrupt-cells = <2>;
 223                 };
 224
 225                 gpio2: gpio@48055000 {
 226                         compatible = "ti,omap4-gpio";
 227                         reg = <0x48055000 0x200>;
 228                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 229                         ti,hwmods = "gpio2";
 230                         gpio-controller;
 231                         #gpio-cells = <2>;
 232                         interrupt-controller;
 233                         #interrupt-cells = <2>;
 234                 };
 235
 236                 gpio3: gpio@48057000 {
 237                         compatible = "ti,omap4-gpio";
 238                         reg = <0x48057000 0x200>;
 239                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 240                         ti,hwmods = "gpio3";
 241                         gpio-controller;
 242                         #gpio-cells = <2>;
 243                         interrupt-controller;
 244                         #interrupt-cells = <2>;
 245                 };
 246
 247                 gpio4: gpio@48059000 {
 248                         compatible = "ti,omap4-gpio";
 249                         reg = <0x48059000 0x200>;
 250                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 251                         ti,hwmods = "gpio4";
 252                         gpio-controller;
 253                         #gpio-cells = <2>;
 254                         interrupt-controller;
 255                         #interrupt-cells = <2>;
 256                 };
 257
 258                 gpio5: gpio@4805b000 {
 259                         compatible = "ti,omap4-gpio";
 260                         reg = <0x4805b000 0x200>;
 261                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 262                         ti,hwmods = "gpio5";
 263                         gpio-controller;
 264                         #gpio-cells = <2>;
 265                         interrupt-controller;
 266                         #interrupt-cells = <2>;
 267                 };
 268
 269                 gpio6: gpio@4805d000 {
 270                         compatible = "ti,omap4-gpio";
 271                         reg = <0x4805d000 0x200>;
 272                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 273                         ti,hwmods = "gpio6";
 274                         gpio-controller;
 275                         #gpio-cells = <2>;
 276                         interrupt-controller;
 277                         #interrupt-cells = <2>;
 278                 };
 279
 280                 gpio7: gpio@48051000 {
 281                         compatible = "ti,omap4-gpio";
 282                         reg = <0x48051000 0x200>;
 283                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 284                         ti,hwmods = "gpio7";
 285                         gpio-controller;
 286                         #gpio-cells = <2>;
 287                         interrupt-controller;
 288                         #interrupt-cells = <2>;
 289                 };
 290
 291                 gpio8: gpio@48053000 {
 292                         compatible = "ti,omap4-gpio";
 293                         reg = <0x48053000 0x200>;
 294                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 295                         ti,hwmods = "gpio8";
 296                         gpio-controller;
 297                         #gpio-cells = <2>;
 298                         interrupt-controller;
 299                         #interrupt-cells = <2>;
 300                 };
 301
 302                 gpmc: gpmc@50000000 {
 303                         compatible = "ti,omap4430-gpmc";
 304                         reg = <0x50000000 0x1000>;
 305                         #address-cells = <2>;
 306                         #size-cells = <1>;
 307                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 308                         gpmc,num-cs = <8>;
 309                         gpmc,num-waitpins = <4>;
 310                         ti,hwmods = "gpmc";
 311                 };
 312
 313                 i2c1: i2c@48070000 {
 314                         compatible = "ti,omap4-i2c";
 315                         reg = <0x48070000 0x100>;
 316                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 317                         #address-cells = <1>;
 318                         #size-cells = <0>;
 319                         ti,hwmods = "i2c1";
 320                 };
 321
 322                 i2c2: i2c@48072000 {
 323                         compatible = "ti,omap4-i2c";
 324                         reg = <0x48072000 0x100>;
 325                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 326                         #address-cells = <1>;
 327                         #size-cells = <0>;
 328                         ti,hwmods = "i2c2";
 329                 };
 330
 331                 i2c3: i2c@48060000 {
 332                         compatible = "ti,omap4-i2c";
 333                         reg = <0x48060000 0x100>;
 334                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 335                         #address-cells = <1>;
 336                         #size-cells = <0>;
 337                         ti,hwmods = "i2c3";
 338                 };
 339
 340                 i2c4: i2c@4807a000 {
 341                         compatible = "ti,omap4-i2c";
 342                         reg = <0x4807a000 0x100>;
 343                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 344                         #address-cells = <1>;
 345                         #size-cells = <0>;
 346                         ti,hwmods = "i2c4";
 347                 };
 348
 349                 i2c5: i2c@4807c000 {
 350                         compatible = "ti,omap4-i2c";
 351                         reg = <0x4807c000 0x100>;
 352                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 353                         #address-cells = <1>;
 354                         #size-cells = <0>;
 355                         ti,hwmods = "i2c5";
 356                 };
 357
 358                 hwspinlock: spinlock@4a0f6000 {
 359                         compatible = "ti,omap4-hwspinlock";
 360                         reg = <0x4a0f6000 0x1000>;
 361                         ti,hwmods = "spinlock";
 362                         #hwlock-cells = <1>;
 363                 };
 364
 365                 mcspi1: spi@48098000 {
 366                         compatible = "ti,omap4-mcspi";
 367                         reg = <0x48098000 0x200>;
 368                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 369                         #address-cells = <1>;
 370                         #size-cells = <0>;
 371                         ti,hwmods = "mcspi1";
 372                         ti,spi-num-cs = <4>;
 373                         dmas = <&sdma 35>,
 374                                <&sdma 36>,
 375                                <&sdma 37>,
 376                                <&sdma 38>,
 377                                <&sdma 39>,
 378                                <&sdma 40>,
 379                                <&sdma 41>,
 380                                <&sdma 42>;
 381                         dma-names = "tx0", "rx0", "tx1", "rx1",
 382                                     "tx2", "rx2", "tx3", "rx3";
 383                 };
 384
 385                 mcspi2: spi@4809a000 {
 386                         compatible = "ti,omap4-mcspi";
 387                         reg = <0x4809a000 0x200>;
 388                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 389                         #address-cells = <1>;
 390                         #size-cells = <0>;
 391                         ti,hwmods = "mcspi2";
 392                         ti,spi-num-cs = <2>;
 393                         dmas = <&sdma 43>,
 394                                <&sdma 44>,
 395                                <&sdma 45>,
 396                                <&sdma 46>;
 397                         dma-names = "tx0", "rx0", "tx1", "rx1";
 398                 };
 399
 400                 mcspi3: spi@480b8000 {
 401                         compatible = "ti,omap4-mcspi";
 402                         reg = <0x480b8000 0x200>;
 403                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 404                         #address-cells = <1>;
 405                         #size-cells = <0>;
 406                         ti,hwmods = "mcspi3";
 407                         ti,spi-num-cs = <2>;
 408                         dmas = <&sdma 15>, <&sdma 16>;
 409                         dma-names = "tx0", "rx0";
 410                 };
 411
 412                 mcspi4: spi@480ba000 {
 413                         compatible = "ti,omap4-mcspi";
 414                         reg = <0x480ba000 0x200>;
 415                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 416                         #address-cells = <1>;
 417                         #size-cells = <0>;
 418                         ti,hwmods = "mcspi4";
 419                         ti,spi-num-cs = <1>;
 420                         dmas = <&sdma 70>, <&sdma 71>;
 421                         dma-names = "tx0", "rx0";
 422                 };
 423
 424                 uart1: serial@4806a000 {
 425                         compatible = "ti,omap4-uart";
 426                         reg = <0x4806a000 0x100>;
 427                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 428                         ti,hwmods = "uart1";
 429                         clock-frequency = <48000000>;
 430                 };
 431
 432                 uart2: serial@4806c000 {
 433                         compatible = "ti,omap4-uart";
 434                         reg = <0x4806c000 0x100>;
 435                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 436                         ti,hwmods = "uart2";
 437                         clock-frequency = <48000000>;
 438                 };
 439
 440                 uart3: serial@48020000 {
 441                         compatible = "ti,omap4-uart";
 442                         reg = <0x48020000 0x100>;
 443                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 444                         ti,hwmods = "uart3";
 445                         clock-frequency = <48000000>;
 446                 };
 447
 448                 uart4: serial@4806e000 {
 449                         compatible = "ti,omap4-uart";
 450                         reg = <0x4806e000 0x100>;
 451                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 452                         ti,hwmods = "uart4";
 453                         clock-frequency = <48000000>;
 454                 };
 455
 456                 uart5: serial@48066000 {
 457                         compatible = "ti,omap4-uart";
 458                         reg = <0x48066000 0x100>;
 459                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 460                         ti,hwmods = "uart5";
 461                         clock-frequency = <48000000>;
 462                 };
 463
 464                 uart6: serial@48068000 {
 465                         compatible = "ti,omap4-uart";
 466                         reg = <0x48068000 0x100>;
 467                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 468                         ti,hwmods = "uart6";
 469                         clock-frequency = <48000000>;
 470                 };
 471
 472                 mmc1: mmc@4809c000 {
 473                         compatible = "ti,omap4-hsmmc";
 474                         reg = <0x4809c000 0x400>;
 475                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 476                         ti,hwmods = "mmc1";
 477                         ti,dual-volt;
 478                         ti,needs-special-reset;
 479                         dmas = <&sdma 61>, <&sdma 62>;
 480                         dma-names = "tx", "rx";
 481                 };
 482
 483                 mmc2: mmc@480b4000 {
 484                         compatible = "ti,omap4-hsmmc";
 485                         reg = <0x480b4000 0x400>;
 486                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 487                         ti,hwmods = "mmc2";
 488                         ti,needs-special-reset;
 489                         dmas = <&sdma 47>, <&sdma 48>;
 490                         dma-names = "tx", "rx";
 491                 };
 492
 493                 mmc3: mmc@480ad000 {
 494                         compatible = "ti,omap4-hsmmc";
 495                         reg = <0x480ad000 0x400>;
 496                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 497                         ti,hwmods = "mmc3";
 498                         ti,needs-special-reset;
 499                         dmas = <&sdma 77>, <&sdma 78>;
 500                         dma-names = "tx", "rx";
 501                 };
 502
 503                 mmc4: mmc@480d1000 {
 504                         compatible = "ti,omap4-hsmmc";
 505                         reg = <0x480d1000 0x400>;
 506                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 507                         ti,hwmods = "mmc4";
 508                         ti,needs-special-reset;
 509                         dmas = <&sdma 57>, <&sdma 58>;
 510                         dma-names = "tx", "rx";
 511                 };
 512
 513                 mmc5: mmc@480d5000 {
 514                         compatible = "ti,omap4-hsmmc";
 515                         reg = <0x480d5000 0x400>;
 516                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 517                         ti,hwmods = "mmc5";
 518                         ti,needs-special-reset;
 519                         dmas = <&sdma 59>, <&sdma 60>;
 520                         dma-names = "tx", "rx";
 521                 };
 522
 523                 mmu_dsp: mmu@4a066000 {
 524                         compatible = "ti,omap4-iommu";
 525                         reg = <0x4a066000 0x100>;
 526                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 527                         ti,hwmods = "mmu_dsp";
 528                 };
 529
 530                 mmu_ipu: mmu@55082000 {
 531                         compatible = "ti,omap4-iommu";
 532                         reg = <0x55082000 0x100>;
 533                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 534                         ti,hwmods = "mmu_ipu";
 535                         ti,iommu-bus-err-back;
 536                 };
 537
 538                 keypad: keypad@4ae1c000 {
 539                         compatible = "ti,omap4-keypad";
 540                         reg = <0x4ae1c000 0x400>;
 541                         ti,hwmods = "kbd";
 542                 };
 543
 544                 mcpdm: mcpdm@40132000 {
 545                         compatible = "ti,omap4-mcpdm";
 546                         reg = <0x40132000 0x7f>, /* MPU private access */
 547                               <0x49032000 0x7f>; /* L3 Interconnect */
 548                         reg-names = "mpu", "dma";
 549                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 550                         ti,hwmods = "mcpdm";
 551                         dmas = <&sdma 65>,
 552                                <&sdma 66>;
 553                         dma-names = "up_link", "dn_link";
 554                         status = "disabled";
 555                 };
 556
 557                 dmic: dmic@4012e000 {
 558                         compatible = "ti,omap4-dmic";
 559                         reg = <0x4012e000 0x7f>, /* MPU private access */
 560                               <0x4902e000 0x7f>; /* L3 Interconnect */
 561                         reg-names = "mpu", "dma";
 562                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 563                         ti,hwmods = "dmic";
 564                         dmas = <&sdma 67>;
 565                         dma-names = "up_link";
 566                         status = "disabled";
 567                 };
 568
 569                 mcbsp1: mcbsp@40122000 {
 570                         compatible = "ti,omap4-mcbsp";
 571                         reg = <0x40122000 0xff>, /* MPU private access */
 572                               <0x49022000 0xff>; /* L3 Interconnect */
 573                         reg-names = "mpu", "dma";
 574                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 575                         interrupt-names = "common";
 576                         ti,buffer-size = <128>;
 577                         ti,hwmods = "mcbsp1";
 578                         dmas = <&sdma 33>,
 579                                <&sdma 34>;
 580                         dma-names = "tx", "rx";
 581                         status = "disabled";
 582                 };
 583
 584                 mcbsp2: mcbsp@40124000 {
 585                         compatible = "ti,omap4-mcbsp";
 586                         reg = <0x40124000 0xff>, /* MPU private access */
 587                               <0x49024000 0xff>; /* L3 Interconnect */
 588                         reg-names = "mpu", "dma";
 589                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 590                         interrupt-names = "common";
 591                         ti,buffer-size = <128>;
 592                         ti,hwmods = "mcbsp2";
 593                         dmas = <&sdma 17>,
 594                                <&sdma 18>;
 595                         dma-names = "tx", "rx";
 596                         status = "disabled";
 597                 };
 598
 599                 mcbsp3: mcbsp@40126000 {
 600                         compatible = "ti,omap4-mcbsp";
 601                         reg = <0x40126000 0xff>, /* MPU private access */
 602                               <0x49026000 0xff>; /* L3 Interconnect */
 603                         reg-names = "mpu", "dma";
 604                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 605                         interrupt-names = "common";
 606                         ti,buffer-size = <128>;
 607                         ti,hwmods = "mcbsp3";
 608                         dmas = <&sdma 19>,
 609                                <&sdma 20>;
 610                         dma-names = "tx", "rx";
 611                         status = "disabled";
 612                 };
 613
 614                 timer1: timer@4ae18000 {
 615                         compatible = "ti,omap5430-timer";
 616                         reg = <0x4ae18000 0x80>;
 617                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 618                         ti,hwmods = "timer1";
 619                         ti,timer-alwon;
 620                 };
 621
 622                 timer2: timer@48032000 {
 623                         compatible = "ti,omap5430-timer";
 624                         reg = <0x48032000 0x80>;
 625                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 626                         ti,hwmods = "timer2";
 627                 };
 628
 629                 timer3: timer@48034000 {
 630                         compatible = "ti,omap5430-timer";
 631                         reg = <0x48034000 0x80>;
 632                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 633                         ti,hwmods = "timer3";
 634                 };
 635
 636                 timer4: timer@48036000 {
 637                         compatible = "ti,omap5430-timer";
 638                         reg = <0x48036000 0x80>;
 639                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 640                         ti,hwmods = "timer4";
 641                 };
 642
 643                 timer5: timer@40138000 {
 644                         compatible = "ti,omap5430-timer";
 645                         reg = <0x40138000 0x80>,
 646                               <0x49038000 0x80>;
 647                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 648                         ti,hwmods = "timer5";
 649                         ti,timer-dsp;
 650                         ti,timer-pwm;
 651                 };
 652
 653                 timer6: timer@4013a000 {
 654                         compatible = "ti,omap5430-timer";
 655                         reg = <0x4013a000 0x80>,
 656                               <0x4903a000 0x80>;
 657                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 658                         ti,hwmods = "timer6";
 659                         ti,timer-dsp;
 660                         ti,timer-pwm;
 661                 };
 662
 663                 timer7: timer@4013c000 {
 664                         compatible = "ti,omap5430-timer";
 665                         reg = <0x4013c000 0x80>,
 666                               <0x4903c000 0x80>;
 667                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 668                         ti,hwmods = "timer7";
 669                         ti,timer-dsp;
 670                 };
 671
 672                 timer8: timer@4013e000 {
 673                         compatible = "ti,omap5430-timer";
 674                         reg = <0x4013e000 0x80>,
 675                               <0x4903e000 0x80>;
 676                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 677                         ti,hwmods = "timer8";
 678                         ti,timer-dsp;
 679                         ti,timer-pwm;
 680                 };
 681
 682                 timer9: timer@4803e000 {
 683                         compatible = "ti,omap5430-timer";
 684                         reg = <0x4803e000 0x80>;
 685                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 686                         ti,hwmods = "timer9";
 687                         ti,timer-pwm;
 688                 };
 689
 690                 timer10: timer@48086000 {
 691                         compatible = "ti,omap5430-timer";
 692                         reg = <0x48086000 0x80>;
 693                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 694                         ti,hwmods = "timer10";
 695                         ti,timer-pwm;
 696                 };
 697
 698                 timer11: timer@48088000 {
 699                         compatible = "ti,omap5430-timer";
 700                         reg = <0x48088000 0x80>;
 701                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 702                         ti,hwmods = "timer11";
 703                         ti,timer-pwm;
 704                 };
 705
 706                 wdt2: wdt@4ae14000 {
 707                         compatible = "ti,omap5-wdt", "ti,omap3-wdt";
 708                         reg = <0x4ae14000 0x80>;
 709                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 710                         ti,hwmods = "wd_timer2";
 711                 };
 712
 713                 dmm@4e000000 {
 714                         compatible = "ti,omap5-dmm";
 715                         reg = <0x4e000000 0x800>;
 716                         interrupts = <0 113 0x4>;
 717                         ti,hwmods = "dmm";
 718                 };
 719
 720                 emif1: emif@4c000000 {
 721                         compatible      = "ti,emif-4d5";
 722                         ti,hwmods       = "emif1";
 723                         ti,no-idle-on-init;
 724                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 725                         reg = <0x4c000000 0x400>;
 726                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 727                         hw-caps-read-idle-ctrl;
 728                         hw-caps-ll-interface;
 729                         hw-caps-temp-alert;
 730                 };
 731
 732                 emif2: emif@4d000000 {
 733                         compatible      = "ti,emif-4d5";
 734                         ti,hwmods       = "emif2";
 735                         ti,no-idle-on-init;
 736                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 737                         reg = <0x4d000000 0x400>;
 738                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 739                         hw-caps-read-idle-ctrl;
 740                         hw-caps-ll-interface;
 741                         hw-caps-temp-alert;
 742                 };
 743
 744                 omap_control_usb2phy: control-phy@4a002300 {
 745                         compatible = "ti,control-phy-usb2";
 746                         reg = <0x4a002300 0x4>;
 747                         reg-names = "power";
 748                 };
 749
 750                 omap_control_usb3phy: control-phy@4a002370 {
 751                         compatible = "ti,control-phy-pipe3";
 752                         reg = <0x4a002370 0x4>;
 753                         reg-names = "power";
 754                 };
 755
 756                 usb3: omap_dwc3@4a020000 {
 757                         compatible = "ti,dwc3";
 758                         ti,hwmods = "usb_otg_ss";
 759                         reg = <0x4a020000 0x10000>;
 760                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 761                         #address-cells = <1>;
 762                         #size-cells = <1>;
 763                         utmi-mode = <2>;
 764                         ranges;
 765                         dwc3@4a030000 {
 766                                 compatible = "snps,dwc3";
 767                                 reg = <0x4a030000 0x10000>;
 768                                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 769                                 phys = <&usb2_phy>, <&usb3_phy>;
 770                                 phy-names = "usb2-phy", "usb3-phy";
 771                                 dr_mode = "peripheral";
 772                                 tx-fifo-resize;
 773                         };
 774                 };
 775
 776                 ocp2scp@4a080000 {
 777                         compatible = "ti,omap-ocp2scp";
 778                         #address-cells = <1>;
 779                         #size-cells = <1>;
 780                         reg = <0x4a080000 0x20>;
 781                         ranges;
 782                         ti,hwmods = "ocp2scp1";
 783                         usb2_phy: usb2phy@4a084000 {
 784                                 compatible = "ti,omap-usb2";
 785                                 reg = <0x4a084000 0x7c>;
 786                                 ctrl-module = <&omap_control_usb2phy>;
 787                                 #phy-cells = <0>;
 788                         };
 789
 790                         usb3_phy: usb3phy@4a084400 {
 791                                 compatible = "ti,omap-usb3";
 792                                 reg = <0x4a084400 0x80>,
 793                                       <0x4a084800 0x64>,
 794                                       <0x4a084c00 0x40>;
 795                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
 796                                 ctrl-module = <&omap_control_usb3phy>;
 797                                 #phy-cells = <0>;
 798                         };
 799                 };
 800
 801                 usbhstll: usbhstll@4a062000 {
 802                         compatible = "ti,usbhs-tll";
 803                         reg = <0x4a062000 0x1000>;
 804                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 805                         ti,hwmods = "usb_tll_hs";
 806                 };
 807
 808                 usbhshost: usbhshost@4a064000 {
 809                         compatible = "ti,usbhs-host";
 810                         reg = <0x4a064000 0x800>;
 811                         ti,hwmods = "usb_host_hs";
 812                         #address-cells = <1>;
 813                         #size-cells = <1>;
 814                         ranges;
 815
 816                         usbhsohci: ohci@4a064800 {
 817                                 compatible = "ti,ohci-omap3";
 818                                 reg = <0x4a064800 0x400>;
 819                                 interrupt-parent = <&gic>;
 820                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 821                         };
 822
 823                         usbhsehci: ehci@4a064c00 {
 824                                 compatible = "ti,ehci-omap";
 825                                 reg = <0x4a064c00 0x400>;
 826                                 interrupt-parent = <&gic>;
 827                                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 828                         };
 829                 };
 830
 831                 bandgap: bandgap@4a0021e0 {
 832                         reg = <0x4a0021e0 0xc
 833                                0x4a00232c 0xc
 834                                0x4a002380 0x2c
 835                                0x4a0023C0 0x3c>;
 836                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 837                         compatible = "ti,omap5430-bandgap";
 838
 839                         #thermal-sensor-cells = <1>;
 840                 };
 841         };
 842 };
 843
 844 /include/ "omap54xx-clocks.dtsi"