arch/arm/boot/dts/omap5.dtsi

   1 /*
   2  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include <dt-bindings/pinctrl/omap.h>
  13
  14 #include "skeleton.dtsi"
  15
  16 / {
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         compatible = "ti,omap5";
  21         interrupt-parent = <&gic>;
  22
  23         aliases {
  24                 i2c0 = &i2c1;
  25                 i2c1 = &i2c2;
  26                 i2c2 = &i2c3;
  27                 i2c3 = &i2c4;
  28                 i2c4 = &i2c5;
  29                 serial0 = &uart1;
  30                 serial1 = &uart2;
  31                 serial2 = &uart3;
  32                 serial3 = &uart4;
  33                 serial4 = &uart5;
  34                 serial5 = &uart6;
  35         };
  36
  37         cpus {
  38                 #address-cells = <1>;
  39                 #size-cells = <0>;
  40
  41                 cpu0: cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a15";
  44                         reg = <0x0>;
  45
  46                         operating-points = <
  47                                 /* kHz    uV */
  48                                 500000  880000
  49                                 1000000 1060000
  50                                 1500000 1250000
  51                         >;
  52
  53                         clocks = <&dpll_mpu_ck>;
  54                         clock-names = "cpu";
  55
  56                         clock-latency = <300000>; /* From omap-cpufreq driver */
  57
  58                         /* cooling options */
  59                         cooling-min-level = <0>;
  60                         cooling-max-level = <2>;
  61                         #cooling-cells = <2>; /* min followed by max */
  62                 };
  63                 cpu@1 {
  64                         device_type = "cpu";
  65                         compatible = "arm,cortex-a15";
  66                         reg = <0x1>;
  67                 };
  68         };
  69
  70         thermal-zones {
  71                 #include "omap4-cpu-thermal.dtsi"
  72                 #include "omap5-gpu-thermal.dtsi"
  73                 #include "omap5-core-thermal.dtsi"
  74         };
  75
  76         timer {
  77                 compatible = "arm,armv7-timer";
  78                 /* PPI secure/nonsecure IRQ */
  79                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  80                              <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  81                              <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  82                              <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
  83         };
  84
  85         gic: interrupt-controller@48211000 {
  86                 compatible = "arm,cortex-a15-gic";
  87                 interrupt-controller;
  88                 #interrupt-cells = <3>;
  89                 reg = <0x48211000 0x1000>,
  90                       <0x48212000 0x1000>,
  91                       <0x48214000 0x2000>,
  92                       <0x48216000 0x2000>;
  93         };
  94
  95         /*
  96          * The soc node represents the soc top level view. It is uses for IPs
  97          * that are not memory mapped in the MPU view or for the MPU itself.
  98          */
  99         soc {
 100                 compatible = "ti,omap-infra";
 101                 mpu {
 102                         compatible = "ti,omap5-mpu";
 103                         ti,hwmods = "mpu";
 104                 };
 105         };
 106
 107         /*
 108          * XXX: Use a flat representation of the OMAP3 interconnect.
 109          * The real OMAP interconnect network is quite complex.
 110          * Since that will not bring real advantage to represent that in DT for
 111          * the moment, just use a fake OCP bus entry to represent the whole bus
 112          * hierarchy.
 113          */
 114         ocp {
 115                 compatible = "ti,omap4-l3-noc", "simple-bus";
 116                 #address-cells = <1>;
 117                 #size-cells = <1>;
 118                 ranges;
 119                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
 120                 reg = <0x44000000 0x2000>,
 121                       <0x44800000 0x3000>,
 122                       <0x45000000 0x4000>;
 123                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 124                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 125
 126                 prm: prm@4ae06000 {
 127                         compatible = "ti,omap5-prm";
 128                         reg = <0x4ae06000 0x3000>;
 129
 130                         prm_clocks: clocks {
 131                                 #address-cells = <1>;
 132                                 #size-cells = <0>;
 133                         };
 134
 135                         prm_clockdomains: clockdomains {
 136                         };
 137                 };
 138
 139                 cm_core_aon: cm_core_aon@4a004000 {
 140                         compatible = "ti,omap5-cm-core-aon";
 141                         reg = <0x4a004000 0x2000>;
 142
 143                         cm_core_aon_clocks: clocks {
 144                                 #address-cells = <1>;
 145                                 #size-cells = <0>;
 146                         };
 147
 148                         cm_core_aon_clockdomains: clockdomains {
 149                         };
 150                 };
 151
 152                 scrm: scrm@4ae0a000 {
 153                         compatible = "ti,omap5-scrm";
 154                         reg = <0x4ae0a000 0x2000>;
 155
 156                         scrm_clocks: clocks {
 157                                 #address-cells = <1>;
 158                                 #size-cells = <0>;
 159                         };
 160
 161                         scrm_clockdomains: clockdomains {
 162                         };
 163                 };
 164
 165                 cm_core: cm_core@4a008000 {
 166                         compatible = "ti,omap5-cm-core";
 167                         reg = <0x4a008000 0x3000>;
 168
 169                         cm_core_clocks: clocks {
 170                                 #address-cells = <1>;
 171                                 #size-cells = <0>;
 172                         };
 173
 174                         cm_core_clockdomains: clockdomains {
 175                         };
 176                 };
 177
 178                 counter32k: counter@4ae04000 {
 179                         compatible = "ti,omap-counter32k";
 180                         reg = <0x4ae04000 0x40>;
 181                         ti,hwmods = "counter_32k";
 182                 };
 183
 184                 omap5_pmx_core: pinmux@4a002840 {
 185                         compatible = "ti,omap4-padconf", "pinctrl-single";
 186                         reg = <0x4a002840 0x01b6>;
 187                         #address-cells = <1>;
 188                         #size-cells = <0>;
 189                         pinctrl-single,register-width = <16>;
 190                         pinctrl-single,function-mask = <0x7fff>;
 191                 };
 192                 omap5_pmx_wkup: pinmux@4ae0c840 {
 193                         compatible = "ti,omap4-padconf", "pinctrl-single";
 194                         reg = <0x4ae0c840 0x0038>;
 195                         #address-cells = <1>;
 196                         #size-cells = <0>;
 197                         pinctrl-single,register-width = <16>;
 198                         pinctrl-single,function-mask = <0x7fff>;
 199                 };
 200
 201                 sdma: dma-controller@4a056000 {
 202                         compatible = "ti,omap4430-sdma";
 203                         reg = <0x4a056000 0x1000>;
 204                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 205                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 206                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 207                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 208                         #dma-cells = <1>;
 209                         #dma-channels = <32>;
 210                         #dma-requests = <127>;
 211                 };
 212
 213                 gpio1: gpio@4ae10000 {
 214                         compatible = "ti,omap4-gpio";
 215                         reg = <0x4ae10000 0x200>;
 216                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 217                         ti,hwmods = "gpio1";
 218                         ti,gpio-always-on;
 219                         gpio-controller;
 220                         #gpio-cells = <2>;
 221                         interrupt-controller;
 222                         #interrupt-cells = <2>;
 223                 };
 224
 225                 gpio2: gpio@48055000 {
 226                         compatible = "ti,omap4-gpio";
 227                         reg = <0x48055000 0x200>;
 228                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 229                         ti,hwmods = "gpio2";
 230                         gpio-controller;
 231                         #gpio-cells = <2>;
 232                         interrupt-controller;
 233                         #interrupt-cells = <2>;
 234                 };
 235
 236                 gpio3: gpio@48057000 {
 237                         compatible = "ti,omap4-gpio";
 238                         reg = <0x48057000 0x200>;
 239                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 240                         ti,hwmods = "gpio3";
 241                         gpio-controller;
 242                         #gpio-cells = <2>;
 243                         interrupt-controller;
 244                         #interrupt-cells = <2>;
 245                 };
 246
 247                 gpio4: gpio@48059000 {
 248                         compatible = "ti,omap4-gpio";
 249                         reg = <0x48059000 0x200>;
 250                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 251                         ti,hwmods = "gpio4";
 252                         gpio-controller;
 253                         #gpio-cells = <2>;
 254                         interrupt-controller;
 255                         #interrupt-cells = <2>;
 256                 };
 257
 258                 gpio5: gpio@4805b000 {
 259                         compatible = "ti,omap4-gpio";
 260                         reg = <0x4805b000 0x200>;
 261                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 262                         ti,hwmods = "gpio5";
 263                         gpio-controller;
 264                         #gpio-cells = <2>;
 265                         interrupt-controller;
 266                         #interrupt-cells = <2>;
 267                 };
 268
 269                 gpio6: gpio@4805d000 {
 270                         compatible = "ti,omap4-gpio";
 271                         reg = <0x4805d000 0x200>;
 272                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 273                         ti,hwmods = "gpio6";
 274                         gpio-controller;
 275                         #gpio-cells = <2>;
 276                         interrupt-controller;
 277                         #interrupt-cells = <2>;
 278                 };
 279
 280                 gpio7: gpio@48051000 {
 281                         compatible = "ti,omap4-gpio";
 282                         reg = <0x48051000 0x200>;
 283                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 284                         ti,hwmods = "gpio7";
 285                         gpio-controller;
 286                         #gpio-cells = <2>;
 287                         interrupt-controller;
 288                         #interrupt-cells = <2>;
 289                 };
 290
 291                 gpio8: gpio@48053000 {
 292                         compatible = "ti,omap4-gpio";
 293                         reg = <0x48053000 0x200>;
 294                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 295                         ti,hwmods = "gpio8";
 296                         gpio-controller;
 297                         #gpio-cells = <2>;
 298                         interrupt-controller;
 299                         #interrupt-cells = <2>;
 300                 };
 301
 302                 gpmc: gpmc@50000000 {
 303                         compatible = "ti,omap4430-gpmc";
 304                         reg = <0x50000000 0x1000>;
 305                         #address-cells = <2>;
 306                         #size-cells = <1>;
 307                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 308                         gpmc,num-cs = <8>;
 309                         gpmc,num-waitpins = <4>;
 310                         ti,hwmods = "gpmc";
 311                         clocks = <&l3_iclk_div>;
 312                         clock-names = "fck";
 313                 };
 314
 315                 i2c1: i2c@48070000 {
 316                         compatible = "ti,omap4-i2c";
 317                         reg = <0x48070000 0x100>;
 318                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 319                         #address-cells = <1>;
 320                         #size-cells = <0>;
 321                         ti,hwmods = "i2c1";
 322                 };
 323
 324                 i2c2: i2c@48072000 {
 325                         compatible = "ti,omap4-i2c";
 326                         reg = <0x48072000 0x100>;
 327                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 328                         #address-cells = <1>;
 329                         #size-cells = <0>;
 330                         ti,hwmods = "i2c2";
 331                 };
 332
 333                 i2c3: i2c@48060000 {
 334                         compatible = "ti,omap4-i2c";
 335                         reg = <0x48060000 0x100>;
 336                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 337                         #address-cells = <1>;
 338                         #size-cells = <0>;
 339                         ti,hwmods = "i2c3";
 340                 };
 341
 342                 i2c4: i2c@4807a000 {
 343                         compatible = "ti,omap4-i2c";
 344                         reg = <0x4807a000 0x100>;
 345                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 346                         #address-cells = <1>;
 347                         #size-cells = <0>;
 348                         ti,hwmods = "i2c4";
 349                 };
 350
 351                 i2c5: i2c@4807c000 {
 352                         compatible = "ti,omap4-i2c";
 353                         reg = <0x4807c000 0x100>;
 354                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 355                         #address-cells = <1>;
 356                         #size-cells = <0>;
 357                         ti,hwmods = "i2c5";
 358                 };
 359
 360                 hwspinlock: spinlock@4a0f6000 {
 361                         compatible = "ti,omap4-hwspinlock";
 362                         reg = <0x4a0f6000 0x1000>;
 363                         ti,hwmods = "spinlock";
 364                         #hwlock-cells = <1>;
 365                 };
 366
 367                 mcspi1: spi@48098000 {
 368                         compatible = "ti,omap4-mcspi";
 369                         reg = <0x48098000 0x200>;
 370                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 371                         #address-cells = <1>;
 372                         #size-cells = <0>;
 373                         ti,hwmods = "mcspi1";
 374                         ti,spi-num-cs = <4>;
 375                         dmas = <&sdma 35>,
 376                                <&sdma 36>,
 377                                <&sdma 37>,
 378                                <&sdma 38>,
 379                                <&sdma 39>,
 380                                <&sdma 40>,
 381                                <&sdma 41>,
 382                                <&sdma 42>;
 383                         dma-names = "tx0", "rx0", "tx1", "rx1",
 384                                     "tx2", "rx2", "tx3", "rx3";
 385                 };
 386
 387                 mcspi2: spi@4809a000 {
 388                         compatible = "ti,omap4-mcspi";
 389                         reg = <0x4809a000 0x200>;
 390                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 391                         #address-cells = <1>;
 392                         #size-cells = <0>;
 393                         ti,hwmods = "mcspi2";
 394                         ti,spi-num-cs = <2>;
 395                         dmas = <&sdma 43>,
 396                                <&sdma 44>,
 397                                <&sdma 45>,
 398                                <&sdma 46>;
 399                         dma-names = "tx0", "rx0", "tx1", "rx1";
 400                 };
 401
 402                 mcspi3: spi@480b8000 {
 403                         compatible = "ti,omap4-mcspi";
 404                         reg = <0x480b8000 0x200>;
 405                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 406                         #address-cells = <1>;
 407                         #size-cells = <0>;
 408                         ti,hwmods = "mcspi3";
 409                         ti,spi-num-cs = <2>;
 410                         dmas = <&sdma 15>, <&sdma 16>;
 411                         dma-names = "tx0", "rx0";
 412                 };
 413
 414                 mcspi4: spi@480ba000 {
 415                         compatible = "ti,omap4-mcspi";
 416                         reg = <0x480ba000 0x200>;
 417                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 418                         #address-cells = <1>;
 419                         #size-cells = <0>;
 420                         ti,hwmods = "mcspi4";
 421                         ti,spi-num-cs = <1>;
 422                         dmas = <&sdma 70>, <&sdma 71>;
 423                         dma-names = "tx0", "rx0";
 424                 };
 425
 426                 uart1: serial@4806a000 {
 427                         compatible = "ti,omap4-uart";
 428                         reg = <0x4806a000 0x100>;
 429                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 430                         ti,hwmods = "uart1";
 431                         clock-frequency = <48000000>;
 432                 };
 433
 434                 uart2: serial@4806c000 {
 435                         compatible = "ti,omap4-uart";
 436                         reg = <0x4806c000 0x100>;
 437                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 438                         ti,hwmods = "uart2";
 439                         clock-frequency = <48000000>;
 440                 };
 441
 442                 uart3: serial@48020000 {
 443                         compatible = "ti,omap4-uart";
 444                         reg = <0x48020000 0x100>;
 445                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 446                         ti,hwmods = "uart3";
 447                         clock-frequency = <48000000>;
 448                 };
 449
 450                 uart4: serial@4806e000 {
 451                         compatible = "ti,omap4-uart";
 452                         reg = <0x4806e000 0x100>;
 453                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 454                         ti,hwmods = "uart4";
 455                         clock-frequency = <48000000>;
 456                 };
 457
 458                 uart5: serial@48066000 {
 459                         compatible = "ti,omap4-uart";
 460                         reg = <0x48066000 0x100>;
 461                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 462                         ti,hwmods = "uart5";
 463                         clock-frequency = <48000000>;
 464                 };
 465
 466                 uart6: serial@48068000 {
 467                         compatible = "ti,omap4-uart";
 468                         reg = <0x48068000 0x100>;
 469                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 470                         ti,hwmods = "uart6";
 471                         clock-frequency = <48000000>;
 472                 };
 473
 474                 mmc1: mmc@4809c000 {
 475                         compatible = "ti,omap4-hsmmc";
 476                         reg = <0x4809c000 0x400>;
 477                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 478                         ti,hwmods = "mmc1";
 479                         ti,dual-volt;
 480                         ti,needs-special-reset;
 481                         dmas = <&sdma 61>, <&sdma 62>;
 482                         dma-names = "tx", "rx";
 483                 };
 484
 485                 mmc2: mmc@480b4000 {
 486                         compatible = "ti,omap4-hsmmc";
 487                         reg = <0x480b4000 0x400>;
 488                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 489                         ti,hwmods = "mmc2";
 490                         ti,needs-special-reset;
 491                         dmas = <&sdma 47>, <&sdma 48>;
 492                         dma-names = "tx", "rx";
 493                 };
 494
 495                 mmc3: mmc@480ad000 {
 496                         compatible = "ti,omap4-hsmmc";
 497                         reg = <0x480ad000 0x400>;
 498                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 499                         ti,hwmods = "mmc3";
 500                         ti,needs-special-reset;
 501                         dmas = <&sdma 77>, <&sdma 78>;
 502                         dma-names = "tx", "rx";
 503                 };
 504
 505                 mmc4: mmc@480d1000 {
 506                         compatible = "ti,omap4-hsmmc";
 507                         reg = <0x480d1000 0x400>;
 508                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 509                         ti,hwmods = "mmc4";
 510                         ti,needs-special-reset;
 511                         dmas = <&sdma 57>, <&sdma 58>;
 512                         dma-names = "tx", "rx";
 513                 };
 514
 515                 mmc5: mmc@480d5000 {
 516                         compatible = "ti,omap4-hsmmc";
 517                         reg = <0x480d5000 0x400>;
 518                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 519                         ti,hwmods = "mmc5";
 520                         ti,needs-special-reset;
 521                         dmas = <&sdma 59>, <&sdma 60>;
 522                         dma-names = "tx", "rx";
 523                 };
 524
 525                 mmu_dsp: mmu@4a066000 {
 526                         compatible = "ti,omap4-iommu";
 527                         reg = <0x4a066000 0x100>;
 528                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 529                         ti,hwmods = "mmu_dsp";
 530                 };
 531
 532                 mmu_ipu: mmu@55082000 {
 533                         compatible = "ti,omap4-iommu";
 534                         reg = <0x55082000 0x100>;
 535                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 536                         ti,hwmods = "mmu_ipu";
 537                         ti,iommu-bus-err-back;
 538                 };
 539
 540                 keypad: keypad@4ae1c000 {
 541                         compatible = "ti,omap4-keypad";
 542                         reg = <0x4ae1c000 0x400>;
 543                         ti,hwmods = "kbd";
 544                 };
 545
 546                 mcpdm: mcpdm@40132000 {
 547                         compatible = "ti,omap4-mcpdm";
 548                         reg = <0x40132000 0x7f>, /* MPU private access */
 549                               <0x49032000 0x7f>; /* L3 Interconnect */
 550                         reg-names = "mpu", "dma";
 551                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 552                         ti,hwmods = "mcpdm";
 553                         dmas = <&sdma 65>,
 554                                <&sdma 66>;
 555                         dma-names = "up_link", "dn_link";
 556                         status = "disabled";
 557                 };
 558
 559                 dmic: dmic@4012e000 {
 560                         compatible = "ti,omap4-dmic";
 561                         reg = <0x4012e000 0x7f>, /* MPU private access */
 562                               <0x4902e000 0x7f>; /* L3 Interconnect */
 563                         reg-names = "mpu", "dma";
 564                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 565                         ti,hwmods = "dmic";
 566                         dmas = <&sdma 67>;
 567                         dma-names = "up_link";
 568                         status = "disabled";
 569                 };
 570
 571                 mcbsp1: mcbsp@40122000 {
 572                         compatible = "ti,omap4-mcbsp";
 573                         reg = <0x40122000 0xff>, /* MPU private access */
 574                               <0x49022000 0xff>; /* L3 Interconnect */
 575                         reg-names = "mpu", "dma";
 576                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 577                         interrupt-names = "common";
 578                         ti,buffer-size = <128>;
 579                         ti,hwmods = "mcbsp1";
 580                         dmas = <&sdma 33>,
 581                                <&sdma 34>;
 582                         dma-names = "tx", "rx";
 583                         status = "disabled";
 584                 };
 585
 586                 mcbsp2: mcbsp@40124000 {
 587                         compatible = "ti,omap4-mcbsp";
 588                         reg = <0x40124000 0xff>, /* MPU private access */
 589                               <0x49024000 0xff>; /* L3 Interconnect */
 590                         reg-names = "mpu", "dma";
 591                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 592                         interrupt-names = "common";
 593                         ti,buffer-size = <128>;
 594                         ti,hwmods = "mcbsp2";
 595                         dmas = <&sdma 17>,
 596                                <&sdma 18>;
 597                         dma-names = "tx", "rx";
 598                         status = "disabled";
 599                 };
 600
 601                 mcbsp3: mcbsp@40126000 {
 602                         compatible = "ti,omap4-mcbsp";
 603                         reg = <0x40126000 0xff>, /* MPU private access */
 604                               <0x49026000 0xff>; /* L3 Interconnect */
 605                         reg-names = "mpu", "dma";
 606                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 607                         interrupt-names = "common";
 608                         ti,buffer-size = <128>;
 609                         ti,hwmods = "mcbsp3";
 610                         dmas = <&sdma 19>,
 611                                <&sdma 20>;
 612                         dma-names = "tx", "rx";
 613                         status = "disabled";
 614                 };
 615
 616                 timer1: timer@4ae18000 {
 617                         compatible = "ti,omap5430-timer";
 618                         reg = <0x4ae18000 0x80>;
 619                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 620                         ti,hwmods = "timer1";
 621                         ti,timer-alwon;
 622                 };
 623
 624                 timer2: timer@48032000 {
 625                         compatible = "ti,omap5430-timer";
 626                         reg = <0x48032000 0x80>;
 627                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 628                         ti,hwmods = "timer2";
 629                 };
 630
 631                 timer3: timer@48034000 {
 632                         compatible = "ti,omap5430-timer";
 633                         reg = <0x48034000 0x80>;
 634                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 635                         ti,hwmods = "timer3";
 636                 };
 637
 638                 timer4: timer@48036000 {
 639                         compatible = "ti,omap5430-timer";
 640                         reg = <0x48036000 0x80>;
 641                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 642                         ti,hwmods = "timer4";
 643                 };
 644
 645                 timer5: timer@40138000 {
 646                         compatible = "ti,omap5430-timer";
 647                         reg = <0x40138000 0x80>,
 648                               <0x49038000 0x80>;
 649                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 650                         ti,hwmods = "timer5";
 651                         ti,timer-dsp;
 652                         ti,timer-pwm;
 653                 };
 654
 655                 timer6: timer@4013a000 {
 656                         compatible = "ti,omap5430-timer";
 657                         reg = <0x4013a000 0x80>,
 658                               <0x4903a000 0x80>;
 659                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 660                         ti,hwmods = "timer6";
 661                         ti,timer-dsp;
 662                         ti,timer-pwm;
 663                 };
 664
 665                 timer7: timer@4013c000 {
 666                         compatible = "ti,omap5430-timer";
 667                         reg = <0x4013c000 0x80>,
 668                               <0x4903c000 0x80>;
 669                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 670                         ti,hwmods = "timer7";
 671                         ti,timer-dsp;
 672                 };
 673
 674                 timer8: timer@4013e000 {
 675                         compatible = "ti,omap5430-timer";
 676                         reg = <0x4013e000 0x80>,
 677                               <0x4903e000 0x80>;
 678                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 679                         ti,hwmods = "timer8";
 680                         ti,timer-dsp;
 681                         ti,timer-pwm;
 682                 };
 683
 684                 timer9: timer@4803e000 {
 685                         compatible = "ti,omap5430-timer";
 686                         reg = <0x4803e000 0x80>;
 687                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 688                         ti,hwmods = "timer9";
 689                         ti,timer-pwm;
 690                 };
 691
 692                 timer10: timer@48086000 {
 693                         compatible = "ti,omap5430-timer";
 694                         reg = <0x48086000 0x80>;
 695                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 696                         ti,hwmods = "timer10";
 697                         ti,timer-pwm;
 698                 };
 699
 700                 timer11: timer@48088000 {
 701                         compatible = "ti,omap5430-timer";
 702                         reg = <0x48088000 0x80>;
 703                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 704                         ti,hwmods = "timer11";
 705                         ti,timer-pwm;
 706                 };
 707
 708                 wdt2: wdt@4ae14000 {
 709                         compatible = "ti,omap5-wdt", "ti,omap3-wdt";
 710                         reg = <0x4ae14000 0x80>;
 711                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 712                         ti,hwmods = "wd_timer2";
 713                 };
 714
 715                 dmm@4e000000 {
 716                         compatible = "ti,omap5-dmm";
 717                         reg = <0x4e000000 0x800>;
 718                         interrupts = <0 113 0x4>;
 719                         ti,hwmods = "dmm";
 720                 };
 721
 722                 emif1: emif@4c000000 {
 723                         compatible      = "ti,emif-4d5";
 724                         ti,hwmods       = "emif1";
 725                         ti,no-idle-on-init;
 726                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 727                         reg = <0x4c000000 0x400>;
 728                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 729                         hw-caps-read-idle-ctrl;
 730                         hw-caps-ll-interface;
 731                         hw-caps-temp-alert;
 732                 };
 733
 734                 emif2: emif@4d000000 {
 735                         compatible      = "ti,emif-4d5";
 736                         ti,hwmods       = "emif2";
 737                         ti,no-idle-on-init;
 738                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 739                         reg = <0x4d000000 0x400>;
 740                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 741                         hw-caps-read-idle-ctrl;
 742                         hw-caps-ll-interface;
 743                         hw-caps-temp-alert;
 744                 };
 745
 746                 omap_control_usb2phy: control-phy@4a002300 {
 747                         compatible = "ti,control-phy-usb2";
 748                         reg = <0x4a002300 0x4>;
 749                         reg-names = "power";
 750                 };
 751
 752                 omap_control_usb3phy: control-phy@4a002370 {
 753                         compatible = "ti,control-phy-pipe3";
 754                         reg = <0x4a002370 0x4>;
 755                         reg-names = "power";
 756                 };
 757
 758                 usb3: omap_dwc3@4a020000 {
 759                         compatible = "ti,dwc3";
 760                         ti,hwmods = "usb_otg_ss";
 761                         reg = <0x4a020000 0x10000>;
 762                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 763                         #address-cells = <1>;
 764                         #size-cells = <1>;
 765                         utmi-mode = <2>;
 766                         ranges;
 767                         dwc3@4a030000 {
 768                                 compatible = "snps,dwc3";
 769                                 reg = <0x4a030000 0x10000>;
 770                                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 771                                 phys = <&usb2_phy>, <&usb3_phy>;
 772                                 phy-names = "usb2-phy", "usb3-phy";
 773                                 dr_mode = "peripheral";
 774                                 tx-fifo-resize;
 775                         };
 776                 };
 777
 778                 ocp2scp@4a080000 {
 779                         compatible = "ti,omap-ocp2scp";
 780                         #address-cells = <1>;
 781                         #size-cells = <1>;
 782                         reg = <0x4a080000 0x20>;
 783                         ranges;
 784                         ti,hwmods = "ocp2scp1";
 785                         usb2_phy: usb2phy@4a084000 {
 786                                 compatible = "ti,omap-usb2";
 787                                 reg = <0x4a084000 0x7c>;
 788                                 ctrl-module = <&omap_control_usb2phy>;
 789                                 #phy-cells = <0>;
 790                         };
 791
 792                         usb3_phy: usb3phy@4a084400 {
 793                                 compatible = "ti,omap-usb3";
 794                                 reg = <0x4a084400 0x80>,
 795                                       <0x4a084800 0x64>,
 796                                       <0x4a084c00 0x40>;
 797                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
 798                                 ctrl-module = <&omap_control_usb3phy>;
 799                                 #phy-cells = <0>;
 800                         };
 801                 };
 802
 803                 usbhstll: usbhstll@4a062000 {
 804                         compatible = "ti,usbhs-tll";
 805                         reg = <0x4a062000 0x1000>;
 806                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 807                         ti,hwmods = "usb_tll_hs";
 808                 };
 809
 810                 usbhshost: usbhshost@4a064000 {
 811                         compatible = "ti,usbhs-host";
 812                         reg = <0x4a064000 0x800>;
 813                         ti,hwmods = "usb_host_hs";
 814                         #address-cells = <1>;
 815                         #size-cells = <1>;
 816                         ranges;
 817                         clocks = <&l3init_60m_fclk>,
 818                                  <&xclk60mhsp1_ck>,
 819                                  <&xclk60mhsp2_ck>;
 820                         clock-names = "refclk_60m_int",
 821                                       "refclk_60m_ext_p1",
 822                                       "refclk_60m_ext_p2";
 823
 824                         usbhsohci: ohci@4a064800 {
 825                                 compatible = "ti,ohci-omap3";
 826                                 reg = <0x4a064800 0x400>;
 827                                 interrupt-parent = <&gic>;
 828                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 829                         };
 830
 831                         usbhsehci: ehci@4a064c00 {
 832                                 compatible = "ti,ehci-omap";
 833                                 reg = <0x4a064c00 0x400>;
 834                                 interrupt-parent = <&gic>;
 835                                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 836                         };
 837                 };
 838
 839                 bandgap: bandgap@4a0021e0 {
 840                         reg = <0x4a0021e0 0xc
 841                                0x4a00232c 0xc
 842                                0x4a002380 0x2c
 843                                0x4a0023C0 0x3c>;
 844                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 845                         compatible = "ti,omap5430-bandgap";
 846
 847                         #thermal-sensor-cells = <1>;
 848                 };
 849         };
 850 };
 851
 852 /include/ "omap54xx-clocks.dtsi"