arch/arm/boot/dts/imx6qdl.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include "skeleton.dtsi"
  14
  15 / {
  16         aliases {
  17                 serial0 = &uart1;
  18                 serial1 = &uart2;
  19                 serial2 = &uart3;
  20                 serial3 = &uart4;
  21                 serial4 = &uart5;
  22                 gpio0 = &gpio1;
  23                 gpio1 = &gpio2;
  24                 gpio2 = &gpio3;
  25                 gpio3 = &gpio4;
  26                 gpio4 = &gpio5;
  27                 gpio5 = &gpio6;
  28                 gpio6 = &gpio7;
  29         };
  30
  31         intc: interrupt-controller@00a01000 {
  32                 compatible = "arm,cortex-a9-gic";
  33                 #interrupt-cells = <3>;
  34                 #address-cells = <1>;
  35                 #size-cells = <1>;
  36                 interrupt-controller;
  37                 reg = <0x00a01000 0x1000>,
  38                       <0x00a00100 0x100>;
  39         };
  40
  41         clocks {
  42                 #address-cells = <1>;
  43                 #size-cells = <0>;
  44
  45                 ckil {
  46                         compatible = "fsl,imx-ckil", "fixed-clock";
  47                         clock-frequency = <32768>;
  48                 };
  49
  50                 ckih1 {
  51                         compatible = "fsl,imx-ckih1", "fixed-clock";
  52                         clock-frequency = <0>;
  53                 };
  54
  55                 osc {
  56                         compatible = "fsl,imx-osc", "fixed-clock";
  57                         clock-frequency = <24000000>;
  58                 };
  59         };
  60
  61         soc {
  62                 #address-cells = <1>;
  63                 #size-cells = <1>;
  64                 compatible = "simple-bus";
  65                 interrupt-parent = <&intc>;
  66                 ranges;
  67
  68                 dma-apbh@00110000 {
  69                         compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
  70                         reg = <0x00110000 0x2000>;
  71                         clocks = <&clks 106>;
  72                 };
  73
  74                 gpmi: gpmi-nand@00112000 {
  75                         compatible = "fsl,imx6q-gpmi-nand";
  76                         #address-cells = <1>;
  77                         #size-cells = <1>;
  78                         reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
  79                         reg-names = "gpmi-nand", "bch";
  80                         interrupts = <0 13 0x04>, <0 15 0x04>;
  81                         interrupt-names = "gpmi-dma", "bch";
  82                         clocks = <&clks 152>, <&clks 153>, <&clks 151>,
  83                                  <&clks 150>, <&clks 149>;
  84                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
  85                                       "gpmi_bch_apb", "per1_bch";
  86                         fsl,gpmi-dma-channel = <0>;
  87                         status = "disabled";
  88                 };
  89
  90                 timer@00a00600 {
  91                         compatible = "arm,cortex-a9-twd-timer";
  92                         reg = <0x00a00600 0x20>;
  93                         interrupts = <1 13 0xf01>;
  94                 };
  95
  96                 L2: l2-cache@00a02000 {
  97                         compatible = "arm,pl310-cache";
  98                         reg = <0x00a02000 0x1000>;
  99                         interrupts = <0 92 0x04>;
 100                         cache-unified;
 101                         cache-level = <2>;
 102                 };
 103
 104                 pmu {
 105                         compatible = "arm,cortex-a9-pmu";
 106                         interrupts = <0 94 0x04>;
 107                 };
 108
 109                 aips-bus@02000000 { /* AIPS1 */
 110                         compatible = "fsl,aips-bus", "simple-bus";
 111                         #address-cells = <1>;
 112                         #size-cells = <1>;
 113                         reg = <0x02000000 0x100000>;
 114                         ranges;
 115
 116                         spba-bus@02000000 {
 117                                 compatible = "fsl,spba-bus", "simple-bus";
 118                                 #address-cells = <1>;
 119                                 #size-cells = <1>;
 120                                 reg = <0x02000000 0x40000>;
 121                                 ranges;
 122
 123                                 spdif: spdif@02004000 {
 124                                         reg = <0x02004000 0x4000>;
 125                                         interrupts = <0 52 0x04>;
 126                                 };
 127
 128                                 ecspi1: ecspi@02008000 {
 129                                         #address-cells = <1>;
 130                                         #size-cells = <0>;
 131                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 132                                         reg = <0x02008000 0x4000>;
 133                                         interrupts = <0 31 0x04>;
 134                                         clocks = <&clks 112>, <&clks 112>;
 135                                         clock-names = "ipg", "per";
 136                                         status = "disabled";
 137                                 };
 138
 139                                 ecspi2: ecspi@0200c000 {
 140                                         #address-cells = <1>;
 141                                         #size-cells = <0>;
 142                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 143                                         reg = <0x0200c000 0x4000>;
 144                                         interrupts = <0 32 0x04>;
 145                                         clocks = <&clks 113>, <&clks 113>;
 146                                         clock-names = "ipg", "per";
 147                                         status = "disabled";
 148                                 };
 149
 150                                 ecspi3: ecspi@02010000 {
 151                                         #address-cells = <1>;
 152                                         #size-cells = <0>;
 153                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 154                                         reg = <0x02010000 0x4000>;
 155                                         interrupts = <0 33 0x04>;
 156                                         clocks = <&clks 114>, <&clks 114>;
 157                                         clock-names = "ipg", "per";
 158                                         status = "disabled";
 159                                 };
 160
 161                                 ecspi4: ecspi@02014000 {
 162                                         #address-cells = <1>;
 163                                         #size-cells = <0>;
 164                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 165                                         reg = <0x02014000 0x4000>;
 166                                         interrupts = <0 34 0x04>;
 167                                         clocks = <&clks 115>, <&clks 115>;
 168                                         clock-names = "ipg", "per";
 169                                         status = "disabled";
 170                                 };
 171
 172                                 uart1: serial@02020000 {
 173                                         compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 174                                         reg = <0x02020000 0x4000>;
 175                                         interrupts = <0 26 0x04>;
 176                                         clocks = <&clks 160>, <&clks 161>;
 177                                         clock-names = "ipg", "per";
 178                                         status = "disabled";
 179                                 };
 180
 181                                 esai: esai@02024000 {
 182                                         reg = <0x02024000 0x4000>;
 183                                         interrupts = <0 51 0x04>;
 184                                 };
 185
 186                                 ssi1: ssi@02028000 {
 187                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 188                                         reg = <0x02028000 0x4000>;
 189                                         interrupts = <0 46 0x04>;
 190                                         clocks = <&clks 178>;
 191                                         fsl,fifo-depth = <15>;
 192                                         fsl,ssi-dma-events = <38 37>;
 193                                         status = "disabled";
 194                                 };
 195
 196                                 ssi2: ssi@0202c000 {
 197                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 198                                         reg = <0x0202c000 0x4000>;
 199                                         interrupts = <0 47 0x04>;
 200                                         clocks = <&clks 179>;
 201                                         fsl,fifo-depth = <15>;
 202                                         fsl,ssi-dma-events = <42 41>;
 203                                         status = "disabled";
 204                                 };
 205
 206                                 ssi3: ssi@02030000 {
 207                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 208                                         reg = <0x02030000 0x4000>;
 209                                         interrupts = <0 48 0x04>;
 210                                         clocks = <&clks 180>;
 211                                         fsl,fifo-depth = <15>;
 212                                         fsl,ssi-dma-events = <46 45>;
 213                                         status = "disabled";
 214                                 };
 215
 216                                 asrc: asrc@02034000 {
 217                                         reg = <0x02034000 0x4000>;
 218                                         interrupts = <0 50 0x04>;
 219                                 };
 220
 221                                 spba@0203c000 {
 222                                         reg = <0x0203c000 0x4000>;
 223                                 };
 224                         };
 225
 226                         vpu: vpu@02040000 {
 227                                 reg = <0x02040000 0x3c000>;
 228                                 interrupts = <0 3 0x04 0 12 0x04>;
 229                         };
 230
 231                         aipstz@0207c000 { /* AIPSTZ1 */
 232                                 reg = <0x0207c000 0x4000>;
 233                         };
 234
 235                         pwm1: pwm@02080000 {
 236                                 #pwm-cells = <2>;
 237                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 238                                 reg = <0x02080000 0x4000>;
 239                                 interrupts = <0 83 0x04>;
 240                                 clocks = <&clks 62>, <&clks 145>;
 241                                 clock-names = "ipg", "per";
 242                         };
 243
 244                         pwm2: pwm@02084000 {
 245                                 #pwm-cells = <2>;
 246                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 247                                 reg = <0x02084000 0x4000>;
 248                                 interrupts = <0 84 0x04>;
 249                                 clocks = <&clks 62>, <&clks 146>;
 250                                 clock-names = "ipg", "per";
 251                         };
 252
 253                         pwm3: pwm@02088000 {
 254                                 #pwm-cells = <2>;
 255                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 256                                 reg = <0x02088000 0x4000>;
 257                                 interrupts = <0 85 0x04>;
 258                                 clocks = <&clks 62>, <&clks 147>;
 259                                 clock-names = "ipg", "per";
 260                         };
 261
 262                         pwm4: pwm@0208c000 {
 263                                 #pwm-cells = <2>;
 264                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 265                                 reg = <0x0208c000 0x4000>;
 266                                 interrupts = <0 86 0x04>;
 267                                 clocks = <&clks 62>, <&clks 148>;
 268                                 clock-names = "ipg", "per";
 269                         };
 270
 271                         can1: flexcan@02090000 {
 272                                 reg = <0x02090000 0x4000>;
 273                                 interrupts = <0 110 0x04>;
 274                         };
 275
 276                         can2: flexcan@02094000 {
 277                                 reg = <0x02094000 0x4000>;
 278                                 interrupts = <0 111 0x04>;
 279                         };
 280
 281                         gpt: gpt@02098000 {
 282                                 compatible = "fsl,imx6q-gpt";
 283                                 reg = <0x02098000 0x4000>;
 284                                 interrupts = <0 55 0x04>;
 285                                 clocks = <&clks 119>, <&clks 120>;
 286                                 clock-names = "ipg", "per";
 287                         };
 288
 289                         gpio1: gpio@0209c000 {
 290                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 291                                 reg = <0x0209c000 0x4000>;
 292                                 interrupts = <0 66 0x04 0 67 0x04>;
 293                                 gpio-controller;
 294                                 #gpio-cells = <2>;
 295                                 interrupt-controller;
 296                                 #interrupt-cells = <2>;
 297                         };
 298
 299                         gpio2: gpio@020a0000 {
 300                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 301                                 reg = <0x020a0000 0x4000>;
 302                                 interrupts = <0 68 0x04 0 69 0x04>;
 303                                 gpio-controller;
 304                                 #gpio-cells = <2>;
 305                                 interrupt-controller;
 306                                 #interrupt-cells = <2>;
 307                         };
 308
 309                         gpio3: gpio@020a4000 {
 310                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 311                                 reg = <0x020a4000 0x4000>;
 312                                 interrupts = <0 70 0x04 0 71 0x04>;
 313                                 gpio-controller;
 314                                 #gpio-cells = <2>;
 315                                 interrupt-controller;
 316                                 #interrupt-cells = <2>;
 317                         };
 318
 319                         gpio4: gpio@020a8000 {
 320                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 321                                 reg = <0x020a8000 0x4000>;
 322                                 interrupts = <0 72 0x04 0 73 0x04>;
 323                                 gpio-controller;
 324                                 #gpio-cells = <2>;
 325                                 interrupt-controller;
 326                                 #interrupt-cells = <2>;
 327                         };
 328
 329                         gpio5: gpio@020ac000 {
 330                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 331                                 reg = <0x020ac000 0x4000>;
 332                                 interrupts = <0 74 0x04 0 75 0x04>;
 333                                 gpio-controller;
 334                                 #gpio-cells = <2>;
 335                                 interrupt-controller;
 336                                 #interrupt-cells = <2>;
 337                         };
 338
 339                         gpio6: gpio@020b0000 {
 340                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 341                                 reg = <0x020b0000 0x4000>;
 342                                 interrupts = <0 76 0x04 0 77 0x04>;
 343                                 gpio-controller;
 344                                 #gpio-cells = <2>;
 345                                 interrupt-controller;
 346                                 #interrupt-cells = <2>;
 347                         };
 348
 349                         gpio7: gpio@020b4000 {
 350                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 351                                 reg = <0x020b4000 0x4000>;
 352                                 interrupts = <0 78 0x04 0 79 0x04>;
 353                                 gpio-controller;
 354                                 #gpio-cells = <2>;
 355                                 interrupt-controller;
 356                                 #interrupt-cells = <2>;
 357                         };
 358
 359                         kpp: kpp@020b8000 {
 360                                 reg = <0x020b8000 0x4000>;
 361                                 interrupts = <0 82 0x04>;
 362                         };
 363
 364                         wdog1: wdog@020bc000 {
 365                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 366                                 reg = <0x020bc000 0x4000>;
 367                                 interrupts = <0 80 0x04>;
 368                                 clocks = <&clks 0>;
 369                         };
 370
 371                         wdog2: wdog@020c0000 {
 372                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 373                                 reg = <0x020c0000 0x4000>;
 374                                 interrupts = <0 81 0x04>;
 375                                 clocks = <&clks 0>;
 376                                 status = "disabled";
 377                         };
 378
 379                         clks: ccm@020c4000 {
 380                                 compatible = "fsl,imx6q-ccm";
 381                                 reg = <0x020c4000 0x4000>;
 382                                 interrupts = <0 87 0x04 0 88 0x04>;
 383                                 #clock-cells = <1>;
 384                         };
 385
 386                         anatop: anatop@020c8000 {
 387                                 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
 388                                 reg = <0x020c8000 0x1000>;
 389                                 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
 390
 391                                 regulator-1p1@110 {
 392                                         compatible = "fsl,anatop-regulator";
 393                                         regulator-name = "vdd1p1";
 394                                         regulator-min-microvolt = <800000>;
 395                                         regulator-max-microvolt = <1375000>;
 396                                         regulator-always-on;
 397                                         anatop-reg-offset = <0x110>;
 398                                         anatop-vol-bit-shift = <8>;
 399                                         anatop-vol-bit-width = <5>;
 400                                         anatop-min-bit-val = <4>;
 401                                         anatop-min-voltage = <800000>;
 402                                         anatop-max-voltage = <1375000>;
 403                                 };
 404
 405                                 regulator-3p0@120 {
 406                                         compatible = "fsl,anatop-regulator";
 407                                         regulator-name = "vdd3p0";
 408                                         regulator-min-microvolt = <2800000>;
 409                                         regulator-max-microvolt = <3150000>;
 410                                         regulator-always-on;
 411                                         anatop-reg-offset = <0x120>;
 412                                         anatop-vol-bit-shift = <8>;
 413                                         anatop-vol-bit-width = <5>;
 414                                         anatop-min-bit-val = <0>;
 415                                         anatop-min-voltage = <2625000>;
 416                                         anatop-max-voltage = <3400000>;
 417                                 };
 418
 419                                 regulator-2p5@130 {
 420                                         compatible = "fsl,anatop-regulator";
 421                                         regulator-name = "vdd2p5";
 422                                         regulator-min-microvolt = <2000000>;
 423                                         regulator-max-microvolt = <2750000>;
 424                                         regulator-always-on;
 425                                         anatop-reg-offset = <0x130>;
 426                                         anatop-vol-bit-shift = <8>;
 427                                         anatop-vol-bit-width = <5>;
 428                                         anatop-min-bit-val = <0>;
 429                                         anatop-min-voltage = <2000000>;
 430                                         anatop-max-voltage = <2750000>;
 431                                 };
 432
 433                                 reg_arm: regulator-vddcore@140 {
 434                                         compatible = "fsl,anatop-regulator";
 435                                         regulator-name = "cpu";
 436                                         regulator-min-microvolt = <725000>;
 437                                         regulator-max-microvolt = <1450000>;
 438                                         regulator-always-on;
 439                                         anatop-reg-offset = <0x140>;
 440                                         anatop-vol-bit-shift = <0>;
 441                                         anatop-vol-bit-width = <5>;
 442                                         anatop-delay-reg-offset = <0x170>;
 443                                         anatop-delay-bit-shift = <24>;
 444                                         anatop-delay-bit-width = <2>;
 445                                         anatop-min-bit-val = <1>;
 446                                         anatop-min-voltage = <725000>;
 447                                         anatop-max-voltage = <1450000>;
 448                                 };
 449
 450                                 reg_pu: regulator-vddpu@140 {
 451                                         compatible = "fsl,anatop-regulator";
 452                                         regulator-name = "vddpu";
 453                                         regulator-min-microvolt = <725000>;
 454                                         regulator-max-microvolt = <1450000>;
 455                                         regulator-always-on;
 456                                         anatop-reg-offset = <0x140>;
 457                                         anatop-vol-bit-shift = <9>;
 458                                         anatop-vol-bit-width = <5>;
 459                                         anatop-delay-reg-offset = <0x170>;
 460                                         anatop-delay-bit-shift = <26>;
 461                                         anatop-delay-bit-width = <2>;
 462                                         anatop-min-bit-val = <1>;
 463                                         anatop-min-voltage = <725000>;
 464                                         anatop-max-voltage = <1450000>;
 465                                 };
 466
 467                                 reg_soc: regulator-vddsoc@140 {
 468                                         compatible = "fsl,anatop-regulator";
 469                                         regulator-name = "vddsoc";
 470                                         regulator-min-microvolt = <725000>;
 471                                         regulator-max-microvolt = <1450000>;
 472                                         regulator-always-on;
 473                                         anatop-reg-offset = <0x140>;
 474                                         anatop-vol-bit-shift = <18>;
 475                                         anatop-vol-bit-width = <5>;
 476                                         anatop-delay-reg-offset = <0x170>;
 477                                         anatop-delay-bit-shift = <28>;
 478                                         anatop-delay-bit-width = <2>;
 479                                         anatop-min-bit-val = <1>;
 480                                         anatop-min-voltage = <725000>;
 481                                         anatop-max-voltage = <1450000>;
 482                                 };
 483                         };
 484
 485                         usbphy1: usbphy@020c9000 {
 486                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 487                                 reg = <0x020c9000 0x1000>;
 488                                 interrupts = <0 44 0x04>;
 489                                 clocks = <&clks 182>;
 490                         };
 491
 492                         usbphy2: usbphy@020ca000 {
 493                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 494                                 reg = <0x020ca000 0x1000>;
 495                                 interrupts = <0 45 0x04>;
 496                                 clocks = <&clks 183>;
 497                         };
 498
 499                         snvs@020cc000 {
 500                                 compatible = "fsl,sec-v4.0-mon", "simple-bus";
 501                                 #address-cells = <1>;
 502                                 #size-cells = <1>;
 503                                 ranges = <0 0x020cc000 0x4000>;
 504
 505                                 snvs-rtc-lp@34 {
 506                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 507                                         reg = <0x34 0x58>;
 508                                         interrupts = <0 19 0x04 0 20 0x04>;
 509                                 };
 510                         };
 511
 512                         epit1: epit@020d0000 { /* EPIT1 */
 513                                 reg = <0x020d0000 0x4000>;
 514                                 interrupts = <0 56 0x04>;
 515                         };
 516
 517                         epit2: epit@020d4000 { /* EPIT2 */
 518                                 reg = <0x020d4000 0x4000>;
 519                                 interrupts = <0 57 0x04>;
 520                         };
 521
 522                         src: src@020d8000 {
 523                                 compatible = "fsl,imx6q-src";
 524                                 reg = <0x020d8000 0x4000>;
 525                                 interrupts = <0 91 0x04 0 96 0x04>;
 526                         };
 527
 528                         gpc: gpc@020dc000 {
 529                                 compatible = "fsl,imx6q-gpc";
 530                                 reg = <0x020dc000 0x4000>;
 531                                 interrupts = <0 89 0x04 0 90 0x04>;
 532                         };
 533
 534                         gpr: iomuxc-gpr@020e0000 {
 535                                 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
 536                                 reg = <0x020e0000 0x38>;
 537                         };
 538
 539                         dcic1: dcic@020e4000 {
 540                                 reg = <0x020e4000 0x4000>;
 541                                 interrupts = <0 124 0x04>;
 542                         };
 543
 544                         dcic2: dcic@020e8000 {
 545                                 reg = <0x020e8000 0x4000>;
 546                                 interrupts = <0 125 0x04>;
 547                         };
 548
 549                         sdma: sdma@020ec000 {
 550                                 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
 551                                 reg = <0x020ec000 0x4000>;
 552                                 interrupts = <0 2 0x04>;
 553                                 clocks = <&clks 155>, <&clks 155>;
 554                                 clock-names = "ipg", "ahb";
 555                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 556                         };
 557                 };
 558
 559                 aips-bus@02100000 { /* AIPS2 */
 560                         compatible = "fsl,aips-bus", "simple-bus";
 561                         #address-cells = <1>;
 562                         #size-cells = <1>;
 563                         reg = <0x02100000 0x100000>;
 564                         ranges;
 565
 566                         caam@02100000 {
 567                                 reg = <0x02100000 0x40000>;
 568                                 interrupts = <0 105 0x04 0 106 0x04>;
 569                         };
 570
 571                         aipstz@0217c000 { /* AIPSTZ2 */
 572                                 reg = <0x0217c000 0x4000>;
 573                         };
 574
 575                         usbotg: usb@02184000 {
 576                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 577                                 reg = <0x02184000 0x200>;
 578                                 interrupts = <0 43 0x04>;
 579                                 clocks = <&clks 162>;
 580                                 fsl,usbphy = <&usbphy1>;
 581                                 fsl,usbmisc = <&usbmisc 0>;
 582                                 status = "disabled";
 583                         };
 584
 585                         usbh1: usb@02184200 {
 586                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 587                                 reg = <0x02184200 0x200>;
 588                                 interrupts = <0 40 0x04>;
 589                                 clocks = <&clks 162>;
 590                                 fsl,usbphy = <&usbphy2>;
 591                                 fsl,usbmisc = <&usbmisc 1>;
 592                                 status = "disabled";
 593                         };
 594
 595                         usbh2: usb@02184400 {
 596                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 597                                 reg = <0x02184400 0x200>;
 598                                 interrupts = <0 41 0x04>;
 599                                 clocks = <&clks 162>;
 600                                 fsl,usbmisc = <&usbmisc 2>;
 601                                 status = "disabled";
 602                         };
 603
 604                         usbh3: usb@02184600 {
 605                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 606                                 reg = <0x02184600 0x200>;
 607                                 interrupts = <0 42 0x04>;
 608                                 clocks = <&clks 162>;
 609                                 fsl,usbmisc = <&usbmisc 3>;
 610                                 status = "disabled";
 611                         };
 612
 613                         usbmisc: usbmisc: usbmisc@02184800 {
 614                                 #index-cells = <1>;
 615                                 compatible = "fsl,imx6q-usbmisc";
 616                                 reg = <0x02184800 0x200>;
 617                                 clocks = <&clks 162>;
 618                         };
 619
 620                         fec: ethernet@02188000 {
 621                                 compatible = "fsl,imx6q-fec";
 622                                 reg = <0x02188000 0x4000>;
 623                                 interrupts = <0 118 0x04 0 119 0x04>;
 624                                 clocks = <&clks 117>, <&clks 117>, <&clks 190>;
 625                                 clock-names = "ipg", "ahb", "ptp";
 626                                 status = "disabled";
 627                         };
 628
 629                         mlb@0218c000 {
 630                                 reg = <0x0218c000 0x4000>;
 631                                 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
 632                         };
 633
 634                         usdhc1: usdhc@02190000 {
 635                                 compatible = "fsl,imx6q-usdhc";
 636                                 reg = <0x02190000 0x4000>;
 637                                 interrupts = <0 22 0x04>;
 638                                 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
 639                                 clock-names = "ipg", "ahb", "per";
 640                                 bus-width = <4>;
 641                                 status = "disabled";
 642                         };
 643
 644                         usdhc2: usdhc@02194000 {
 645                                 compatible = "fsl,imx6q-usdhc";
 646                                 reg = <0x02194000 0x4000>;
 647                                 interrupts = <0 23 0x04>;
 648                                 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
 649                                 clock-names = "ipg", "ahb", "per";
 650                                 bus-width = <4>;
 651                                 status = "disabled";
 652                         };
 653
 654                         usdhc3: usdhc@02198000 {
 655                                 compatible = "fsl,imx6q-usdhc";
 656                                 reg = <0x02198000 0x4000>;
 657                                 interrupts = <0 24 0x04>;
 658                                 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
 659                                 clock-names = "ipg", "ahb", "per";
 660                                 bus-width = <4>;
 661                                 status = "disabled";
 662                         };
 663
 664                         usdhc4: usdhc@0219c000 {
 665                                 compatible = "fsl,imx6q-usdhc";
 666                                 reg = <0x0219c000 0x4000>;
 667                                 interrupts = <0 25 0x04>;
 668                                 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
 669                                 clock-names = "ipg", "ahb", "per";
 670                                 bus-width = <4>;
 671                                 status = "disabled";
 672                         };
 673
 674                         i2c1: i2c@021a0000 {
 675                                 #address-cells = <1>;
 676                                 #size-cells = <0>;
 677                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 678                                 reg = <0x021a0000 0x4000>;
 679                                 interrupts = <0 36 0x04>;
 680                                 clocks = <&clks 125>;
 681                                 status = "disabled";
 682                         };
 683
 684                         i2c2: i2c@021a4000 {
 685                                 #address-cells = <1>;
 686                                 #size-cells = <0>;
 687                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 688                                 reg = <0x021a4000 0x4000>;
 689                                 interrupts = <0 37 0x04>;
 690                                 clocks = <&clks 126>;
 691                                 status = "disabled";
 692                         };
 693
 694                         i2c3: i2c@021a8000 {
 695                                 #address-cells = <1>;
 696                                 #size-cells = <0>;
 697                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 698                                 reg = <0x021a8000 0x4000>;
 699                                 interrupts = <0 38 0x04>;
 700                                 clocks = <&clks 127>;
 701                                 status = "disabled";
 702                         };
 703
 704                         romcp@021ac000 {
 705                                 reg = <0x021ac000 0x4000>;
 706                         };
 707
 708                         mmdc0: mmdc@021b0000 { /* MMDC0 */
 709                                 compatible = "fsl,imx6q-mmdc";
 710                                 reg = <0x021b0000 0x4000>;
 711                         };
 712
 713                         mmdc1: mmdc@021b4000 { /* MMDC1 */
 714                                 reg = <0x021b4000 0x4000>;
 715                         };
 716
 717                         weim@021b8000 {
 718                                 reg = <0x021b8000 0x4000>;
 719                                 interrupts = <0 14 0x04>;
 720                         };
 721
 722                         ocotp@021bc000 {
 723                                 compatible = "fsl,imx6q-ocotp";
 724                                 reg = <0x021bc000 0x4000>;
 725                         };
 726
 727                         ocotp@021c0000 {
 728                                 reg = <0x021c0000 0x4000>;
 729                                 interrupts = <0 21 0x04>;
 730                         };
 731
 732                         tzasc@021d0000 { /* TZASC1 */
 733                                 reg = <0x021d0000 0x4000>;
 734                                 interrupts = <0 108 0x04>;
 735                         };
 736
 737                         tzasc@021d4000 { /* TZASC2 */
 738                                 reg = <0x021d4000 0x4000>;
 739                                 interrupts = <0 109 0x04>;
 740                         };
 741
 742                         audmux: audmux@021d8000 {
 743                                 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
 744                                 reg = <0x021d8000 0x4000>;
 745                                 status = "disabled";
 746                         };
 747
 748                         mipi@021dc000 { /* MIPI-CSI */
 749                                 reg = <0x021dc000 0x4000>;
 750                         };
 751
 752                         mipi@021e0000 { /* MIPI-DSI */
 753                                 reg = <0x021e0000 0x4000>;
 754                         };
 755
 756                         vdoa@021e4000 {
 757                                 reg = <0x021e4000 0x4000>;
 758                                 interrupts = <0 18 0x04>;
 759                         };
 760
 761                         uart2: serial@021e8000 {
 762                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 763                                 reg = <0x021e8000 0x4000>;
 764                                 interrupts = <0 27 0x04>;
 765                                 clocks = <&clks 160>, <&clks 161>;
 766                                 clock-names = "ipg", "per";
 767                                 status = "disabled";
 768                         };
 769
 770                         uart3: serial@021ec000 {
 771                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 772                                 reg = <0x021ec000 0x4000>;
 773                                 interrupts = <0 28 0x04>;
 774                                 clocks = <&clks 160>, <&clks 161>;
 775                                 clock-names = "ipg", "per";
 776                                 status = "disabled";
 777                         };
 778
 779                         uart4: serial@021f0000 {
 780                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 781                                 reg = <0x021f0000 0x4000>;
 782                                 interrupts = <0 29 0x04>;
 783                                 clocks = <&clks 160>, <&clks 161>;
 784                                 clock-names = "ipg", "per";
 785                                 status = "disabled";
 786                         };
 787
 788                         uart5: serial@021f4000 {
 789                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 790                                 reg = <0x021f4000 0x4000>;
 791                                 interrupts = <0 30 0x04>;
 792                                 clocks = <&clks 160>, <&clks 161>;
 793                                 clock-names = "ipg", "per";
 794                                 status = "disabled";
 795                         };
 796                 };
 797
 798                 ipu1: ipu@02400000 {
 799                         #crtc-cells = <1>;
 800                         compatible = "fsl,imx6q-ipu";
 801                         reg = <0x02400000 0x400000>;
 802                         interrupts = <0 6 0x4 0 5 0x4>;
 803                         clocks = <&clks 130>, <&clks 131>, <&clks 132>;
 804                         clock-names = "bus", "di0", "di1";
 805                 };
 806         };
 807 };