arch/arm/boot/dts/imx6q.dtsi

   1
   2 /*
   3  * Copyright 2013 Freescale Semiconductor, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  */
  10
  11 #include "imx6q-pinfunc.h"
  12 #include "imx6qdl.dtsi"
  13
  14 / {
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu@0 {
  20                         compatible = "arm,cortex-a9";
  21                         device_type = "cpu";
  22                         reg = <0>;
  23                         next-level-cache = <&L2>;
  24                         operating-points = <
  25                                 /* kHz    uV */
  26                                 1200000 1275000
  27                                 996000  1250000
  28                                 792000  1150000
  29                                 396000  950000
  30                         >;
  31                         clock-latency = <61036>; /* two CLK32 periods */
  32                         clocks = <&clks 104>, <&clks 6>, <&clks 16>,
  33                                  <&clks 17>, <&clks 170>;
  34                         clock-names = "arm", "pll2_pfd2_396m", "step",
  35                                       "pll1_sw", "pll1_sys";
  36                         arm-supply = <&reg_arm>;
  37                         pu-supply = <&reg_pu>;
  38                         soc-supply = <&reg_soc>;
  39                 };
  40
  41                 cpu@1 {
  42                         compatible = "arm,cortex-a9";
  43                         device_type = "cpu";
  44                         reg = <1>;
  45                         next-level-cache = <&L2>;
  46                 };
  47
  48                 cpu@2 {
  49                         compatible = "arm,cortex-a9";
  50                         device_type = "cpu";
  51                         reg = <2>;
  52                         next-level-cache = <&L2>;
  53                 };
  54
  55                 cpu@3 {
  56                         compatible = "arm,cortex-a9";
  57                         device_type = "cpu";
  58                         reg = <3>;
  59                         next-level-cache = <&L2>;
  60                 };
  61         };
  62
  63         soc {
  64                 aips-bus@02000000 { /* AIPS1 */
  65                         spba-bus@02000000 {
  66                                 ecspi5: ecspi@02018000 {
  67                                         #address-cells = <1>;
  68                                         #size-cells = <0>;
  69                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
  70                                         reg = <0x02018000 0x4000>;
  71                                         interrupts = <0 35 0x04>;
  72                                         clocks = <&clks 116>, <&clks 116>;
  73                                         clock-names = "ipg", "per";
  74                                         status = "disabled";
  75                                 };
  76                         };
  77
  78                         iomuxc: iomuxc@020e0000 {
  79                                 compatible = "fsl,imx6q-iomuxc";
  80
  81                                 ipu2 {
  82                                         pinctrl_ipu2_1: ipu2grp-1 {
  83                                                 fsl,pins = <
  84                                                         MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x10
  85                                                         MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15       0x10
  86                                                         MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02        0x10
  87                                                         MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03        0x10
  88                                                         MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04        0x80000000
  89                                                         MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00   0x10
  90                                                         MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01   0x10
  91                                                         MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02   0x10
  92                                                         MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03   0x10
  93                                                         MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04   0x10
  94                                                         MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05   0x10
  95                                                         MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06   0x10
  96                                                         MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07   0x10
  97                                                         MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08   0x10
  98                                                         MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09   0x10
  99                                                         MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10  0x10
 100                                                         MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11  0x10
 101                                                         MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12  0x10
 102                                                         MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13  0x10
 103                                                         MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14  0x10
 104                                                         MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15  0x10
 105                                                         MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16  0x10
 106                                                         MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17  0x10
 107                                                         MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18  0x10
 108                                                         MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19  0x10
 109                                                         MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20  0x10
 110                                                         MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21  0x10
 111                                                         MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22  0x10
 112                                                         MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23  0x10
 113                                                 >;
 114                                         };
 115                                 };
 116                         };
 117                 };
 118
 119                 ipu2: ipu@02800000 {
 120                         #crtc-cells = <1>;
 121                         compatible = "fsl,imx6q-ipu";
 122                         reg = <0x02800000 0x400000>;
 123                         interrupts = <0 8 0x4 0 7 0x4>;
 124                         clocks = <&clks 133>, <&clks 134>, <&clks 137>;
 125                         clock-names = "bus", "di0", "di1";
 126                         resets = <&src 4>;
 127                 };
 128         };
 129 };
 130
 131 &ldb {
 132         clocks = <&clks 33>, <&clks 34>,
 133                  <&clks 39>, <&clks 40>, <&clks 41>, <&clks 42>,
 134                  <&clks 135>, <&clks 136>;
 135         clock-names = "di0_pll", "di1_pll",
 136                       "di0_sel", "di1_sel", "di2_sel", "di3_sel",
 137                       "di0", "di1";
 138
 139         lvds-channel@0 {
 140                 crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
 141         };
 142
 143         lvds-channel@1 {
 144                 crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
 145         };
 146 };