arch/arm/boot/dts/imx51.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include "skeleton.dtsi"
  14 #include "imx51-pinfunc.h"
  15
  16 / {
  17         aliases {
  18                 serial0 = &uart1;
  19                 serial1 = &uart2;
  20                 serial2 = &uart3;
  21                 gpio0 = &gpio1;
  22                 gpio1 = &gpio2;
  23                 gpio2 = &gpio3;
  24                 gpio3 = &gpio4;
  25         };
  26
  27         tzic: tz-interrupt-controller@e0000000 {
  28                 compatible = "fsl,imx51-tzic", "fsl,tzic";
  29                 interrupt-controller;
  30                 #interrupt-cells = <1>;
  31                 reg = <0xe0000000 0x4000>;
  32         };
  33
  34         clocks {
  35                 #address-cells = <1>;
  36                 #size-cells = <0>;
  37
  38                 ckil {
  39                         compatible = "fsl,imx-ckil", "fixed-clock";
  40                         clock-frequency = <32768>;
  41                 };
  42
  43                 ckih1 {
  44                         compatible = "fsl,imx-ckih1", "fixed-clock";
  45                         clock-frequency = <22579200>;
  46                 };
  47
  48                 ckih2 {
  49                         compatible = "fsl,imx-ckih2", "fixed-clock";
  50                         clock-frequency = <0>;
  51                 };
  52
  53                 osc {
  54                         compatible = "fsl,imx-osc", "fixed-clock";
  55                         clock-frequency = <24000000>;
  56                 };
  57         };
  58
  59         soc {
  60                 #address-cells = <1>;
  61                 #size-cells = <1>;
  62                 compatible = "simple-bus";
  63                 interrupt-parent = <&tzic>;
  64                 ranges;
  65
  66                 ipu: ipu@40000000 {
  67                         #crtc-cells = <1>;
  68                         compatible = "fsl,imx51-ipu";
  69                         reg = <0x40000000 0x20000000>;
  70                         interrupts = <11 10>;
  71                         clocks = <&clks 59>, <&clks 110>, <&clks 61>;
  72                         clock-names = "bus", "di0", "di1";
  73                         resets = <&src 2>;
  74                 };
  75
  76                 aips@70000000 { /* AIPS1 */
  77                         compatible = "fsl,aips-bus", "simple-bus";
  78                         #address-cells = <1>;
  79                         #size-cells = <1>;
  80                         reg = <0x70000000 0x10000000>;
  81                         ranges;
  82
  83                         spba@70000000 {
  84                                 compatible = "fsl,spba-bus", "simple-bus";
  85                                 #address-cells = <1>;
  86                                 #size-cells = <1>;
  87                                 reg = <0x70000000 0x40000>;
  88                                 ranges;
  89
  90                                 esdhc1: esdhc@70004000 {
  91                                         compatible = "fsl,imx51-esdhc";
  92                                         reg = <0x70004000 0x4000>;
  93                                         interrupts = <1>;
  94                                         clocks = <&clks 44>, <&clks 0>, <&clks 71>;
  95                                         clock-names = "ipg", "ahb", "per";
  96                                         status = "disabled";
  97                                 };
  98
  99                                 esdhc2: esdhc@70008000 {
 100                                         compatible = "fsl,imx51-esdhc";
 101                                         reg = <0x70008000 0x4000>;
 102                                         interrupts = <2>;
 103                                         clocks = <&clks 45>, <&clks 0>, <&clks 72>;
 104                                         clock-names = "ipg", "ahb", "per";
 105                                         bus-width = <4>;
 106                                         status = "disabled";
 107                                 };
 108
 109                                 uart3: serial@7000c000 {
 110                                         compatible = "fsl,imx51-uart", "fsl,imx21-uart";
 111                                         reg = <0x7000c000 0x4000>;
 112                                         interrupts = <33>;
 113                                         clocks = <&clks 32>, <&clks 33>;
 114                                         clock-names = "ipg", "per";
 115                                         status = "disabled";
 116                                 };
 117
 118                                 ecspi1: ecspi@70010000 {
 119                                         #address-cells = <1>;
 120                                         #size-cells = <0>;
 121                                         compatible = "fsl,imx51-ecspi";
 122                                         reg = <0x70010000 0x4000>;
 123                                         interrupts = <36>;
 124                                         clocks = <&clks 51>, <&clks 52>;
 125                                         clock-names = "ipg", "per";
 126                                         status = "disabled";
 127                                 };
 128
 129                                 ssi2: ssi@70014000 {
 130                                         compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
 131                                         reg = <0x70014000 0x4000>;
 132                                         interrupts = <30>;
 133                                         clocks = <&clks 49>;
 134                                         fsl,fifo-depth = <15>;
 135                                         fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
 136                                         status = "disabled";
 137                                 };
 138
 139                                 esdhc3: esdhc@70020000 {
 140                                         compatible = "fsl,imx51-esdhc";
 141                                         reg = <0x70020000 0x4000>;
 142                                         interrupts = <3>;
 143                                         clocks = <&clks 46>, <&clks 0>, <&clks 73>;
 144                                         clock-names = "ipg", "ahb", "per";
 145                                         bus-width = <4>;
 146                                         status = "disabled";
 147                                 };
 148
 149                                 esdhc4: esdhc@70024000 {
 150                                         compatible = "fsl,imx51-esdhc";
 151                                         reg = <0x70024000 0x4000>;
 152                                         interrupts = <4>;
 153                                         clocks = <&clks 47>, <&clks 0>, <&clks 74>;
 154                                         clock-names = "ipg", "ahb", "per";
 155                                         bus-width = <4>;
 156                                         status = "disabled";
 157                                 };
 158                         };
 159
 160                         usbotg: usb@73f80000 {
 161                                 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
 162                                 reg = <0x73f80000 0x0200>;
 163                                 interrupts = <18>;
 164                                 status = "disabled";
 165                         };
 166
 167                         usbh1: usb@73f80200 {
 168                                 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
 169                                 reg = <0x73f80200 0x0200>;
 170                                 interrupts = <14>;
 171                                 status = "disabled";
 172                         };
 173
 174                         usbh2: usb@73f80400 {
 175                                 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
 176                                 reg = <0x73f80400 0x0200>;
 177                                 interrupts = <16>;
 178                                 status = "disabled";
 179                         };
 180
 181                         usbh3: usb@73f80600 {
 182                                 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
 183                                 reg = <0x73f80600 0x0200>;
 184                                 interrupts = <17>;
 185                                 status = "disabled";
 186                         };
 187
 188                         gpio1: gpio@73f84000 {
 189                                 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
 190                                 reg = <0x73f84000 0x4000>;
 191                                 interrupts = <50 51>;
 192                                 gpio-controller;
 193                                 #gpio-cells = <2>;
 194                                 interrupt-controller;
 195                                 #interrupt-cells = <2>;
 196                         };
 197
 198                         gpio2: gpio@73f88000 {
 199                                 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
 200                                 reg = <0x73f88000 0x4000>;
 201                                 interrupts = <52 53>;
 202                                 gpio-controller;
 203                                 #gpio-cells = <2>;
 204                                 interrupt-controller;
 205                                 #interrupt-cells = <2>;
 206                         };
 207
 208                         gpio3: gpio@73f8c000 {
 209                                 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
 210                                 reg = <0x73f8c000 0x4000>;
 211                                 interrupts = <54 55>;
 212                                 gpio-controller;
 213                                 #gpio-cells = <2>;
 214                                 interrupt-controller;
 215                                 #interrupt-cells = <2>;
 216                         };
 217
 218                         gpio4: gpio@73f90000 {
 219                                 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
 220                                 reg = <0x73f90000 0x4000>;
 221                                 interrupts = <56 57>;
 222                                 gpio-controller;
 223                                 #gpio-cells = <2>;
 224                                 interrupt-controller;
 225                                 #interrupt-cells = <2>;
 226                         };
 227
 228                         kpp: kpp@73f94000 {
 229                                 compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
 230                                 reg = <0x73f94000 0x4000>;
 231                                 interrupts = <60>;
 232                                 clocks = <&clks 0>;
 233                                 status = "disabled";
 234                         };
 235
 236                         wdog1: wdog@73f98000 {
 237                                 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
 238                                 reg = <0x73f98000 0x4000>;
 239                                 interrupts = <58>;
 240                                 clocks = <&clks 0>;
 241                         };
 242
 243                         wdog2: wdog@73f9c000 {
 244                                 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
 245                                 reg = <0x73f9c000 0x4000>;
 246                                 interrupts = <59>;
 247                                 clocks = <&clks 0>;
 248                                 status = "disabled";
 249                         };
 250
 251                         gpt: timer@73fa0000 {
 252                                 compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
 253                                 reg = <0x73fa0000 0x4000>;
 254                                 interrupts = <39>;
 255                                 clocks = <&clks 36>, <&clks 41>;
 256                                 clock-names = "ipg", "per";
 257                         };
 258
 259                         iomuxc: iomuxc@73fa8000 {
 260                                 compatible = "fsl,imx51-iomuxc";
 261                                 reg = <0x73fa8000 0x4000>;
 262
 263                                 audmux {
 264                                         pinctrl_audmux_1: audmuxgrp-1 {
 265                                                 fsl,pins = <
 266                                                         MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
 267                                                         MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
 268                                                         MX51_PAD_AUD3_BB_CK__AUD3_TXC  0x80000000
 269                                                         MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
 270                                                 >;
 271                                         };
 272                                 };
 273
 274                                 fec {
 275                                         pinctrl_fec_1: fecgrp-1 {
 276                                                 fsl,pins = <
 277                                                         MX51_PAD_EIM_EB2__FEC_MDIO         0x80000000
 278                                                         MX51_PAD_EIM_EB3__FEC_RDATA1       0x80000000
 279                                                         MX51_PAD_EIM_CS2__FEC_RDATA2       0x80000000
 280                                                         MX51_PAD_EIM_CS3__FEC_RDATA3       0x80000000
 281                                                         MX51_PAD_EIM_CS4__FEC_RX_ER        0x80000000
 282                                                         MX51_PAD_EIM_CS5__FEC_CRS          0x80000000
 283                                                         MX51_PAD_NANDF_RB2__FEC_COL        0x80000000
 284                                                         MX51_PAD_NANDF_RB3__FEC_RX_CLK     0x80000000
 285                                                         MX51_PAD_NANDF_D9__FEC_RDATA0      0x80000000
 286                                                         MX51_PAD_NANDF_D8__FEC_TDATA0      0x80000000
 287                                                         MX51_PAD_NANDF_CS2__FEC_TX_ER      0x80000000
 288                                                         MX51_PAD_NANDF_CS3__FEC_MDC        0x80000000
 289                                                         MX51_PAD_NANDF_CS4__FEC_TDATA1     0x80000000
 290                                                         MX51_PAD_NANDF_CS5__FEC_TDATA2     0x80000000
 291                                                         MX51_PAD_NANDF_CS6__FEC_TDATA3     0x80000000
 292                                                         MX51_PAD_NANDF_CS7__FEC_TX_EN      0x80000000
 293                                                         MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
 294                                                 >;
 295                                         };
 296
 297                                         pinctrl_fec_2: fecgrp-2 {
 298                                                 fsl,pins = <
 299                                                         MX51_PAD_DI_GP3__FEC_TX_ER        0x80000000
 300                                                         MX51_PAD_DI2_PIN4__FEC_CRS        0x80000000
 301                                                         MX51_PAD_DI2_PIN2__FEC_MDC        0x80000000
 302                                                         MX51_PAD_DI2_PIN3__FEC_MDIO       0x80000000
 303                                                         MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
 304                                                         MX51_PAD_DI_GP4__FEC_RDATA2       0x80000000
 305                                                         MX51_PAD_DISP2_DAT0__FEC_RDATA3   0x80000000
 306                                                         MX51_PAD_DISP2_DAT1__FEC_RX_ER    0x80000000
 307                                                         MX51_PAD_DISP2_DAT6__FEC_TDATA1   0x80000000
 308                                                         MX51_PAD_DISP2_DAT7__FEC_TDATA2   0x80000000
 309                                                         MX51_PAD_DISP2_DAT8__FEC_TDATA3   0x80000000
 310                                                         MX51_PAD_DISP2_DAT9__FEC_TX_EN    0x80000000
 311                                                         MX51_PAD_DISP2_DAT10__FEC_COL     0x80000000
 312                                                         MX51_PAD_DISP2_DAT11__FEC_RX_CLK  0x80000000
 313                                                         MX51_PAD_DISP2_DAT12__FEC_RX_DV   0x80000000
 314                                                         MX51_PAD_DISP2_DAT13__FEC_TX_CLK  0x80000000
 315                                                         MX51_PAD_DISP2_DAT14__FEC_RDATA0  0x80000000
 316                                                         MX51_PAD_DISP2_DAT15__FEC_TDATA0  0x80000000
 317                                                 >;
 318                                         };
 319                                 };
 320
 321                                 ecspi1 {
 322                                         pinctrl_ecspi1_1: ecspi1grp-1 {
 323                                                 fsl,pins = <
 324                                                         MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
 325                                                         MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
 326                                                         MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
 327                                                 >;
 328                                         };
 329                                 };
 330
 331                                 ecspi2 {
 332                                         pinctrl_ecspi2_1: ecspi2grp-1 {
 333                                                 fsl,pins = <
 334                                                         MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185
 335                                                         MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185
 336                                                         MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
 337                                                 >;
 338                                         };
 339                                 };
 340
 341                                 esdhc1 {
 342                                         pinctrl_esdhc1_1: esdhc1grp-1 {
 343                                                 fsl,pins = <
 344                                                         MX51_PAD_SD1_CMD__SD1_CMD     0x400020d5
 345                                                         MX51_PAD_SD1_CLK__SD1_CLK     0x20d5
 346                                                         MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
 347                                                         MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
 348                                                         MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
 349                                                         MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
 350                                                 >;
 351                                         };
 352                                 };
 353
 354                                 esdhc2 {
 355                                         pinctrl_esdhc2_1: esdhc2grp-1 {
 356                                                 fsl,pins = <
 357                                                         MX51_PAD_SD2_CMD__SD2_CMD     0x400020d5
 358                                                         MX51_PAD_SD2_CLK__SD2_CLK     0x20d5
 359                                                         MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
 360                                                         MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
 361                                                         MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
 362                                                         MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
 363                                                 >;
 364                                         };
 365                                 };
 366
 367                                 i2c2 {
 368                                         pinctrl_i2c2_1: i2c2grp-1 {
 369                                                 fsl,pins = <
 370                                                         MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
 371                                                         MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
 372                                                 >;
 373                                         };
 374
 375                                         pinctrl_i2c2_2: i2c2grp-2 {
 376                                                 fsl,pins = <
 377                                                         MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed
 378                                                         MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed
 379                                                 >;
 380                                         };
 381                                 };
 382
 383                                 ipu_disp1 {
 384                                         pinctrl_ipu_disp1_1: ipudisp1grp-1 {
 385                                                 fsl,pins = <
 386                                                         MX51_PAD_DISP1_DAT0__DISP1_DAT0   0x5
 387                                                         MX51_PAD_DISP1_DAT1__DISP1_DAT1   0x5
 388                                                         MX51_PAD_DISP1_DAT2__DISP1_DAT2   0x5
 389                                                         MX51_PAD_DISP1_DAT3__DISP1_DAT3   0x5
 390                                                         MX51_PAD_DISP1_DAT4__DISP1_DAT4   0x5
 391                                                         MX51_PAD_DISP1_DAT5__DISP1_DAT5   0x5
 392                                                         MX51_PAD_DISP1_DAT6__DISP1_DAT6   0x5
 393                                                         MX51_PAD_DISP1_DAT7__DISP1_DAT7   0x5
 394                                                         MX51_PAD_DISP1_DAT8__DISP1_DAT8   0x5
 395                                                         MX51_PAD_DISP1_DAT9__DISP1_DAT9   0x5
 396                                                         MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
 397                                                         MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
 398                                                         MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
 399                                                         MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
 400                                                         MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
 401                                                         MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
 402                                                         MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
 403                                                         MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
 404                                                         MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
 405                                                         MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
 406                                                         MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
 407                                                         MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
 408                                                         MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
 409                                                         MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
 410                                                         MX51_PAD_DI1_PIN2__DI1_PIN2       0x5 /* hsync */
 411                                                         MX51_PAD_DI1_PIN3__DI1_PIN3       0x5 /* vsync */
 412                                                 >;
 413                                         };
 414                                 };
 415
 416                                 ipu_disp2 {
 417                                         pinctrl_ipu_disp2_1: ipudisp2grp-1 {
 418                                                 fsl,pins = <
 419                                                         MX51_PAD_DISP2_DAT0__DISP2_DAT0     0x5
 420                                                         MX51_PAD_DISP2_DAT1__DISP2_DAT1     0x5
 421                                                         MX51_PAD_DISP2_DAT2__DISP2_DAT2     0x5
 422                                                         MX51_PAD_DISP2_DAT3__DISP2_DAT3     0x5
 423                                                         MX51_PAD_DISP2_DAT4__DISP2_DAT4     0x5
 424                                                         MX51_PAD_DISP2_DAT5__DISP2_DAT5     0x5
 425                                                         MX51_PAD_DISP2_DAT6__DISP2_DAT6     0x5
 426                                                         MX51_PAD_DISP2_DAT7__DISP2_DAT7     0x5
 427                                                         MX51_PAD_DISP2_DAT8__DISP2_DAT8     0x5
 428                                                         MX51_PAD_DISP2_DAT9__DISP2_DAT9     0x5
 429                                                         MX51_PAD_DISP2_DAT10__DISP2_DAT10   0x5
 430                                                         MX51_PAD_DISP2_DAT11__DISP2_DAT11   0x5
 431                                                         MX51_PAD_DISP2_DAT12__DISP2_DAT12   0x5
 432                                                         MX51_PAD_DISP2_DAT13__DISP2_DAT13   0x5
 433                                                         MX51_PAD_DISP2_DAT14__DISP2_DAT14   0x5
 434                                                         MX51_PAD_DISP2_DAT15__DISP2_DAT15   0x5
 435                                                         MX51_PAD_DI2_PIN2__DI2_PIN2         0x5 /* hsync */
 436                                                         MX51_PAD_DI2_PIN3__DI2_PIN3         0x5 /* vsync */
 437                                                         MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
 438                                                         MX51_PAD_DI_GP4__DI2_PIN15          0x5
 439                                                 >;
 440                                         };
 441                                 };
 442
 443                                 pata {
 444                                         pinctrl_pata_1: patagrp-1 {
 445                                                 fsl,pins = <
 446                                                         MX51_PAD_NANDF_WE_B__PATA_DIOW          0x2004
 447                                                         MX51_PAD_NANDF_RE_B__PATA_DIOR          0x2004
 448                                                         MX51_PAD_NANDF_ALE__PATA_BUFFER_EN      0x2004
 449                                                         MX51_PAD_NANDF_CLE__PATA_RESET_B        0x2004
 450                                                         MX51_PAD_NANDF_WP_B__PATA_DMACK         0x2004
 451                                                         MX51_PAD_NANDF_RB0__PATA_DMARQ          0x2004
 452                                                         MX51_PAD_NANDF_RB1__PATA_IORDY          0x2004
 453                                                         MX51_PAD_GPIO_NAND__PATA_INTRQ          0x2004
 454                                                         MX51_PAD_NANDF_CS2__PATA_CS_0           0x2004
 455                                                         MX51_PAD_NANDF_CS3__PATA_CS_1           0x2004
 456                                                         MX51_PAD_NANDF_CS4__PATA_DA_0           0x2004
 457                                                         MX51_PAD_NANDF_CS5__PATA_DA_1           0x2004
 458                                                         MX51_PAD_NANDF_CS6__PATA_DA_2           0x2004
 459                                                         MX51_PAD_NANDF_D15__PATA_DATA15         0x2004
 460                                                         MX51_PAD_NANDF_D14__PATA_DATA14         0x2004
 461                                                         MX51_PAD_NANDF_D13__PATA_DATA13         0x2004
 462                                                         MX51_PAD_NANDF_D12__PATA_DATA12         0x2004
 463                                                         MX51_PAD_NANDF_D11__PATA_DATA11         0x2004
 464                                                         MX51_PAD_NANDF_D10__PATA_DATA10         0x2004
 465                                                         MX51_PAD_NANDF_D9__PATA_DATA9           0x2004
 466                                                         MX51_PAD_NANDF_D8__PATA_DATA8           0x2004
 467                                                         MX51_PAD_NANDF_D7__PATA_DATA7           0x2004
 468                                                         MX51_PAD_NANDF_D6__PATA_DATA6           0x2004
 469                                                         MX51_PAD_NANDF_D5__PATA_DATA5           0x2004
 470                                                         MX51_PAD_NANDF_D4__PATA_DATA4           0x2004
 471                                                         MX51_PAD_NANDF_D3__PATA_DATA3           0x2004
 472                                                         MX51_PAD_NANDF_D2__PATA_DATA2           0x2004
 473                                                         MX51_PAD_NANDF_D1__PATA_DATA1           0x2004
 474                                                         MX51_PAD_NANDF_D0__PATA_DATA0           0x2004
 475                                                 >;
 476                                         };
 477                                 };
 478
 479                                 uart1 {
 480                                         pinctrl_uart1_1: uart1grp-1 {
 481                                                 fsl,pins = <
 482                                                         MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
 483                                                         MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
 484                                                         MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
 485                                                         MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
 486                                                 >;
 487                                         };
 488                                 };
 489
 490                                 uart2 {
 491                                         pinctrl_uart2_1: uart2grp-1 {
 492                                                 fsl,pins = <
 493                                                         MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
 494                                                         MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
 495                                                 >;
 496                                         };
 497                                 };
 498
 499                                 uart3 {
 500                                         pinctrl_uart3_1: uart3grp-1 {
 501                                                 fsl,pins = <
 502                                                         MX51_PAD_EIM_D25__UART3_RXD 0x1c5
 503                                                         MX51_PAD_EIM_D26__UART3_TXD 0x1c5
 504                                                         MX51_PAD_EIM_D27__UART3_RTS 0x1c5
 505                                                         MX51_PAD_EIM_D24__UART3_CTS 0x1c5
 506                                                 >;
 507                                         };
 508
 509                                         pinctrl_uart3_2: uart3grp-2 {
 510                                                 fsl,pins = <
 511                                                         MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
 512                                                         MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
 513                                                 >;
 514                                         };
 515                                 };
 516
 517                                 kpp {
 518                                         pinctrl_kpp_1: kppgrp-1 {
 519                                                 fsl,pins = <
 520                                                         MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
 521                                                         MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
 522                                                         MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
 523                                                         MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
 524                                                         MX51_PAD_KEY_COL0__KEY_COL0 0xe8
 525                                                         MX51_PAD_KEY_COL1__KEY_COL1 0xe8
 526                                                         MX51_PAD_KEY_COL2__KEY_COL2 0xe8
 527                                                         MX51_PAD_KEY_COL3__KEY_COL3 0xe8
 528                                                 >;
 529                                         };
 530                                 };
 531                         };
 532
 533                         pwm1: pwm@73fb4000 {
 534                                 #pwm-cells = <2>;
 535                                 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
 536                                 reg = <0x73fb4000 0x4000>;
 537                                 clocks = <&clks 37>, <&clks 38>;
 538                                 clock-names = "ipg", "per";
 539                                 interrupts = <61>;
 540                         };
 541
 542                         pwm2: pwm@73fb8000 {
 543                                 #pwm-cells = <2>;
 544                                 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
 545                                 reg = <0x73fb8000 0x4000>;
 546                                 clocks = <&clks 39>, <&clks 40>;
 547                                 clock-names = "ipg", "per";
 548                                 interrupts = <94>;
 549                         };
 550
 551                         uart1: serial@73fbc000 {
 552                                 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
 553                                 reg = <0x73fbc000 0x4000>;
 554                                 interrupts = <31>;
 555                                 clocks = <&clks 28>, <&clks 29>;
 556                                 clock-names = "ipg", "per";
 557                                 status = "disabled";
 558                         };
 559
 560                         uart2: serial@73fc0000 {
 561                                 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
 562                                 reg = <0x73fc0000 0x4000>;
 563                                 interrupts = <32>;
 564                                 clocks = <&clks 30>, <&clks 31>;
 565                                 clock-names = "ipg", "per";
 566                                 status = "disabled";
 567                         };
 568
 569                         src: src@73fd0000 {
 570                                 compatible = "fsl,imx51-src";
 571                                 reg = <0x73fd0000 0x4000>;
 572                                 #reset-cells = <1>;
 573                         };
 574
 575                         clks: ccm@73fd4000{
 576                                 compatible = "fsl,imx51-ccm";
 577                                 reg = <0x73fd4000 0x4000>;
 578                                 interrupts = <0 71 0x04 0 72 0x04>;
 579                                 #clock-cells = <1>;
 580                         };
 581                 };
 582
 583                 aips@80000000 { /* AIPS2 */
 584                         compatible = "fsl,aips-bus", "simple-bus";
 585                         #address-cells = <1>;
 586                         #size-cells = <1>;
 587                         reg = <0x80000000 0x10000000>;
 588                         ranges;
 589
 590                         ecspi2: ecspi@83fac000 {
 591                                 #address-cells = <1>;
 592                                 #size-cells = <0>;
 593                                 compatible = "fsl,imx51-ecspi";
 594                                 reg = <0x83fac000 0x4000>;
 595                                 interrupts = <37>;
 596                                 clocks = <&clks 53>, <&clks 54>;
 597                                 clock-names = "ipg", "per";
 598                                 status = "disabled";
 599                         };
 600
 601                         sdma: sdma@83fb0000 {
 602                                 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
 603                                 reg = <0x83fb0000 0x4000>;
 604                                 interrupts = <6>;
 605                                 clocks = <&clks 56>, <&clks 56>;
 606                                 clock-names = "ipg", "ahb";
 607                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
 608                         };
 609
 610                         cspi: cspi@83fc0000 {
 611                                 #address-cells = <1>;
 612                                 #size-cells = <0>;
 613                                 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
 614                                 reg = <0x83fc0000 0x4000>;
 615                                 interrupts = <38>;
 616                                 clocks = <&clks 55>, <&clks 0>;
 617                                 clock-names = "ipg", "per";
 618                                 status = "disabled";
 619                         };
 620
 621                         i2c2: i2c@83fc4000 {
 622                                 #address-cells = <1>;
 623                                 #size-cells = <0>;
 624                                 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
 625                                 reg = <0x83fc4000 0x4000>;
 626                                 interrupts = <63>;
 627                                 clocks = <&clks 35>;
 628                                 status = "disabled";
 629                         };
 630
 631                         i2c1: i2c@83fc8000 {
 632                                 #address-cells = <1>;
 633                                 #size-cells = <0>;
 634                                 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
 635                                 reg = <0x83fc8000 0x4000>;
 636                                 interrupts = <62>;
 637                                 clocks = <&clks 34>;
 638                                 status = "disabled";
 639                         };
 640
 641                         ssi1: ssi@83fcc000 {
 642                                 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
 643                                 reg = <0x83fcc000 0x4000>;
 644                                 interrupts = <29>;
 645                                 clocks = <&clks 48>;
 646                                 fsl,fifo-depth = <15>;
 647                                 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
 648                                 status = "disabled";
 649                         };
 650
 651                         audmux: audmux@83fd0000 {
 652                                 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
 653                                 reg = <0x83fd0000 0x4000>;
 654                                 status = "disabled";
 655                         };
 656
 657                         nfc: nand@83fdb000 {
 658                                 compatible = "fsl,imx51-nand";
 659                                 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
 660                                 interrupts = <8>;
 661                                 clocks = <&clks 60>;
 662                                 status = "disabled";
 663                         };
 664
 665                         pata: pata@83fe0000 {
 666                                 compatible = "fsl,imx51-pata", "fsl,imx27-pata";
 667                                 reg = <0x83fe0000 0x4000>;
 668                                 interrupts = <70>;
 669                                 clocks = <&clks 161>;
 670                                 status = "disabled";
 671                         };
 672
 673                         ssi3: ssi@83fe8000 {
 674                                 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
 675                                 reg = <0x83fe8000 0x4000>;
 676                                 interrupts = <96>;
 677                                 clocks = <&clks 50>;
 678                                 fsl,fifo-depth = <15>;
 679                                 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
 680                                 status = "disabled";
 681                         };
 682
 683                         fec: ethernet@83fec000 {
 684                                 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
 685                                 reg = <0x83fec000 0x4000>;
 686                                 interrupts = <87>;
 687                                 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
 688                                 clock-names = "ipg", "ahb", "ptp";
 689                                 status = "disabled";
 690                         };
 691                 };
 692         };
 693 };