arch/arm/boot/dts/exynos3250.dtsi

   1 /*
   2  * Samsung's Exynos3250 SoC device tree source
   3  *
   4  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
   8  * based board files can include this file and provide values for board specfic
   9  * bindings.
  10  *
  11  * Note: This file does not include device nodes for all the controllers in
  12  * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
  13  * nodes can be added to this file.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  */
  19
  20 #include "skeleton.dtsi"
  21 #include <dt-bindings/clock/exynos3250.h>
  22
  23 / {
  24         compatible = "samsung,exynos3250";
  25         interrupt-parent = <&gic>;
  26
  27         aliases {
  28                 pinctrl0 = &pinctrl_0;
  29                 pinctrl1 = &pinctrl_1;
  30                 mshc0 = &mshc_0;
  31                 mshc1 = &mshc_1;
  32                 spi0 = &spi_0;
  33                 spi1 = &spi_1;
  34                 i2c0 = &i2c_0;
  35                 i2c1 = &i2c_1;
  36                 i2c2 = &i2c_2;
  37                 i2c3 = &i2c_3;
  38                 i2c4 = &i2c_4;
  39                 i2c5 = &i2c_5;
  40                 i2c6 = &i2c_6;
  41                 i2c7 = &i2c_7;
  42                 serial0 = &serial_0;
  43                 serial1 = &serial_1;
  44         };
  45
  46         cpus {
  47                 #address-cells = <1>;
  48                 #size-cells = <0>;
  49
  50                 cpu0: cpu@0 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a7";
  53                         reg = <0>;
  54                         clock-frequency = <1000000000>;
  55                 };
  56
  57                 cpu1: cpu@1 {
  58                         device_type = "cpu";
  59                         compatible = "arm,cortex-a7";
  60                         reg = <1>;
  61                         clock-frequency = <1000000000>;
  62                 };
  63         };
  64
  65         soc: soc {
  66                 compatible = "simple-bus";
  67                 #address-cells = <1>;
  68                 #size-cells = <1>;
  69                 ranges;
  70
  71                 fixed-rate-clocks {
  72                         #address-cells = <1>;
  73                         #size-cells = <0>;
  74
  75                         xusbxti: clock@0 {
  76                                 compatible = "fixed-clock";
  77                                 #address-cells = <1>;
  78                                 #size-cells = <0>;
  79                                 reg = <0>;
  80                                 clock-frequency = <0>;
  81                                 #clock-cells = <0>;
  82                                 clock-output-names = "xusbxti";
  83                         };
  84
  85                         xxti: clock@1 {
  86                                 compatible = "fixed-clock";
  87                                 reg = <1>;
  88                                 clock-frequency = <0>;
  89                                 #clock-cells = <0>;
  90                                 clock-output-names = "xxti";
  91                         };
  92
  93                         xtcxo: clock@2 {
  94                                 compatible = "fixed-clock";
  95                                 reg = <2>;
  96                                 clock-frequency = <0>;
  97                                 #clock-cells = <0>;
  98                                 clock-output-names = "xtcxo";
  99                         };
 100                 };
 101
 102                 sysram@02020000 {
 103                         compatible = "mmio-sram";
 104                         reg = <0x02020000 0x40000>;
 105                         #address-cells = <1>;
 106                         #size-cells = <1>;
 107                         ranges = <0 0x02020000 0x40000>;
 108
 109                         smp-sysram@0 {
 110                                 compatible = "samsung,exynos4210-sysram";
 111                                 reg = <0x0 0x1000>;
 112                         };
 113
 114                         smp-sysram@3f000 {
 115                                 compatible = "samsung,exynos4210-sysram-ns";
 116                                 reg = <0x3f000 0x1000>;
 117                         };
 118                 };
 119
 120                 chipid@10000000 {
 121                         compatible = "samsung,exynos4210-chipid";
 122                         reg = <0x10000000 0x100>;
 123                 };
 124
 125                 sys_reg: syscon@10010000 {
 126                         compatible = "samsung,exynos3-sysreg", "syscon";
 127                         reg = <0x10010000 0x400>;
 128                 };
 129
 130                 pmu_system_controller: system-controller@10020000 {
 131                         compatible = "samsung,exynos3250-pmu", "syscon";
 132                         reg = <0x10020000 0x4000>;
 133                 };
 134
 135                 mipi_phy: video-phy@10020710 {
 136                         compatible = "samsung,s5pv210-mipi-video-phy";
 137                         reg = <0x10020710 8>;
 138                         #phy-cells = <1>;
 139                 };
 140
 141                 pd_cam: cam-power-domain@10023C00 {
 142                         compatible = "samsung,exynos4210-pd";
 143                         reg = <0x10023C00 0x20>;
 144                 };
 145
 146                 pd_mfc: mfc-power-domain@10023C40 {
 147                         compatible = "samsung,exynos4210-pd";
 148                         reg = <0x10023C40 0x20>;
 149                 };
 150
 151                 pd_g3d: g3d-power-domain@10023C60 {
 152                         compatible = "samsung,exynos4210-pd";
 153                         reg = <0x10023C60 0x20>;
 154                 };
 155
 156                 pd_lcd0: lcd0-power-domain@10023C80 {
 157                         compatible = "samsung,exynos4210-pd";
 158                         reg = <0x10023C80 0x20>;
 159                 };
 160
 161                 pd_isp: isp-power-domain@10023CA0 {
 162                         compatible = "samsung,exynos4210-pd";
 163                         reg = <0x10023CA0 0x20>;
 164                 };
 165
 166                 cmu: clock-controller@10030000 {
 167                         compatible = "samsung,exynos3250-cmu";
 168                         reg = <0x10030000 0x20000>;
 169                         #clock-cells = <1>;
 170                 };
 171
 172                 rtc: rtc@10070000 {
 173                         compatible = "samsung,exynos3250-rtc";
 174                         reg = <0x10070000 0x100>;
 175                         interrupts = <0 73 0>, <0 74 0>;
 176                         status = "disabled";
 177                 };
 178
 179                 tmu: tmu@100C0000 {
 180                         compatible = "samsung,exynos3250-tmu";
 181                         reg = <0x100C0000 0x100>;
 182                         interrupts = <0 216 0>;
 183                         clocks = <&cmu CLK_TMU_APBIF>;
 184                         clock-names = "tmu_apbif";
 185                         status = "disabled";
 186                 };
 187
 188                 gic: interrupt-controller@10481000 {
 189                         compatible = "arm,cortex-a15-gic";
 190                         #interrupt-cells = <3>;
 191                         interrupt-controller;
 192                         reg = <0x10481000 0x1000>,
 193                               <0x10482000 0x1000>,
 194                               <0x10484000 0x2000>,
 195                               <0x10486000 0x2000>;
 196                         interrupts = <1 9 0xf04>;
 197                 };
 198
 199                 mct@10050000 {
 200                         compatible = "samsung,exynos4210-mct";
 201                         reg = <0x10050000 0x800>;
 202                         interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
 203                                      <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
 204                         clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
 205                         clock-names = "fin_pll", "mct";
 206                 };
 207
 208                 pinctrl_1: pinctrl@11000000 {
 209                         compatible = "samsung,exynos3250-pinctrl";
 210                         reg = <0x11000000 0x1000>;
 211                         interrupts = <0 225 0>;
 212
 213                         wakeup-interrupt-controller {
 214                                 compatible = "samsung,exynos4210-wakeup-eint";
 215                                 interrupts = <0 48 0>;
 216                         };
 217                 };
 218
 219                 pinctrl_0: pinctrl@11400000 {
 220                         compatible = "samsung,exynos3250-pinctrl";
 221                         reg = <0x11400000 0x1000>;
 222                         interrupts = <0 240 0>;
 223                 };
 224
 225                 fimd: fimd@11c00000 {
 226                         compatible = "samsung,exynos3250-fimd";
 227                         reg = <0x11c00000 0x30000>;
 228                         interrupt-names = "fifo", "vsync", "lcd_sys";
 229                         interrupts = <0 84 0>, <0 85 0>, <0 86 0>;
 230                         clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
 231                         clock-names = "sclk_fimd", "fimd";
 232                         samsung,power-domain = <&pd_lcd0>;
 233                         samsung,sysreg = <&sys_reg>;
 234                         status = "disabled";
 235                 };
 236
 237                 dsi_0: dsi@11C80000 {
 238                         compatible = "samsung,exynos3250-mipi-dsi";
 239                         reg = <0x11C80000 0x10000>;
 240                         interrupts = <0 83 0>;
 241                         samsung,phy-type = <0>;
 242                         samsung,power-domain = <&pd_lcd0>;
 243                         phys = <&mipi_phy 1>;
 244                         phy-names = "dsim";
 245                         clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
 246                         clock-names = "bus_clk", "pll_clk";
 247                         #address-cells = <1>;
 248                         #size-cells = <0>;
 249                         status = "disabled";
 250                 };
 251
 252                 mshc_0: mshc@12510000 {
 253                         compatible = "samsung,exynos5250-dw-mshc";
 254                         reg = <0x12510000 0x1000>;
 255                         interrupts = <0 142 0>;
 256                         clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
 257                         clock-names = "biu", "ciu";
 258                         fifo-depth = <0x80>;
 259                         #address-cells = <1>;
 260                         #size-cells = <0>;
 261                         status = "disabled";
 262                 };
 263
 264                 mshc_1: mshc@12520000 {
 265                         compatible = "samsung,exynos5250-dw-mshc";
 266                         reg = <0x12520000 0x1000>;
 267                         interrupts = <0 143 0>;
 268                         clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
 269                         clock-names = "biu", "ciu";
 270                         fifo-depth = <0x80>;
 271                         #address-cells = <1>;
 272                         #size-cells = <0>;
 273                         status = "disabled";
 274                 };
 275
 276                 amba {
 277                         compatible = "arm,amba-bus";
 278                         #address-cells = <1>;
 279                         #size-cells = <1>;
 280                         ranges;
 281
 282                         pdma0: pdma@12680000 {
 283                                 compatible = "arm,pl330", "arm,primecell";
 284                                 reg = <0x12680000 0x1000>;
 285                                 interrupts = <0 138 0>;
 286                                 clocks = <&cmu CLK_PDMA0>;
 287                                 clock-names = "apb_pclk";
 288                                 #dma-cells = <1>;
 289                                 #dma-channels = <8>;
 290                                 #dma-requests = <32>;
 291                         };
 292
 293                         pdma1: pdma@12690000 {
 294                                 compatible = "arm,pl330", "arm,primecell";
 295                                 reg = <0x12690000 0x1000>;
 296                                 interrupts = <0 139 0>;
 297                                 clocks = <&cmu CLK_PDMA1>;
 298                                 clock-names = "apb_pclk";
 299                                 #dma-cells = <1>;
 300                                 #dma-channels = <8>;
 301                                 #dma-requests = <32>;
 302                         };
 303                 };
 304
 305                 adc: adc@126C0000 {
 306                         compatible = "samsung,exynos3250-adc",
 307                                      "samsung,exynos-adc-v2";
 308                         reg = <0x126C0000 0x100>, <0x10020718 0x4>;
 309                         interrupts = <0 137 0>;
 310                         clock-names = "adc", "sclk";
 311                         clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
 312                         #io-channel-cells = <1>;
 313                         io-channel-ranges;
 314                         status = "disabled";
 315                 };
 316
 317                 serial_0: serial@13800000 {
 318                         compatible = "samsung,exynos4210-uart";
 319                         reg = <0x13800000 0x100>;
 320                         interrupts = <0 109 0>;
 321                         clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
 322                         clock-names = "uart", "clk_uart_baud0";
 323                         pinctrl-names = "default";
 324                         pinctrl-0 = <&uart0_data &uart0_fctl>;
 325                         status = "disabled";
 326                 };
 327
 328                 serial_1: serial@13810000 {
 329                         compatible = "samsung,exynos4210-uart";
 330                         reg = <0x13810000 0x100>;
 331                         interrupts = <0 110 0>;
 332                         clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
 333                         clock-names = "uart", "clk_uart_baud0";
 334                         pinctrl-names = "default";
 335                         pinctrl-0 = <&uart1_data>;
 336                         status = "disabled";
 337                 };
 338
 339                 i2c_0: i2c@13860000 {
 340                         #address-cells = <1>;
 341                         #size-cells = <0>;
 342                         compatible = "samsung,s3c2440-i2c";
 343                         reg = <0x13860000 0x100>;
 344                         interrupts = <0 113 0>;
 345                         clocks = <&cmu CLK_I2C0>;
 346                         clock-names = "i2c";
 347                         pinctrl-names = "default";
 348                         pinctrl-0 = <&i2c0_bus>;
 349                         status = "disabled";
 350                 };
 351
 352                 i2c_1: i2c@13870000 {
 353                         #address-cells = <1>;
 354                         #size-cells = <0>;
 355                         compatible = "samsung,s3c2440-i2c";
 356                         reg = <0x13870000 0x100>;
 357                         interrupts = <0 114 0>;
 358                         clocks = <&cmu CLK_I2C1>;
 359                         clock-names = "i2c";
 360                         pinctrl-names = "default";
 361                         pinctrl-0 = <&i2c1_bus>;
 362                         status = "disabled";
 363                 };
 364
 365                 i2c_2: i2c@13880000 {
 366                         #address-cells = <1>;
 367                         #size-cells = <0>;
 368                         compatible = "samsung,s3c2440-i2c";
 369                         reg = <0x13880000 0x100>;
 370                         interrupts = <0 115 0>;
 371                         clocks = <&cmu CLK_I2C2>;
 372                         clock-names = "i2c";
 373                         pinctrl-names = "default";
 374                         pinctrl-0 = <&i2c2_bus>;
 375                         status = "disabled";
 376                 };
 377
 378                 i2c_3: i2c@13890000 {
 379                         #address-cells = <1>;
 380                         #size-cells = <0>;
 381                         compatible = "samsung,s3c2440-i2c";
 382                         reg = <0x13890000 0x100>;
 383                         interrupts = <0 116 0>;
 384                         clocks = <&cmu CLK_I2C3>;
 385                         clock-names = "i2c";
 386                         pinctrl-names = "default";
 387                         pinctrl-0 = <&i2c3_bus>;
 388                         status = "disabled";
 389                 };
 390
 391                 i2c_4: i2c@138A0000 {
 392                         #address-cells = <1>;
 393                         #size-cells = <0>;
 394                         compatible = "samsung,s3c2440-i2c";
 395                         reg = <0x138A0000 0x100>;
 396                         interrupts = <0 117 0>;
 397                         clocks = <&cmu CLK_I2C4>;
 398                         clock-names = "i2c";
 399                         pinctrl-names = "default";
 400                         pinctrl-0 = <&i2c4_bus>;
 401                         status = "disabled";
 402                 };
 403
 404                 i2c_5: i2c@138B0000 {
 405                         #address-cells = <1>;
 406                         #size-cells = <0>;
 407                         compatible = "samsung,s3c2440-i2c";
 408                         reg = <0x138B0000 0x100>;
 409                         interrupts = <0 118 0>;
 410                         clocks = <&cmu CLK_I2C5>;
 411                         clock-names = "i2c";
 412                         pinctrl-names = "default";
 413                         pinctrl-0 = <&i2c5_bus>;
 414                         status = "disabled";
 415                 };
 416
 417                 i2c_6: i2c@138C0000 {
 418                         #address-cells = <1>;
 419                         #size-cells = <0>;
 420                         compatible = "samsung,s3c2440-i2c";
 421                         reg = <0x138C0000 0x100>;
 422                         interrupts = <0 119 0>;
 423                         clocks = <&cmu CLK_I2C6>;
 424                         clock-names = "i2c";
 425                         pinctrl-names = "default";
 426                         pinctrl-0 = <&i2c6_bus>;
 427                         status = "disabled";
 428                 };
 429
 430                 i2c_7: i2c@138D0000 {
 431                         #address-cells = <1>;
 432                         #size-cells = <0>;
 433                         compatible = "samsung,s3c2440-i2c";
 434                         reg = <0x138D0000 0x100>;
 435                         interrupts = <0 120 0>;
 436                         clocks = <&cmu CLK_I2C7>;
 437                         clock-names = "i2c";
 438                         pinctrl-names = "default";
 439                         pinctrl-0 = <&i2c7_bus>;
 440                         status = "disabled";
 441                 };
 442
 443                 spi_0: spi@13920000 {
 444                         compatible = "samsung,exynos4210-spi";
 445                         reg = <0x13920000 0x100>;
 446                         interrupts = <0 121 0>;
 447                         dmas = <&pdma0 7>, <&pdma0 6>;
 448                         dma-names = "tx", "rx";
 449                         #address-cells = <1>;
 450                         #size-cells = <0>;
 451                         clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
 452                         clock-names = "spi", "spi_busclk0";
 453                         samsung,spi-src-clk = <0>;
 454                         pinctrl-names = "default";
 455                         pinctrl-0 = <&spi0_bus>;
 456                         status = "disabled";
 457                 };
 458
 459                 spi_1: spi@13930000 {
 460                         compatible = "samsung,exynos4210-spi";
 461                         reg = <0x13930000 0x100>;
 462                         interrupts = <0 122 0>;
 463                         dmas = <&pdma1 7>, <&pdma1 6>;
 464                         dma-names = "tx", "rx";
 465                         #address-cells = <1>;
 466                         #size-cells = <0>;
 467                         clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
 468                         clock-names = "spi", "spi_busclk0";
 469                         samsung,spi-src-clk = <0>;
 470                         pinctrl-names = "default";
 471                         pinctrl-0 = <&spi1_bus>;
 472                         status = "disabled";
 473                 };
 474
 475                 i2s2: i2s@13970000 {
 476                         compatible = "samsung,s3c6410-i2s";
 477                         reg = <0x13970000 0x100>;
 478                         interrupts = <0 126 0>;
 479                         clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
 480                         clock-names = "iis", "i2s_opclk0";
 481                         dmas = <&pdma0 14>, <&pdma0 13>;
 482                         dma-names = "tx", "rx";
 483                         pinctrl-0 = <&i2s2_bus>;
 484                         pinctrl-names = "default";
 485                         status = "disabled";
 486                 };
 487
 488                 pwm: pwm@139D0000 {
 489                         compatible = "samsung,exynos4210-pwm";
 490                         reg = <0x139D0000 0x1000>;
 491                         interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
 492                                      <0 107 0>, <0 108 0>;
 493                         #pwm-cells = <3>;
 494                         status = "disabled";
 495                 };
 496
 497                 pmu {
 498                         compatible = "arm,cortex-a7-pmu";
 499                         interrupts = <0 18 0>, <0 19 0>;
 500                 };
 501         };
 502 };
 503
 504 #include "exynos3250-pinctrl.dtsi"