ARM: dts: OMAP2: fix interrupt number for rng
[pandora-kernel.git] / arch / arm / boot / dts / dra7.dtsi
1 /*
2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  * Based on "omap4.dtsi"
8  */
9
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/dra.h>
12
13 #include "skeleton.dtsi"
14
15 / {
16         #address-cells = <1>;
17         #size-cells = <1>;
18
19         compatible = "ti,dra7xx";
20         interrupt-parent = <&gic>;
21
22         aliases {
23                 i2c0 = &i2c1;
24                 i2c1 = &i2c2;
25                 i2c2 = &i2c3;
26                 i2c3 = &i2c4;
27                 i2c4 = &i2c5;
28                 serial0 = &uart1;
29                 serial1 = &uart2;
30                 serial2 = &uart3;
31                 serial3 = &uart4;
32                 serial4 = &uart5;
33                 serial5 = &uart6;
34         };
35
36         cpus {
37                 #address-cells = <1>;
38                 #size-cells = <0>;
39
40                 cpu0: cpu@0 {
41                         device_type = "cpu";
42                         compatible = "arm,cortex-a15";
43                         reg = <0>;
44
45                         operating-points = <
46                                 /* kHz    uV */
47                                 1000000 1060000
48                                 1176000 1160000
49                                 >;
50                 };
51                 cpu@1 {
52                         device_type = "cpu";
53                         compatible = "arm,cortex-a15";
54                         reg = <1>;
55                 };
56         };
57
58         timer {
59                 compatible = "arm,armv7-timer";
60                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
61                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
62                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
63                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
64         };
65
66         gic: interrupt-controller@48211000 {
67                 compatible = "arm,cortex-a15-gic";
68                 interrupt-controller;
69                 #interrupt-cells = <3>;
70                 reg = <0x48211000 0x1000>,
71                       <0x48212000 0x1000>,
72                       <0x48214000 0x2000>,
73                       <0x48216000 0x2000>;
74                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
75         };
76
77         /*
78          * The soc node represents the soc top level view. It is uses for IPs
79          * that are not memory mapped in the MPU view or for the MPU itself.
80          */
81         soc {
82                 compatible = "ti,omap-infra";
83                 mpu {
84                         compatible = "ti,omap5-mpu";
85                         ti,hwmods = "mpu";
86                 };
87         };
88
89         /*
90          * XXX: Use a flat representation of the SOC interconnect.
91          * The real OMAP interconnect network is quite complex.
92          * Since that will not bring real advantage to represent that in DT for
93          * the moment, just use a fake OCP bus entry to represent the whole bus
94          * hierarchy.
95          */
96         ocp {
97                 compatible = "ti,omap4-l3-noc", "simple-bus";
98                 #address-cells = <1>;
99                 #size-cells = <1>;
100                 ranges;
101                 ti,hwmods = "l3_main_1", "l3_main_2";
102                 reg = <0x44000000 0x2000>,
103                       <0x44800000 0x3000>;
104                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
105                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
106
107                 counter32k: counter@4ae04000 {
108                         compatible = "ti,omap-counter32k";
109                         reg = <0x4ae04000 0x40>;
110                         ti,hwmods = "counter_32k";
111                 };
112
113                 dra7_pmx_core: pinmux@4a003400 {
114                         compatible = "pinctrl-single";
115                         reg = <0x4a003400 0x0464>;
116                         #address-cells = <1>;
117                         #size-cells = <0>;
118                         pinctrl-single,register-width = <32>;
119                         pinctrl-single,function-mask = <0x3fffffff>;
120                 };
121
122                 sdma: dma-controller@4a056000 {
123                         compatible = "ti,omap4430-sdma";
124                         reg = <0x4a056000 0x1000>;
125                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
126                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
127                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
128                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
129                         #dma-cells = <1>;
130                         #dma-channels = <32>;
131                         #dma-requests = <127>;
132                 };
133
134                 gpio1: gpio@4ae10000 {
135                         compatible = "ti,omap4-gpio";
136                         reg = <0x4ae10000 0x200>;
137                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
138                         ti,hwmods = "gpio1";
139                         gpio-controller;
140                         #gpio-cells = <2>;
141                         interrupt-controller;
142                         #interrupt-cells = <1>;
143                 };
144
145                 gpio2: gpio@48055000 {
146                         compatible = "ti,omap4-gpio";
147                         reg = <0x48055000 0x200>;
148                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
149                         ti,hwmods = "gpio2";
150                         gpio-controller;
151                         #gpio-cells = <2>;
152                         interrupt-controller;
153                         #interrupt-cells = <1>;
154                 };
155
156                 gpio3: gpio@48057000 {
157                         compatible = "ti,omap4-gpio";
158                         reg = <0x48057000 0x200>;
159                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
160                         ti,hwmods = "gpio3";
161                         gpio-controller;
162                         #gpio-cells = <2>;
163                         interrupt-controller;
164                         #interrupt-cells = <1>;
165                 };
166
167                 gpio4: gpio@48059000 {
168                         compatible = "ti,omap4-gpio";
169                         reg = <0x48059000 0x200>;
170                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
171                         ti,hwmods = "gpio4";
172                         gpio-controller;
173                         #gpio-cells = <2>;
174                         interrupt-controller;
175                         #interrupt-cells = <1>;
176                 };
177
178                 gpio5: gpio@4805b000 {
179                         compatible = "ti,omap4-gpio";
180                         reg = <0x4805b000 0x200>;
181                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
182                         ti,hwmods = "gpio5";
183                         gpio-controller;
184                         #gpio-cells = <2>;
185                         interrupt-controller;
186                         #interrupt-cells = <1>;
187                 };
188
189                 gpio6: gpio@4805d000 {
190                         compatible = "ti,omap4-gpio";
191                         reg = <0x4805d000 0x200>;
192                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
193                         ti,hwmods = "gpio6";
194                         gpio-controller;
195                         #gpio-cells = <2>;
196                         interrupt-controller;
197                         #interrupt-cells = <1>;
198                 };
199
200                 gpio7: gpio@48051000 {
201                         compatible = "ti,omap4-gpio";
202                         reg = <0x48051000 0x200>;
203                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
204                         ti,hwmods = "gpio7";
205                         gpio-controller;
206                         #gpio-cells = <2>;
207                         interrupt-controller;
208                         #interrupt-cells = <1>;
209                 };
210
211                 gpio8: gpio@48053000 {
212                         compatible = "ti,omap4-gpio";
213                         reg = <0x48053000 0x200>;
214                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
215                         ti,hwmods = "gpio8";
216                         gpio-controller;
217                         #gpio-cells = <2>;
218                         interrupt-controller;
219                         #interrupt-cells = <1>;
220                 };
221
222                 uart1: serial@4806a000 {
223                         compatible = "ti,omap4-uart";
224                         reg = <0x4806a000 0x100>;
225                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
226                         ti,hwmods = "uart1";
227                         clock-frequency = <48000000>;
228                         status = "disabled";
229                 };
230
231                 uart2: serial@4806c000 {
232                         compatible = "ti,omap4-uart";
233                         reg = <0x4806c000 0x100>;
234                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
235                         ti,hwmods = "uart2";
236                         clock-frequency = <48000000>;
237                         status = "disabled";
238                 };
239
240                 uart3: serial@48020000 {
241                         compatible = "ti,omap4-uart";
242                         reg = <0x48020000 0x100>;
243                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
244                         ti,hwmods = "uart3";
245                         clock-frequency = <48000000>;
246                         status = "disabled";
247                 };
248
249                 uart4: serial@4806e000 {
250                         compatible = "ti,omap4-uart";
251                         reg = <0x4806e000 0x100>;
252                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
253                         ti,hwmods = "uart4";
254                         clock-frequency = <48000000>;
255                         status = "disabled";
256                 };
257
258                 uart5: serial@48066000 {
259                         compatible = "ti,omap4-uart";
260                         reg = <0x48066000 0x100>;
261                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
262                         ti,hwmods = "uart5";
263                         clock-frequency = <48000000>;
264                         status = "disabled";
265                 };
266
267                 uart6: serial@48068000 {
268                         compatible = "ti,omap4-uart";
269                         reg = <0x48068000 0x100>;
270                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
271                         ti,hwmods = "uart6";
272                         clock-frequency = <48000000>;
273                         status = "disabled";
274                 };
275
276                 uart7: serial@48420000 {
277                         compatible = "ti,omap4-uart";
278                         reg = <0x48420000 0x100>;
279                         ti,hwmods = "uart7";
280                         clock-frequency = <48000000>;
281                         status = "disabled";
282                 };
283
284                 uart8: serial@48422000 {
285                         compatible = "ti,omap4-uart";
286                         reg = <0x48422000 0x100>;
287                         ti,hwmods = "uart8";
288                         clock-frequency = <48000000>;
289                         status = "disabled";
290                 };
291
292                 uart9: serial@48424000 {
293                         compatible = "ti,omap4-uart";
294                         reg = <0x48424000 0x100>;
295                         ti,hwmods = "uart9";
296                         clock-frequency = <48000000>;
297                         status = "disabled";
298                 };
299
300                 uart10: serial@4ae2b000 {
301                         compatible = "ti,omap4-uart";
302                         reg = <0x4ae2b000 0x100>;
303                         ti,hwmods = "uart10";
304                         clock-frequency = <48000000>;
305                         status = "disabled";
306                 };
307
308                 timer1: timer@4ae18000 {
309                         compatible = "ti,omap5430-timer";
310                         reg = <0x4ae18000 0x80>;
311                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
312                         ti,hwmods = "timer1";
313                         ti,timer-alwon;
314                 };
315
316                 timer2: timer@48032000 {
317                         compatible = "ti,omap5430-timer";
318                         reg = <0x48032000 0x80>;
319                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
320                         ti,hwmods = "timer2";
321                 };
322
323                 timer3: timer@48034000 {
324                         compatible = "ti,omap5430-timer";
325                         reg = <0x48034000 0x80>;
326                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
327                         ti,hwmods = "timer3";
328                 };
329
330                 timer4: timer@48036000 {
331                         compatible = "ti,omap5430-timer";
332                         reg = <0x48036000 0x80>;
333                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
334                         ti,hwmods = "timer4";
335                 };
336
337                 timer5: timer@48820000 {
338                         compatible = "ti,omap5430-timer";
339                         reg = <0x48820000 0x80>;
340                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
341                         ti,hwmods = "timer5";
342                         ti,timer-dsp;
343                 };
344
345                 timer6: timer@48822000 {
346                         compatible = "ti,omap5430-timer";
347                         reg = <0x48822000 0x80>;
348                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
349                         ti,hwmods = "timer6";
350                         ti,timer-dsp;
351                         ti,timer-pwm;
352                 };
353
354                 timer7: timer@48824000 {
355                         compatible = "ti,omap5430-timer";
356                         reg = <0x48824000 0x80>;
357                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
358                         ti,hwmods = "timer7";
359                         ti,timer-dsp;
360                 };
361
362                 timer8: timer@48826000 {
363                         compatible = "ti,omap5430-timer";
364                         reg = <0x48826000 0x80>;
365                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
366                         ti,hwmods = "timer8";
367                         ti,timer-dsp;
368                         ti,timer-pwm;
369                 };
370
371                 timer9: timer@4803e000 {
372                         compatible = "ti,omap5430-timer";
373                         reg = <0x4803e000 0x80>;
374                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
375                         ti,hwmods = "timer9";
376                 };
377
378                 timer10: timer@48086000 {
379                         compatible = "ti,omap5430-timer";
380                         reg = <0x48086000 0x80>;
381                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
382                         ti,hwmods = "timer10";
383                 };
384
385                 timer11: timer@48088000 {
386                         compatible = "ti,omap5430-timer";
387                         reg = <0x48088000 0x80>;
388                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
389                         ti,hwmods = "timer11";
390                         ti,timer-pwm;
391                 };
392
393                 timer13: timer@48828000 {
394                         compatible = "ti,omap5430-timer";
395                         reg = <0x48828000 0x80>;
396                         ti,hwmods = "timer13";
397                         status = "disabled";
398                 };
399
400                 timer14: timer@4882a000 {
401                         compatible = "ti,omap5430-timer";
402                         reg = <0x4882a000 0x80>;
403                         ti,hwmods = "timer14";
404                         status = "disabled";
405                 };
406
407                 timer15: timer@4882c000 {
408                         compatible = "ti,omap5430-timer";
409                         reg = <0x4882c000 0x80>;
410                         ti,hwmods = "timer15";
411                         status = "disabled";
412                 };
413
414                 timer16: timer@4882e000 {
415                         compatible = "ti,omap5430-timer";
416                         reg = <0x4882e000 0x80>;
417                         ti,hwmods = "timer16";
418                         status = "disabled";
419                 };
420
421                 wdt2: wdt@4ae14000 {
422                         compatible = "ti,omap4-wdt";
423                         reg = <0x4ae14000 0x80>;
424                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
425                         ti,hwmods = "wd_timer2";
426                 };
427
428                 i2c1: i2c@48070000 {
429                         compatible = "ti,omap4-i2c";
430                         reg = <0x48070000 0x100>;
431                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
432                         #address-cells = <1>;
433                         #size-cells = <0>;
434                         ti,hwmods = "i2c1";
435                         status = "disabled";
436                 };
437
438                 i2c2: i2c@48072000 {
439                         compatible = "ti,omap4-i2c";
440                         reg = <0x48072000 0x100>;
441                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
442                         #address-cells = <1>;
443                         #size-cells = <0>;
444                         ti,hwmods = "i2c2";
445                         status = "disabled";
446                 };
447
448                 i2c3: i2c@48060000 {
449                         compatible = "ti,omap4-i2c";
450                         reg = <0x48060000 0x100>;
451                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
452                         #address-cells = <1>;
453                         #size-cells = <0>;
454                         ti,hwmods = "i2c3";
455                         status = "disabled";
456                 };
457
458                 i2c4: i2c@4807a000 {
459                         compatible = "ti,omap4-i2c";
460                         reg = <0x4807a000 0x100>;
461                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
462                         #address-cells = <1>;
463                         #size-cells = <0>;
464                         ti,hwmods = "i2c4";
465                         status = "disabled";
466                 };
467
468                 i2c5: i2c@4807c000 {
469                         compatible = "ti,omap4-i2c";
470                         reg = <0x4807c000 0x100>;
471                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
472                         #address-cells = <1>;
473                         #size-cells = <0>;
474                         ti,hwmods = "i2c5";
475                         status = "disabled";
476                 };
477
478                 mmc1: mmc@4809c000 {
479                         compatible = "ti,omap4-hsmmc";
480                         reg = <0x4809c000 0x400>;
481                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
482                         ti,hwmods = "mmc1";
483                         ti,dual-volt;
484                         ti,needs-special-reset;
485                         dmas = <&sdma 61>, <&sdma 62>;
486                         dma-names = "tx", "rx";
487                         status = "disabled";
488                 };
489
490                 mmc2: mmc@480b4000 {
491                         compatible = "ti,omap4-hsmmc";
492                         reg = <0x480b4000 0x400>;
493                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
494                         ti,hwmods = "mmc2";
495                         ti,needs-special-reset;
496                         dmas = <&sdma 47>, <&sdma 48>;
497                         dma-names = "tx", "rx";
498                         status = "disabled";
499                 };
500
501                 mmc3: mmc@480ad000 {
502                         compatible = "ti,omap4-hsmmc";
503                         reg = <0x480ad000 0x400>;
504                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
505                         ti,hwmods = "mmc3";
506                         ti,needs-special-reset;
507                         dmas = <&sdma 77>, <&sdma 78>;
508                         dma-names = "tx", "rx";
509                         status = "disabled";
510                 };
511
512                 mmc4: mmc@480d1000 {
513                         compatible = "ti,omap4-hsmmc";
514                         reg = <0x480d1000 0x400>;
515                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
516                         ti,hwmods = "mmc4";
517                         ti,needs-special-reset;
518                         dmas = <&sdma 57>, <&sdma 58>;
519                         dma-names = "tx", "rx";
520                         status = "disabled";
521                 };
522
523                 mcspi1: spi@48098000 {
524                         compatible = "ti,omap4-mcspi";
525                         reg = <0x48098000 0x200>;
526                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
527                         #address-cells = <1>;
528                         #size-cells = <0>;
529                         ti,hwmods = "mcspi1";
530                         ti,spi-num-cs = <4>;
531                         dmas = <&sdma 35>,
532                                <&sdma 36>,
533                                <&sdma 37>,
534                                <&sdma 38>,
535                                <&sdma 39>,
536                                <&sdma 40>,
537                                <&sdma 41>,
538                                <&sdma 42>;
539                         dma-names = "tx0", "rx0", "tx1", "rx1",
540                                     "tx2", "rx2", "tx3", "rx3";
541                         status = "disabled";
542                 };
543
544                 mcspi2: spi@4809a000 {
545                         compatible = "ti,omap4-mcspi";
546                         reg = <0x4809a000 0x200>;
547                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
548                         #address-cells = <1>;
549                         #size-cells = <0>;
550                         ti,hwmods = "mcspi2";
551                         ti,spi-num-cs = <2>;
552                         dmas = <&sdma 43>,
553                                <&sdma 44>,
554                                <&sdma 45>,
555                                <&sdma 46>;
556                         dma-names = "tx0", "rx0", "tx1", "rx1";
557                         status = "disabled";
558                 };
559
560                 mcspi3: spi@480b8000 {
561                         compatible = "ti,omap4-mcspi";
562                         reg = <0x480b8000 0x200>;
563                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
564                         #address-cells = <1>;
565                         #size-cells = <0>;
566                         ti,hwmods = "mcspi3";
567                         ti,spi-num-cs = <2>;
568                         dmas = <&sdma 15>, <&sdma 16>;
569                         dma-names = "tx0", "rx0";
570                         status = "disabled";
571                 };
572
573                 mcspi4: spi@480ba000 {
574                         compatible = "ti,omap4-mcspi";
575                         reg = <0x480ba000 0x200>;
576                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
577                         #address-cells = <1>;
578                         #size-cells = <0>;
579                         ti,hwmods = "mcspi4";
580                         ti,spi-num-cs = <1>;
581                         dmas = <&sdma 70>, <&sdma 71>;
582                         dma-names = "tx0", "rx0";
583                         status = "disabled";
584                 };
585         };
586 };