2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/dra.h>
13 #include "skeleton.dtsi"
19 compatible = "ti,dra7xx";
20 interrupt-parent = <&gic>;
42 compatible = "arm,cortex-a15";
53 compatible = "arm,cortex-a15";
59 compatible = "arm,armv7-timer";
60 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
61 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
62 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
63 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
66 gic: interrupt-controller@48211000 {
67 compatible = "arm,cortex-a15-gic";
69 #interrupt-cells = <3>;
70 reg = <0x48211000 0x1000>,
74 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
78 * The soc node represents the soc top level view. It is uses for IPs
79 * that are not memory mapped in the MPU view or for the MPU itself.
82 compatible = "ti,omap-infra";
84 compatible = "ti,omap5-mpu";
90 * XXX: Use a flat representation of the SOC interconnect.
91 * The real OMAP interconnect network is quite complex.
92 * Since that will not bring real advantage to represent that in DT for
93 * the moment, just use a fake OCP bus entry to represent the whole bus
97 compatible = "ti,omap4-l3-noc", "simple-bus";
101 ti,hwmods = "l3_main_1", "l3_main_2";
102 reg = <0x44000000 0x2000>,
104 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
107 counter32k: counter@4ae04000 {
108 compatible = "ti,omap-counter32k";
109 reg = <0x4ae04000 0x40>;
110 ti,hwmods = "counter_32k";
113 dra7_pmx_core: pinmux@4a003400 {
114 compatible = "pinctrl-single";
115 reg = <0x4a003400 0x0464>;
116 #address-cells = <1>;
118 pinctrl-single,register-width = <32>;
119 pinctrl-single,function-mask = <0x3fffffff>;
122 sdma: dma-controller@4a056000 {
123 compatible = "ti,omap4430-sdma";
124 reg = <0x4a056000 0x1000>;
125 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
126 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
127 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
128 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
130 #dma-channels = <32>;
131 #dma-requests = <127>;
134 gpio1: gpio@4ae10000 {
135 compatible = "ti,omap4-gpio";
136 reg = <0x4ae10000 0x200>;
137 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
141 interrupt-controller;
142 #interrupt-cells = <1>;
145 gpio2: gpio@48055000 {
146 compatible = "ti,omap4-gpio";
147 reg = <0x48055000 0x200>;
148 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
152 interrupt-controller;
153 #interrupt-cells = <1>;
156 gpio3: gpio@48057000 {
157 compatible = "ti,omap4-gpio";
158 reg = <0x48057000 0x200>;
159 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
163 interrupt-controller;
164 #interrupt-cells = <1>;
167 gpio4: gpio@48059000 {
168 compatible = "ti,omap4-gpio";
169 reg = <0x48059000 0x200>;
170 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
174 interrupt-controller;
175 #interrupt-cells = <1>;
178 gpio5: gpio@4805b000 {
179 compatible = "ti,omap4-gpio";
180 reg = <0x4805b000 0x200>;
181 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
185 interrupt-controller;
186 #interrupt-cells = <1>;
189 gpio6: gpio@4805d000 {
190 compatible = "ti,omap4-gpio";
191 reg = <0x4805d000 0x200>;
192 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
196 interrupt-controller;
197 #interrupt-cells = <1>;
200 gpio7: gpio@48051000 {
201 compatible = "ti,omap4-gpio";
202 reg = <0x48051000 0x200>;
203 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
207 interrupt-controller;
208 #interrupt-cells = <1>;
211 gpio8: gpio@48053000 {
212 compatible = "ti,omap4-gpio";
213 reg = <0x48053000 0x200>;
214 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
218 interrupt-controller;
219 #interrupt-cells = <1>;
222 uart1: serial@4806a000 {
223 compatible = "ti,omap4-uart";
224 reg = <0x4806a000 0x100>;
225 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
227 clock-frequency = <48000000>;
231 uart2: serial@4806c000 {
232 compatible = "ti,omap4-uart";
233 reg = <0x4806c000 0x100>;
234 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
236 clock-frequency = <48000000>;
240 uart3: serial@48020000 {
241 compatible = "ti,omap4-uart";
242 reg = <0x48020000 0x100>;
243 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
245 clock-frequency = <48000000>;
249 uart4: serial@4806e000 {
250 compatible = "ti,omap4-uart";
251 reg = <0x4806e000 0x100>;
252 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
254 clock-frequency = <48000000>;
258 uart5: serial@48066000 {
259 compatible = "ti,omap4-uart";
260 reg = <0x48066000 0x100>;
261 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
263 clock-frequency = <48000000>;
267 uart6: serial@48068000 {
268 compatible = "ti,omap4-uart";
269 reg = <0x48068000 0x100>;
270 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
272 clock-frequency = <48000000>;
276 uart7: serial@48420000 {
277 compatible = "ti,omap4-uart";
278 reg = <0x48420000 0x100>;
280 clock-frequency = <48000000>;
284 uart8: serial@48422000 {
285 compatible = "ti,omap4-uart";
286 reg = <0x48422000 0x100>;
288 clock-frequency = <48000000>;
292 uart9: serial@48424000 {
293 compatible = "ti,omap4-uart";
294 reg = <0x48424000 0x100>;
296 clock-frequency = <48000000>;
300 uart10: serial@4ae2b000 {
301 compatible = "ti,omap4-uart";
302 reg = <0x4ae2b000 0x100>;
303 ti,hwmods = "uart10";
304 clock-frequency = <48000000>;
308 timer1: timer@4ae18000 {
309 compatible = "ti,omap5430-timer";
310 reg = <0x4ae18000 0x80>;
311 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
312 ti,hwmods = "timer1";
316 timer2: timer@48032000 {
317 compatible = "ti,omap5430-timer";
318 reg = <0x48032000 0x80>;
319 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
320 ti,hwmods = "timer2";
323 timer3: timer@48034000 {
324 compatible = "ti,omap5430-timer";
325 reg = <0x48034000 0x80>;
326 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
327 ti,hwmods = "timer3";
330 timer4: timer@48036000 {
331 compatible = "ti,omap5430-timer";
332 reg = <0x48036000 0x80>;
333 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
334 ti,hwmods = "timer4";
337 timer5: timer@48820000 {
338 compatible = "ti,omap5430-timer";
339 reg = <0x48820000 0x80>;
340 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
341 ti,hwmods = "timer5";
345 timer6: timer@48822000 {
346 compatible = "ti,omap5430-timer";
347 reg = <0x48822000 0x80>;
348 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
349 ti,hwmods = "timer6";
354 timer7: timer@48824000 {
355 compatible = "ti,omap5430-timer";
356 reg = <0x48824000 0x80>;
357 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
358 ti,hwmods = "timer7";
362 timer8: timer@48826000 {
363 compatible = "ti,omap5430-timer";
364 reg = <0x48826000 0x80>;
365 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
366 ti,hwmods = "timer8";
371 timer9: timer@4803e000 {
372 compatible = "ti,omap5430-timer";
373 reg = <0x4803e000 0x80>;
374 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
375 ti,hwmods = "timer9";
378 timer10: timer@48086000 {
379 compatible = "ti,omap5430-timer";
380 reg = <0x48086000 0x80>;
381 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
382 ti,hwmods = "timer10";
385 timer11: timer@48088000 {
386 compatible = "ti,omap5430-timer";
387 reg = <0x48088000 0x80>;
388 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
389 ti,hwmods = "timer11";
393 timer13: timer@48828000 {
394 compatible = "ti,omap5430-timer";
395 reg = <0x48828000 0x80>;
396 ti,hwmods = "timer13";
400 timer14: timer@4882a000 {
401 compatible = "ti,omap5430-timer";
402 reg = <0x4882a000 0x80>;
403 ti,hwmods = "timer14";
407 timer15: timer@4882c000 {
408 compatible = "ti,omap5430-timer";
409 reg = <0x4882c000 0x80>;
410 ti,hwmods = "timer15";
414 timer16: timer@4882e000 {
415 compatible = "ti,omap5430-timer";
416 reg = <0x4882e000 0x80>;
417 ti,hwmods = "timer16";
422 compatible = "ti,omap4-wdt";
423 reg = <0x4ae14000 0x80>;
424 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
425 ti,hwmods = "wd_timer2";
429 compatible = "ti,omap4-i2c";
430 reg = <0x48070000 0x100>;
431 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
432 #address-cells = <1>;
439 compatible = "ti,omap4-i2c";
440 reg = <0x48072000 0x100>;
441 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
442 #address-cells = <1>;
449 compatible = "ti,omap4-i2c";
450 reg = <0x48060000 0x100>;
451 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
452 #address-cells = <1>;
459 compatible = "ti,omap4-i2c";
460 reg = <0x4807a000 0x100>;
461 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
462 #address-cells = <1>;
469 compatible = "ti,omap4-i2c";
470 reg = <0x4807c000 0x100>;
471 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
472 #address-cells = <1>;
479 compatible = "ti,omap4-hsmmc";
480 reg = <0x4809c000 0x400>;
481 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
484 ti,needs-special-reset;
485 dmas = <&sdma 61>, <&sdma 62>;
486 dma-names = "tx", "rx";
491 compatible = "ti,omap4-hsmmc";
492 reg = <0x480b4000 0x400>;
493 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
495 ti,needs-special-reset;
496 dmas = <&sdma 47>, <&sdma 48>;
497 dma-names = "tx", "rx";
502 compatible = "ti,omap4-hsmmc";
503 reg = <0x480ad000 0x400>;
504 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
506 ti,needs-special-reset;
507 dmas = <&sdma 77>, <&sdma 78>;
508 dma-names = "tx", "rx";
513 compatible = "ti,omap4-hsmmc";
514 reg = <0x480d1000 0x400>;
515 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
517 ti,needs-special-reset;
518 dmas = <&sdma 57>, <&sdma 58>;
519 dma-names = "tx", "rx";
523 mcspi1: spi@48098000 {
524 compatible = "ti,omap4-mcspi";
525 reg = <0x48098000 0x200>;
526 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
527 #address-cells = <1>;
529 ti,hwmods = "mcspi1";
539 dma-names = "tx0", "rx0", "tx1", "rx1",
540 "tx2", "rx2", "tx3", "rx3";
544 mcspi2: spi@4809a000 {
545 compatible = "ti,omap4-mcspi";
546 reg = <0x4809a000 0x200>;
547 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
548 #address-cells = <1>;
550 ti,hwmods = "mcspi2";
556 dma-names = "tx0", "rx0", "tx1", "rx1";
560 mcspi3: spi@480b8000 {
561 compatible = "ti,omap4-mcspi";
562 reg = <0x480b8000 0x200>;
563 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
564 #address-cells = <1>;
566 ti,hwmods = "mcspi3";
568 dmas = <&sdma 15>, <&sdma 16>;
569 dma-names = "tx0", "rx0";
573 mcspi4: spi@480ba000 {
574 compatible = "ti,omap4-mcspi";
575 reg = <0x480ba000 0x200>;
576 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
577 #address-cells = <1>;
579 ti,hwmods = "mcspi4";
581 dmas = <&sdma 70>, <&sdma 71>;
582 dma-names = "tx0", "rx0";