arch/arm/boot/dts/armada-38x.dtsi

   1 /*
   2  * Device Tree Include file for Marvell Armada 38x family of SoCs.
   3  *
   4  * Copyright (C) 2014 Marvell
   5  *
   6  * Lior Amsalem <alior@marvell.com>
   7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   8  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   9  *
  10  * This file is licensed under the terms of the GNU General Public
  11  * License version 2.  This program is licensed "as is" without any
  12  * warranty of any kind, whether express or implied.
  13  */
  14
  15 #include "skeleton.dtsi"
  16 #include <dt-bindings/interrupt-controller/arm-gic.h>
  17 #include <dt-bindings/interrupt-controller/irq.h>
  18
  19 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
  20
  21 / {
  22         model = "Marvell Armada 38x family SoC";
  23         compatible = "marvell,armada38x";
  24
  25         aliases {
  26                 gpio0 = &gpio0;
  27                 gpio1 = &gpio1;
  28                 eth0 = &eth0;
  29                 eth1 = &eth1;
  30                 eth2 = &eth2;
  31         };
  32
  33         soc {
  34                 compatible = "marvell,armada380-mbus", "marvell,armada370-mbus",
  35                              "simple-bus";
  36                 #address-cells = <2>;
  37                 #size-cells = <1>;
  38                 controller = <&mbusc>;
  39                 interrupt-parent = <&gic>;
  40                 pcie-mem-aperture = <0xe0000000 0x8000000>;
  41                 pcie-io-aperture  = <0xe8000000 0x100000>;
  42
  43                 bootrom {
  44                         compatible = "marvell,bootrom";
  45                         reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
  46                 };
  47
  48                 devbus-bootcs {
  49                         compatible = "marvell,mvebu-devbus";
  50                         reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
  51                         ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
  52                         #address-cells = <1>;
  53                         #size-cells = <1>;
  54                         clocks = <&coreclk 0>;
  55                         status = "disabled";
  56                 };
  57
  58                 devbus-cs0 {
  59                         compatible = "marvell,mvebu-devbus";
  60                         reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
  61                         ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
  62                         #address-cells = <1>;
  63                         #size-cells = <1>;
  64                         clocks = <&coreclk 0>;
  65                         status = "disabled";
  66                 };
  67
  68                 devbus-cs1 {
  69                         compatible = "marvell,mvebu-devbus";
  70                         reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
  71                         ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
  72                         #address-cells = <1>;
  73                         #size-cells = <1>;
  74                         clocks = <&coreclk 0>;
  75                         status = "disabled";
  76                 };
  77
  78                 devbus-cs2 {
  79                         compatible = "marvell,mvebu-devbus";
  80                         reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
  81                         ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
  82                         #address-cells = <1>;
  83                         #size-cells = <1>;
  84                         clocks = <&coreclk 0>;
  85                         status = "disabled";
  86                 };
  87
  88                 devbus-cs3 {
  89                         compatible = "marvell,mvebu-devbus";
  90                         reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
  91                         ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
  92                         #address-cells = <1>;
  93                         #size-cells = <1>;
  94                         clocks = <&coreclk 0>;
  95                         status = "disabled";
  96                 };
  97
  98                 internal-regs {
  99                         compatible = "simple-bus";
 100                         #address-cells = <1>;
 101                         #size-cells = <1>;
 102                         ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
 103
 104                         L2: cache-controller@8000 {
 105                                 compatible = "arm,pl310-cache";
 106                                 reg = <0x8000 0x1000>;
 107                                 cache-unified;
 108                                 cache-level = <2>;
 109                         };
 110
 111                         timer@c600 {
 112                                 compatible = "arm,cortex-a9-twd-timer";
 113                                 reg = <0xc600 0x20>;
 114                                 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
 115                                 clocks = <&coreclk 2>;
 116                         };
 117
 118                         gic: interrupt-controller@d000 {
 119                                 compatible = "arm,cortex-a9-gic";
 120                                 #interrupt-cells = <3>;
 121                                 #size-cells = <0>;
 122                                 interrupt-controller;
 123                                 reg = <0xd000 0x1000>,
 124                                       <0xc100 0x100>;
 125                         };
 126
 127                         spi0: spi@10600 {
 128                                 compatible = "marvell,orion-spi";
 129                                 reg = <0x10600 0x50>;
 130                                 #address-cells = <1>;
 131                                 #size-cells = <0>;
 132                                 cell-index = <0>;
 133                                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 134                                 clocks = <&coreclk 0>;
 135                                 status = "disabled";
 136                         };
 137
 138                         spi1: spi@10680 {
 139                                 compatible = "marvell,orion-spi";
 140                                 reg = <0x10680 0x50>;
 141                                 #address-cells = <1>;
 142                                 #size-cells = <0>;
 143                                 cell-index = <1>;
 144                                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 145                                 clocks = <&coreclk 0>;
 146                                 status = "disabled";
 147                         };
 148
 149                         i2c0: i2c@11000 {
 150                                 compatible = "marvell,mv64xxx-i2c";
 151                                 reg = <0x11000 0x20>;
 152                                 #address-cells = <1>;
 153                                 #size-cells = <0>;
 154                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 155                                 timeout-ms = <1000>;
 156                                 clocks = <&coreclk 0>;
 157                                 status = "disabled";
 158                         };
 159
 160                         i2c1: i2c@11100 {
 161                                 compatible = "marvell,mv64xxx-i2c";
 162                                 reg = <0x11100 0x20>;
 163                                 #address-cells = <1>;
 164                                 #size-cells = <0>;
 165                                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 166                                 timeout-ms = <1000>;
 167                                 clocks = <&coreclk 0>;
 168                                 status = "disabled";
 169                         };
 170
 171                         serial@12000 {
 172                                 compatible = "snps,dw-apb-uart";
 173                                 reg = <0x12000 0x100>;
 174                                 reg-shift = <2>;
 175                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 176                                 reg-io-width = <1>;
 177                                 status = "disabled";
 178                         };
 179
 180                         serial@12100 {
 181                                 compatible = "snps,dw-apb-uart";
 182                                 reg = <0x12100 0x100>;
 183                                 reg-shift = <2>;
 184                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 185                                 reg-io-width = <1>;
 186                                 status = "disabled";
 187                         };
 188
 189                         pinctrl {
 190                                 compatible = "marvell,mv88f6820-pinctrl";
 191                                 reg = <0x18000 0x20>;
 192                         };
 193
 194                         gpio0: gpio@18100 {
 195                                 compatible = "marvell,orion-gpio";
 196                                 reg = <0x18100 0x40>;
 197                                 ngpios = <32>;
 198                                 gpio-controller;
 199                                 #gpio-cells = <2>;
 200                                 interrupt-controller;
 201                                 #interrupt-cells = <2>;
 202                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 203                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 204                                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 205                                              <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 206                         };
 207
 208                         gpio1: gpio@18140 {
 209                                 compatible = "marvell,orion-gpio";
 210                                 reg = <0x18140 0x40>;
 211                                 ngpios = <28>;
 212                                 gpio-controller;
 213                                 #gpio-cells = <2>;
 214                                 interrupt-controller;
 215                                 #interrupt-cells = <2>;
 216                                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 217                                              <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 218                                              <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 219                                              <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 220                         };
 221
 222                         system-controller@18200 {
 223                                 compatible = "marvell,armada-380-system-controller",
 224                                              "marvell,armada-370-xp-system-controller";
 225                                 reg = <0x18200 0x100>;
 226                         };
 227
 228                         gateclk: clock-gating-control@18220 {
 229                                 compatible = "marvell,armada-380-gating-clock";
 230                                 reg = <0x18220 0x4>;
 231                                 clocks = <&coreclk 0>;
 232                                 #clock-cells = <1>;
 233                         };
 234
 235                         coreclk: mvebu-sar@18600 {
 236                                 compatible = "marvell,armada-380-core-clock";
 237                                 reg = <0x18600 0x04>;
 238                                 #clock-cells = <1>;
 239                         };
 240
 241                         mbusc: mbus-controller@20000 {
 242                                 compatible = "marvell,mbus-controller";
 243                                 reg = <0x20000 0x100>, <0x20180 0x20>;
 244                         };
 245
 246                         mpic: interrupt-controller@20000 {
 247                                 compatible = "marvell,mpic";
 248                                 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
 249                                 #interrupt-cells = <1>;
 250                                 #size-cells = <1>;
 251                                 interrupt-controller;
 252                                 msi-controller;
 253                                 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
 254                         };
 255
 256                         timer@20300 {
 257                                 compatible = "marvell,armada-380-timer",
 258                                              "marvell,armada-xp-timer";
 259                                 reg = <0x20300 0x30>, <0x21040 0x30>;
 260                                 interrupts-extended = <&gic  GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
 261                                                       <&gic  GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
 262                                                       <&gic  GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
 263                                                       <&gic  GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 264                                                       <&mpic 5>,
 265                                                       <&mpic 6>;
 266                                 clocks = <&coreclk 2>, <&refclk>;
 267                                 clock-names = "nbclk", "fixed";
 268                         };
 269
 270                         eth1: ethernet@30000 {
 271                                 compatible = "marvell,armada-370-neta";
 272                                 reg = <0x30000 0x4000>;
 273                                 interrupts-extended = <&mpic 10>;
 274                                 clocks = <&gateclk 3>;
 275                                 status = "disabled";
 276                         };
 277
 278                         eth2: ethernet@34000 {
 279                                 compatible = "marvell,armada-370-neta";
 280                                 reg = <0x34000 0x4000>;
 281                                 interrupts-extended = <&mpic 12>;
 282                                 clocks = <&gateclk 2>;
 283                                 status = "disabled";
 284                         };
 285
 286                         xor@60800 {
 287                                 compatible = "marvell,orion-xor";
 288                                 reg = <0x60800 0x100
 289                                        0x60a00 0x100>;
 290                                 clocks = <&gateclk 22>;
 291                                 status = "okay";
 292
 293                                 xor00 {
 294                                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 295                                         dmacap,memcpy;
 296                                         dmacap,xor;
 297                                 };
 298                                 xor01 {
 299                                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 300                                         dmacap,memcpy;
 301                                         dmacap,xor;
 302                                         dmacap,memset;
 303                                 };
 304                         };
 305
 306                         xor@60900 {
 307                                 compatible = "marvell,orion-xor";
 308                                 reg = <0x60900 0x100
 309                                        0x60b00 0x100>;
 310                                 clocks = <&gateclk 28>;
 311                                 status = "okay";
 312
 313                                 xor10 {
 314                                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 315                                         dmacap,memcpy;
 316                                         dmacap,xor;
 317                                 };
 318                                 xor11 {
 319                                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 320                                         dmacap,memcpy;
 321                                         dmacap,xor;
 322                                         dmacap,memset;
 323                                 };
 324                         };
 325
 326                         eth0: ethernet@70000 {
 327                                 compatible = "marvell,armada-370-neta";
 328                                 reg = <0x70000 0x4000>;
 329                                 interrupts-extended = <&mpic 8>;
 330                                 clocks = <&gateclk 4>;
 331                                 status = "disabled";
 332                         };
 333
 334                         mdio {
 335                                 #address-cells = <1>;
 336                                 #size-cells = <0>;
 337                                 compatible = "marvell,orion-mdio";
 338                                 reg = <0x72004 0x4>;
 339                                 clocks = <&gateclk 4>;
 340                         };
 341
 342                         coredivclk: clock@e4250 {
 343                                 compatible = "marvell,armada-380-corediv-clock";
 344                                 reg = <0xe4250 0xc>;
 345                                 #clock-cells = <1>;
 346                                 clocks = <&mainpll>;
 347                                 clock-output-names = "nand";
 348                         };
 349
 350                         flash@d0000 {
 351                                 compatible = "marvell,armada370-nand";
 352                                 reg = <0xd0000 0x54>;
 353                                 #address-cells = <1>;
 354                                 #size-cells = <1>;
 355                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 356                                 clocks = <&coredivclk 0>;
 357                                 status = "disabled";
 358                         };
 359                 };
 360         };
 361
 362         clocks {
 363                 /* 2 GHz fixed main PLL */
 364                 mainpll: mainpll {
 365                         compatible = "fixed-clock";
 366                         #clock-cells = <0>;
 367                         clock-frequency = <2000000000>;
 368                 };
 369
 370                 /* 25 MHz reference crystal */
 371                 refclk: oscillator {
 372                         compatible = "fixed-clock";
 373                         #clock-cells = <0>;
 374                         clock-frequency = <25000000>;
 375                 };
 376         };
 377 };