2 * Device Tree Include file for Marvell Armada 370 and Armada XP SoC
4 * Copyright (C) 2012 Marvell
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
15 * This file contains the definitions that are common to the Armada
16 * 370 and Armada XP SoC.
19 /include/ "skeleton.dtsi"
22 model = "Marvell Armada 370 and XP SoC";
23 compatible = "marvell,armada-370-xp";
27 compatible = "marvell,sheeva-v7";
31 mpic: interrupt-controller@d0020000 {
32 compatible = "marvell,mpic";
33 #interrupt-cells = <1>;
39 coherency-fabric@d0020200 {
40 compatible = "marvell,coherency-fabric";
41 reg = <0xd0020200 0xb0>,
48 compatible = "simple-bus";
49 interrupt-parent = <&mpic>;
53 compatible = "snps,dw-apb-uart";
54 reg = <0xd0012000 0x100>;
61 compatible = "snps,dw-apb-uart";
62 reg = <0xd0012100 0x100>;
70 compatible = "marvell,armada-370-xp-timer";
71 reg = <0xd0020300 0x30>;
72 interrupts = <37>, <38>, <39>, <40>;
73 clocks = <&coreclk 2>;
76 addr-decoding@d0020000 {
77 compatible = "marvell,armada-addr-decoding-controller";
78 reg = <0xd0020000 0x258>;
82 compatible = "marvell,orion-sata";
83 reg = <0xd00a0000 0x2400>;
85 clocks = <&gateclk 15>, <&gateclk 30>;
86 clock-names = "0", "1";
93 compatible = "marvell,orion-mdio";
94 reg = <0xd0072004 0x4>;
98 compatible = "marvell,armada-370-neta";
99 reg = <0xd0070000 0x2500>;
101 clocks = <&gateclk 4>;
106 compatible = "marvell,armada-370-neta";
107 reg = <0xd0074000 0x2500>;
109 clocks = <&gateclk 3>;
114 compatible = "marvell,mv64xxx-i2c";
115 reg = <0xd0011000 0x20>;
116 #address-cells = <1>;
120 clocks = <&coreclk 0>;
125 compatible = "marvell,mv64xxx-i2c";
126 reg = <0xd0011100 0x20>;
127 #address-cells = <1>;
131 clocks = <&coreclk 0>;