5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if !XIP_KERNEL
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
33 The ARM series is a line of low-power-consumption RISC chip designs
34 licensed by ARM Ltd and targeted at embedded applications and
35 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
36 manufactured, but legacy ARM-based PC hardware remains popular in
37 Europe. There is an ARM Linux project with a web page at
38 <http://www.arm.linux.org.uk/>.
40 config ARM_HAS_SG_CHAIN
49 config SYS_SUPPORTS_APM_EMULATION
52 config HAVE_SCHED_CLOCK
58 config ARCH_USES_GETTIMEOFFSET
62 config GENERIC_CLOCKEVENTS
65 config GENERIC_CLOCKEVENTS_BROADCAST
67 depends on GENERIC_CLOCKEVENTS
76 select GENERIC_ALLOCATOR
87 The Extended Industry Standard Architecture (EISA) bus was
88 developed as an open alternative to the IBM MicroChannel bus.
90 The EISA bus provided some of the features of the IBM MicroChannel
91 bus while maintaining backward compatibility with cards made for
92 the older ISA bus. The EISA bus saw limited use between 1988 and
93 1995 when it was made obsolete by the PCI bus.
95 Say Y here if you are building a kernel for an EISA-based machine.
105 MicroChannel Architecture is found in some IBM PS/2 machines and
106 laptops. It is a bus system similar to PCI or ISA. See
107 <file:Documentation/mca.txt> (and especially the web page given
108 there) before attempting to build an MCA bus kernel.
110 config STACKTRACE_SUPPORT
114 config HAVE_LATENCYTOP_SUPPORT
119 config LOCKDEP_SUPPORT
123 config TRACE_IRQFLAGS_SUPPORT
127 config HARDIRQS_SW_RESEND
131 config GENERIC_IRQ_PROBE
135 config GENERIC_LOCKBREAK
138 depends on SMP && PREEMPT
140 config RWSEM_GENERIC_SPINLOCK
144 config RWSEM_XCHGADD_ALGORITHM
147 config ARCH_HAS_ILOG2_U32
150 config ARCH_HAS_ILOG2_U64
153 config ARCH_HAS_CPUFREQ
156 Internal node to signify that the ARCH has CPUFREQ support
157 and that the relevant menu configurations are displayed for
160 config ARCH_HAS_CPU_IDLE_WAIT
163 config GENERIC_HWEIGHT
167 config GENERIC_CALIBRATE_DELAY
171 config ARCH_MAY_HAVE_PC_FDC
177 config NEED_DMA_MAP_STATE
180 config GENERIC_ISA_DMA
191 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
192 default DRAM_BASE if REMAP_VECTORS_TO_RAM
195 The base address of exception vectors.
197 config ARM_PATCH_PHYS_VIRT
198 bool "Patch physical to virtual translations at runtime" if EMBEDDED
200 depends on !XIP_KERNEL && MMU
201 depends on !ARCH_REALVIEW || !SPARSEMEM
203 Patch phys-to-virt and virt-to-phys translation functions at
204 boot and module load time according to the position of the
205 kernel in system memory.
207 This can only be used with non-XIP MMU kernels where the base
208 of physical memory is at a 16MB boundary.
210 Only disable this option if you know that you do not require
211 this feature (eg, building a kernel for a single machine) and
212 you need to shrink the kernel to the minimal size.
214 config NO_MACH_MEMORY_H
217 Select this when mach/memory.h is removed.
220 hex "Physical address of main memory"
221 depends on !ARM_PATCH_PHYS_VIRT && NO_MACH_MEMORY_H
223 Please provide the physical address corresponding to the
224 location of main memory in your system.
226 source "init/Kconfig"
228 source "kernel/Kconfig.freezer"
233 bool "MMU-based Paged Memory Management Support"
236 Select if you want MMU-based virtualised addressing space
237 support by paged memory management. If unsure, say 'Y'.
240 # The "ARM system type" choice list is ordered alphabetically by option
241 # text. Please add new entries in the option alphabetic order.
244 prompt "ARM system type"
245 default ARCH_VERSATILE
247 config ARCH_INTEGRATOR
248 bool "ARM Ltd. Integrator family"
250 select ARCH_HAS_CPUFREQ
252 select HAVE_MACH_CLKDEV
254 select GENERIC_CLOCKEVENTS
255 select PLAT_VERSATILE
256 select PLAT_VERSATILE_FPGA_IRQ
258 Support for ARM's Integrator platform.
261 bool "ARM Ltd. RealView family"
264 select HAVE_MACH_CLKDEV
266 select GENERIC_CLOCKEVENTS
267 select ARCH_WANT_OPTIONAL_GPIOLIB
268 select PLAT_VERSATILE
269 select PLAT_VERSATILE_CLCD
270 select ARM_TIMER_SP804
271 select GPIO_PL061 if GPIOLIB
273 This enables support for ARM Ltd RealView boards.
275 config ARCH_VERSATILE
276 bool "ARM Ltd. Versatile family"
280 select HAVE_MACH_CLKDEV
282 select GENERIC_CLOCKEVENTS
283 select ARCH_WANT_OPTIONAL_GPIOLIB
284 select PLAT_VERSATILE
285 select PLAT_VERSATILE_CLCD
286 select PLAT_VERSATILE_FPGA_IRQ
287 select ARM_TIMER_SP804
289 This enables support for ARM Ltd Versatile board.
292 bool "ARM Ltd. Versatile Express family"
293 select ARCH_WANT_OPTIONAL_GPIOLIB
295 select ARM_TIMER_SP804
297 select HAVE_MACH_CLKDEV
298 select GENERIC_CLOCKEVENTS
300 select HAVE_PATA_PLATFORM
302 select PLAT_VERSATILE
303 select PLAT_VERSATILE_CLCD
305 This enables support for the ARM Ltd Versatile Express boards.
309 select ARCH_REQUIRE_GPIOLIB
313 This enables support for systems based on the Atmel AT91RM9200,
314 AT91SAM9 and AT91CAP9 processors.
317 bool "Broadcom BCMRING"
321 select ARM_TIMER_SP804
323 select GENERIC_CLOCKEVENTS
324 select ARCH_WANT_OPTIONAL_GPIOLIB
326 Support for Broadcom's BCMRing platform.
329 bool "Cirrus Logic CLPS711x/EP721x-based"
331 select ARCH_USES_GETTIMEOFFSET
333 Support for Cirrus Logic 711x/721x based boards.
336 bool "Cavium Networks CNS3XXX family"
338 select GENERIC_CLOCKEVENTS
340 select MIGHT_HAVE_PCI
341 select PCI_DOMAINS if PCI
343 Support for Cavium Networks CNS3XXX platform.
346 bool "Cortina Systems Gemini"
348 select ARCH_REQUIRE_GPIOLIB
349 select ARCH_USES_GETTIMEOFFSET
351 Support for the Cortina Systems Gemini family SoCs
354 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
358 select GENERIC_CLOCKEVENTS
360 select GENERIC_IRQ_CHIP
364 Support for CSR SiRFSoC ARM Cortex A9 Platform
371 select ARCH_USES_GETTIMEOFFSET
373 This is an evaluation board for the StrongARM processor available
374 from Digital. It has limited hardware on-board, including an
375 Ethernet interface, two PCMCIA sockets, two serial ports and a
384 select ARCH_REQUIRE_GPIOLIB
385 select ARCH_HAS_HOLES_MEMORYMODEL
386 select ARCH_USES_GETTIMEOFFSET
388 This enables support for the Cirrus EP93xx series of CPUs.
390 config ARCH_FOOTBRIDGE
394 select GENERIC_CLOCKEVENTS
396 Support for systems based on the DC21285 companion chip
397 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
400 bool "Freescale MXC/iMX-based"
401 select GENERIC_CLOCKEVENTS
402 select ARCH_REQUIRE_GPIOLIB
405 select GENERIC_IRQ_CHIP
406 select HAVE_SCHED_CLOCK
408 Support for Freescale MXC/iMX-based family of processors
411 bool "Freescale MXS-based"
412 select GENERIC_CLOCKEVENTS
413 select ARCH_REQUIRE_GPIOLIB
417 Support for Freescale MXS-based family of processors
420 bool "Hilscher NetX based"
424 select GENERIC_CLOCKEVENTS
426 This enables support for systems based on the Hilscher NetX Soc
429 bool "Hynix HMS720x-based"
432 select ARCH_USES_GETTIMEOFFSET
434 This enables support for systems based on the Hynix HMS720x
442 select ARCH_SUPPORTS_MSI
445 Support for Intel's IOP13XX (XScale) family of processors.
453 select ARCH_REQUIRE_GPIOLIB
455 Support for Intel's 80219 and IOP32X (XScale) family of
464 select ARCH_REQUIRE_GPIOLIB
466 Support for Intel's IOP33X (XScale) family of processors.
473 select ARCH_USES_GETTIMEOFFSET
475 Support for Intel's IXP23xx (XScale) family of processors.
478 bool "IXP2400/2800-based"
482 select ARCH_USES_GETTIMEOFFSET
484 Support for Intel's IXP2400/2800 (XScale) family of processors.
492 select GENERIC_CLOCKEVENTS
493 select HAVE_SCHED_CLOCK
494 select MIGHT_HAVE_PCI
495 select DMABOUNCE if PCI
497 Support for Intel's IXP4XX (XScale) family of processors.
503 select ARCH_REQUIRE_GPIOLIB
504 select GENERIC_CLOCKEVENTS
506 select NO_MACH_MEMORY_H
508 Support for the Marvell Dove SoC 88AP510
511 bool "Marvell Kirkwood"
514 select ARCH_REQUIRE_GPIOLIB
515 select GENERIC_CLOCKEVENTS
518 Support for the following Marvell Kirkwood series SoCs:
519 88F6180, 88F6192 and 88F6281.
525 select ARCH_REQUIRE_GPIOLIB
528 select USB_ARCH_HAS_OHCI
531 select GENERIC_CLOCKEVENTS
533 Support for the NXP LPC32XX family of processors
536 bool "Marvell MV78xx0"
539 select ARCH_REQUIRE_GPIOLIB
540 select GENERIC_CLOCKEVENTS
543 Support for the following Marvell MV78xx0 series SoCs:
551 select ARCH_REQUIRE_GPIOLIB
552 select GENERIC_CLOCKEVENTS
555 Support for the following Marvell Orion 5x series SoCs:
556 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
557 Orion-2 (5281), Orion-1-90 (6183).
560 bool "Marvell PXA168/910/MMP2"
562 select ARCH_REQUIRE_GPIOLIB
564 select GENERIC_CLOCKEVENTS
565 select HAVE_SCHED_CLOCK
570 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
573 bool "Micrel/Kendin KS8695"
575 select ARCH_REQUIRE_GPIOLIB
576 select ARCH_USES_GETTIMEOFFSET
578 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
579 System-on-Chip devices.
582 bool "Nuvoton W90X900 CPU"
584 select ARCH_REQUIRE_GPIOLIB
587 select GENERIC_CLOCKEVENTS
589 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
590 At present, the w90x900 has been renamed nuc900, regarding
591 the ARM series product line, you can login the following
592 link address to know more.
594 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
595 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
598 bool "Nuvoton NUC93X CPU"
602 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
603 low-power and high performance MPEG-4/JPEG multimedia controller chip.
610 select GENERIC_CLOCKEVENTS
613 select HAVE_SCHED_CLOCK
614 select ARCH_HAS_CPUFREQ
616 This enables support for NVIDIA Tegra based systems (Tegra APX,
617 Tegra 6xx and Tegra 2 series).
620 bool "Philips Nexperia PNX4008 Mobile"
623 select ARCH_USES_GETTIMEOFFSET
625 This enables support for Philips PNX4008 mobile platform.
628 bool "PXA2xx/PXA3xx-based"
631 select ARCH_HAS_CPUFREQ
634 select ARCH_REQUIRE_GPIOLIB
635 select GENERIC_CLOCKEVENTS
636 select HAVE_SCHED_CLOCK
641 select MULTI_IRQ_HANDLER
643 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
648 select GENERIC_CLOCKEVENTS
649 select ARCH_REQUIRE_GPIOLIB
652 Support for Qualcomm MSM/QSD based systems. This runs on the
653 apps processor of the MSM/QSD and depends on a shared memory
654 interface to the modem processor which runs the baseband
655 stack and controls some vital subsystems
656 (clock and power control, etc).
659 bool "Renesas SH-Mobile / R-Mobile"
662 select HAVE_MACH_CLKDEV
663 select GENERIC_CLOCKEVENTS
666 select MULTI_IRQ_HANDLER
667 select PM_GENERIC_DOMAINS if PM
669 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
676 select ARCH_MAY_HAVE_PC_FDC
677 select HAVE_PATA_PLATFORM
680 select ARCH_SPARSEMEM_ENABLE
681 select ARCH_USES_GETTIMEOFFSET
683 On the Acorn Risc-PC, Linux can support the internal IDE disk and
684 CD-ROM interface, serial and parallel port, and the floppy drive.
691 select ARCH_SPARSEMEM_ENABLE
693 select ARCH_HAS_CPUFREQ
695 select GENERIC_CLOCKEVENTS
697 select HAVE_SCHED_CLOCK
699 select ARCH_REQUIRE_GPIOLIB
701 Support for StrongARM 11x0 based boards.
704 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
706 select ARCH_HAS_CPUFREQ
709 select ARCH_USES_GETTIMEOFFSET
710 select HAVE_S3C2410_I2C if I2C
712 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
713 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
714 the Samsung SMDK2410 development board (and derivatives).
716 Note, the S3C2416 and the S3C2450 are so close that they even share
717 the same SoC ID code. This means that there is no separate machine
718 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
721 bool "Samsung S3C64XX"
728 select ARCH_USES_GETTIMEOFFSET
729 select ARCH_HAS_CPUFREQ
730 select ARCH_REQUIRE_GPIOLIB
731 select SAMSUNG_CLKSRC
732 select SAMSUNG_IRQ_VIC_TIMER
733 select SAMSUNG_IRQ_UART
734 select S3C_GPIO_TRACK
735 select S3C_GPIO_PULL_UPDOWN
736 select S3C_GPIO_CFG_S3C24XX
737 select S3C_GPIO_CFG_S3C64XX
739 select USB_ARCH_HAS_OHCI
740 select SAMSUNG_GPIOLIB_4BIT
741 select HAVE_S3C2410_I2C if I2C
742 select HAVE_S3C2410_WATCHDOG if WATCHDOG
744 Samsung S3C64XX series based systems
747 bool "Samsung S5P6440 S5P6450"
753 select HAVE_S3C2410_WATCHDOG if WATCHDOG
754 select GENERIC_CLOCKEVENTS
755 select HAVE_SCHED_CLOCK
756 select HAVE_S3C2410_I2C if I2C
757 select HAVE_S3C_RTC if RTC_CLASS
759 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
763 bool "Samsung S5PC100"
768 select ARM_L1_CACHE_SHIFT_6
769 select ARCH_USES_GETTIMEOFFSET
770 select HAVE_S3C2410_I2C if I2C
771 select HAVE_S3C_RTC if RTC_CLASS
772 select HAVE_S3C2410_WATCHDOG if WATCHDOG
774 Samsung S5PC100 series based systems
777 bool "Samsung S5PV210/S5PC110"
779 select ARCH_SPARSEMEM_ENABLE
780 select ARCH_HAS_HOLES_MEMORYMODEL
785 select ARM_L1_CACHE_SHIFT_6
786 select ARCH_HAS_CPUFREQ
787 select GENERIC_CLOCKEVENTS
788 select HAVE_SCHED_CLOCK
789 select HAVE_S3C2410_I2C if I2C
790 select HAVE_S3C_RTC if RTC_CLASS
791 select HAVE_S3C2410_WATCHDOG if WATCHDOG
793 Samsung S5PV210/S5PC110 series based systems
796 bool "Samsung EXYNOS4"
798 select ARCH_SPARSEMEM_ENABLE
799 select ARCH_HAS_HOLES_MEMORYMODEL
803 select ARCH_HAS_CPUFREQ
804 select GENERIC_CLOCKEVENTS
805 select HAVE_S3C_RTC if RTC_CLASS
806 select HAVE_S3C2410_I2C if I2C
807 select HAVE_S3C2410_WATCHDOG if WATCHDOG
809 Samsung EXYNOS4 series based systems
818 select ARCH_USES_GETTIMEOFFSET
820 Support for the StrongARM based Digital DNARD machine, also known
821 as "Shark" (<http://www.shark-linux.de/shark.html>).
824 bool "Telechips TCC ARM926-based systems"
829 select GENERIC_CLOCKEVENTS
831 Support for Telechips TCC ARM926-based systems.
834 bool "ST-Ericsson U300 Series"
838 select HAVE_SCHED_CLOCK
842 select GENERIC_CLOCKEVENTS
844 select HAVE_MACH_CLKDEV
847 Support for ST-Ericsson U300 series mobile platforms.
850 bool "ST-Ericsson U8500 Series"
853 select GENERIC_CLOCKEVENTS
855 select ARCH_REQUIRE_GPIOLIB
856 select ARCH_HAS_CPUFREQ
858 Support for ST-Ericsson's Ux500 architecture
861 bool "STMicroelectronics Nomadik"
866 select GENERIC_CLOCKEVENTS
867 select ARCH_REQUIRE_GPIOLIB
869 Support for the Nomadik platform by ST-Ericsson
873 select GENERIC_CLOCKEVENTS
874 select ARCH_REQUIRE_GPIOLIB
878 select GENERIC_ALLOCATOR
879 select GENERIC_IRQ_CHIP
880 select ARCH_HAS_HOLES_MEMORYMODEL
882 Support for TI's DaVinci platform.
887 select ARCH_REQUIRE_GPIOLIB
888 select ARCH_HAS_CPUFREQ
890 select GENERIC_CLOCKEVENTS
891 select HAVE_SCHED_CLOCK
892 select ARCH_HAS_HOLES_MEMORYMODEL
894 Support for TI's OMAP platform (OMAP1/2/3/4).
899 select ARCH_REQUIRE_GPIOLIB
902 select GENERIC_CLOCKEVENTS
905 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
908 bool "VIA/WonderMedia 85xx"
911 select ARCH_HAS_CPUFREQ
912 select GENERIC_CLOCKEVENTS
913 select ARCH_REQUIRE_GPIOLIB
916 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
919 bool "Xilinx Zynq ARM Cortex A9 Platform"
922 select GENERIC_CLOCKEVENTS
929 Support for Xilinx Zynq ARM Cortex A9 Platform
933 # This is sorted alphabetically by mach-* pathname. However, plat-*
934 # Kconfigs may be included either alphabetically (according to the
935 # plat- suffix) or along side the corresponding mach-* source.
937 source "arch/arm/mach-at91/Kconfig"
939 source "arch/arm/mach-bcmring/Kconfig"
941 source "arch/arm/mach-clps711x/Kconfig"
943 source "arch/arm/mach-cns3xxx/Kconfig"
945 source "arch/arm/mach-davinci/Kconfig"
947 source "arch/arm/mach-dove/Kconfig"
949 source "arch/arm/mach-ep93xx/Kconfig"
951 source "arch/arm/mach-footbridge/Kconfig"
953 source "arch/arm/mach-gemini/Kconfig"
955 source "arch/arm/mach-h720x/Kconfig"
957 source "arch/arm/mach-integrator/Kconfig"
959 source "arch/arm/mach-iop32x/Kconfig"
961 source "arch/arm/mach-iop33x/Kconfig"
963 source "arch/arm/mach-iop13xx/Kconfig"
965 source "arch/arm/mach-ixp4xx/Kconfig"
967 source "arch/arm/mach-ixp2000/Kconfig"
969 source "arch/arm/mach-ixp23xx/Kconfig"
971 source "arch/arm/mach-kirkwood/Kconfig"
973 source "arch/arm/mach-ks8695/Kconfig"
975 source "arch/arm/mach-lpc32xx/Kconfig"
977 source "arch/arm/mach-msm/Kconfig"
979 source "arch/arm/mach-mv78xx0/Kconfig"
981 source "arch/arm/plat-mxc/Kconfig"
983 source "arch/arm/mach-mxs/Kconfig"
985 source "arch/arm/mach-netx/Kconfig"
987 source "arch/arm/mach-nomadik/Kconfig"
988 source "arch/arm/plat-nomadik/Kconfig"
990 source "arch/arm/mach-nuc93x/Kconfig"
992 source "arch/arm/plat-omap/Kconfig"
994 source "arch/arm/mach-omap1/Kconfig"
996 source "arch/arm/mach-omap2/Kconfig"
998 source "arch/arm/mach-orion5x/Kconfig"
1000 source "arch/arm/mach-pxa/Kconfig"
1001 source "arch/arm/plat-pxa/Kconfig"
1003 source "arch/arm/mach-mmp/Kconfig"
1005 source "arch/arm/mach-realview/Kconfig"
1007 source "arch/arm/mach-sa1100/Kconfig"
1009 source "arch/arm/plat-samsung/Kconfig"
1010 source "arch/arm/plat-s3c24xx/Kconfig"
1011 source "arch/arm/plat-s5p/Kconfig"
1013 source "arch/arm/plat-spear/Kconfig"
1015 source "arch/arm/plat-tcc/Kconfig"
1018 source "arch/arm/mach-s3c2410/Kconfig"
1019 source "arch/arm/mach-s3c2412/Kconfig"
1020 source "arch/arm/mach-s3c2416/Kconfig"
1021 source "arch/arm/mach-s3c2440/Kconfig"
1022 source "arch/arm/mach-s3c2443/Kconfig"
1026 source "arch/arm/mach-s3c64xx/Kconfig"
1029 source "arch/arm/mach-s5p64x0/Kconfig"
1031 source "arch/arm/mach-s5pc100/Kconfig"
1033 source "arch/arm/mach-s5pv210/Kconfig"
1035 source "arch/arm/mach-exynos4/Kconfig"
1037 source "arch/arm/mach-shmobile/Kconfig"
1039 source "arch/arm/mach-tegra/Kconfig"
1041 source "arch/arm/mach-u300/Kconfig"
1043 source "arch/arm/mach-ux500/Kconfig"
1045 source "arch/arm/mach-versatile/Kconfig"
1047 source "arch/arm/mach-vexpress/Kconfig"
1048 source "arch/arm/plat-versatile/Kconfig"
1050 source "arch/arm/mach-vt8500/Kconfig"
1052 source "arch/arm/mach-w90x900/Kconfig"
1054 # Definitions to make life easier
1060 select GENERIC_CLOCKEVENTS
1061 select HAVE_SCHED_CLOCK
1066 select GENERIC_IRQ_CHIP
1067 select HAVE_SCHED_CLOCK
1072 config PLAT_VERSATILE
1075 config ARM_TIMER_SP804
1079 source arch/arm/mm/Kconfig
1082 bool "Enable iWMMXt support"
1083 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1084 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1086 Enable support for iWMMXt context switching at run time if
1087 running on a CPU that supports it.
1089 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1092 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1096 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1097 (!ARCH_OMAP3 || OMAP3_EMU)
1101 config MULTI_IRQ_HANDLER
1104 Allow each machine to specify it's own IRQ handler at run time.
1107 source "arch/arm/Kconfig-nommu"
1110 config ARM_ERRATA_411920
1111 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1112 depends on CPU_V6 || CPU_V6K
1114 Invalidation of the Instruction Cache operation can
1115 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1116 It does not affect the MPCore. This option enables the ARM Ltd.
1117 recommended workaround.
1119 config ARM_ERRATA_430973
1120 bool "ARM errata: Stale prediction on replaced interworking branch"
1123 This option enables the workaround for the 430973 Cortex-A8
1124 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1125 interworking branch is replaced with another code sequence at the
1126 same virtual address, whether due to self-modifying code or virtual
1127 to physical address re-mapping, Cortex-A8 does not recover from the
1128 stale interworking branch prediction. This results in Cortex-A8
1129 executing the new code sequence in the incorrect ARM or Thumb state.
1130 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1131 and also flushes the branch target cache at every context switch.
1132 Note that setting specific bits in the ACTLR register may not be
1133 available in non-secure mode.
1135 config ARM_ERRATA_458693
1136 bool "ARM errata: Processor deadlock when a false hazard is created"
1139 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1140 erratum. For very specific sequences of memory operations, it is
1141 possible for a hazard condition intended for a cache line to instead
1142 be incorrectly associated with a different cache line. This false
1143 hazard might then cause a processor deadlock. The workaround enables
1144 the L1 caching of the NEON accesses and disables the PLD instruction
1145 in the ACTLR register. Note that setting specific bits in the ACTLR
1146 register may not be available in non-secure mode.
1148 config ARM_ERRATA_460075
1149 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1152 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1153 erratum. Any asynchronous access to the L2 cache may encounter a
1154 situation in which recent store transactions to the L2 cache are lost
1155 and overwritten with stale memory contents from external memory. The
1156 workaround disables the write-allocate mode for the L2 cache via the
1157 ACTLR register. Note that setting specific bits in the ACTLR register
1158 may not be available in non-secure mode.
1160 config ARM_ERRATA_742230
1161 bool "ARM errata: DMB operation may be faulty"
1162 depends on CPU_V7 && SMP
1164 This option enables the workaround for the 742230 Cortex-A9
1165 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1166 between two write operations may not ensure the correct visibility
1167 ordering of the two writes. This workaround sets a specific bit in
1168 the diagnostic register of the Cortex-A9 which causes the DMB
1169 instruction to behave as a DSB, ensuring the correct behaviour of
1172 config ARM_ERRATA_742231
1173 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1174 depends on CPU_V7 && SMP
1176 This option enables the workaround for the 742231 Cortex-A9
1177 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1178 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1179 accessing some data located in the same cache line, may get corrupted
1180 data due to bad handling of the address hazard when the line gets
1181 replaced from one of the CPUs at the same time as another CPU is
1182 accessing it. This workaround sets specific bits in the diagnostic
1183 register of the Cortex-A9 which reduces the linefill issuing
1184 capabilities of the processor.
1186 config PL310_ERRATA_588369
1187 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1188 depends on CACHE_L2X0
1190 The PL310 L2 cache controller implements three types of Clean &
1191 Invalidate maintenance operations: by Physical Address
1192 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1193 They are architecturally defined to behave as the execution of a
1194 clean operation followed immediately by an invalidate operation,
1195 both performing to the same memory location. This functionality
1196 is not correctly implemented in PL310 as clean lines are not
1197 invalidated as a result of these operations.
1199 config ARM_ERRATA_720789
1200 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1201 depends on CPU_V7 && SMP
1203 This option enables the workaround for the 720789 Cortex-A9 (prior to
1204 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1205 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1206 As a consequence of this erratum, some TLB entries which should be
1207 invalidated are not, resulting in an incoherency in the system page
1208 tables. The workaround changes the TLB flushing routines to invalidate
1209 entries regardless of the ASID.
1211 config PL310_ERRATA_727915
1212 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1213 depends on CACHE_L2X0
1215 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1216 operation (offset 0x7FC). This operation runs in background so that
1217 PL310 can handle normal accesses while it is in progress. Under very
1218 rare circumstances, due to this erratum, write data can be lost when
1219 PL310 treats a cacheable write transaction during a Clean &
1220 Invalidate by Way operation.
1222 config ARM_ERRATA_743622
1223 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1226 This option enables the workaround for the 743622 Cortex-A9
1227 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1228 optimisation in the Cortex-A9 Store Buffer may lead to data
1229 corruption. This workaround sets a specific bit in the diagnostic
1230 register of the Cortex-A9 which disables the Store Buffer
1231 optimisation, preventing the defect from occurring. This has no
1232 visible impact on the overall performance or power consumption of the
1235 config ARM_ERRATA_751472
1236 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1237 depends on CPU_V7 && SMP
1239 This option enables the workaround for the 751472 Cortex-A9 (prior
1240 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1241 completion of a following broadcasted operation if the second
1242 operation is received by a CPU before the ICIALLUIS has completed,
1243 potentially leading to corrupted entries in the cache or TLB.
1245 config ARM_ERRATA_753970
1246 bool "ARM errata: cache sync operation may be faulty"
1247 depends on CACHE_PL310
1249 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1251 Under some condition the effect of cache sync operation on
1252 the store buffer still remains when the operation completes.
1253 This means that the store buffer is always asked to drain and
1254 this prevents it from merging any further writes. The workaround
1255 is to replace the normal offset of cache sync operation (0x730)
1256 by another offset targeting an unmapped PL310 register 0x740.
1257 This has the same effect as the cache sync operation: store buffer
1258 drain and waiting for all buffers empty.
1260 config ARM_ERRATA_754322
1261 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1264 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1265 r3p*) erratum. A speculative memory access may cause a page table walk
1266 which starts prior to an ASID switch but completes afterwards. This
1267 can populate the micro-TLB with a stale entry which may be hit with
1268 the new ASID. This workaround places two dsb instructions in the mm
1269 switching code so that no page table walks can cross the ASID switch.
1271 config ARM_ERRATA_754327
1272 bool "ARM errata: no automatic Store Buffer drain"
1273 depends on CPU_V7 && SMP
1275 This option enables the workaround for the 754327 Cortex-A9 (prior to
1276 r2p0) erratum. The Store Buffer does not have any automatic draining
1277 mechanism and therefore a livelock may occur if an external agent
1278 continuously polls a memory location waiting to observe an update.
1279 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1280 written polling loops from denying visibility of updates to memory.
1284 source "arch/arm/common/Kconfig"
1294 Find out whether you have ISA slots on your motherboard. ISA is the
1295 name of a bus system, i.e. the way the CPU talks to the other stuff
1296 inside your box. Other bus systems are PCI, EISA, MicroChannel
1297 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1298 newer boards don't support it. If you have ISA, say Y, otherwise N.
1300 # Select ISA DMA controller support
1305 # Select ISA DMA interface
1310 bool "PCI support" if MIGHT_HAVE_PCI
1312 Find out whether you have a PCI motherboard. PCI is the name of a
1313 bus system, i.e. the way the CPU talks to the other stuff inside
1314 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1315 VESA. If you have PCI, say Y, otherwise N.
1321 config PCI_NANOENGINE
1322 bool "BSE nanoEngine PCI support"
1323 depends on SA1100_NANOENGINE
1325 Enable PCI on the BSE nanoEngine board.
1330 # Select the host bridge type
1331 config PCI_HOST_VIA82C505
1333 depends on PCI && ARCH_SHARK
1336 config PCI_HOST_ITE8152
1338 depends on PCI && MACH_ARMCORE
1342 source "drivers/pci/Kconfig"
1344 source "drivers/pcmcia/Kconfig"
1348 menu "Kernel Features"
1350 source "kernel/time/Kconfig"
1353 bool "Symmetric Multi-Processing"
1354 depends on CPU_V6K || CPU_V7
1355 depends on GENERIC_CLOCKEVENTS
1356 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1357 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1358 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1359 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1360 select USE_GENERIC_SMP_HELPERS
1361 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1363 This enables support for systems with more than one CPU. If you have
1364 a system with only one CPU, like most personal computers, say N. If
1365 you have a system with more than one CPU, say Y.
1367 If you say N here, the kernel will run on single and multiprocessor
1368 machines, but will use only one CPU of a multiprocessor machine. If
1369 you say Y here, the kernel will run on many, but not all, single
1370 processor machines. On a single processor machine, the kernel will
1371 run faster if you say N here.
1373 See also <file:Documentation/i386/IO-APIC.txt>,
1374 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1375 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1377 If you don't know what to do here, say N.
1380 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1381 depends on EXPERIMENTAL
1382 depends on SMP && !XIP_KERNEL
1385 SMP kernels contain instructions which fail on non-SMP processors.
1386 Enabling this option allows the kernel to modify itself to make
1387 these instructions safe. Disabling it allows about 1K of space
1390 If you don't know what to do here, say Y.
1395 This option enables support for the ARM system coherency unit
1402 This options enables support for the ARM timer and watchdog unit
1405 prompt "Memory split"
1408 Select the desired split between kernel and user memory.
1410 If you are not absolutely sure what you are doing, leave this
1414 bool "3G/1G user/kernel split"
1416 bool "2G/2G user/kernel split"
1418 bool "1G/3G user/kernel split"
1423 default 0x40000000 if VMSPLIT_1G
1424 default 0x80000000 if VMSPLIT_2G
1428 int "Maximum number of CPUs (2-32)"
1434 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1435 depends on SMP && HOTPLUG && EXPERIMENTAL
1437 Say Y here to experiment with turning CPUs off and on. CPUs
1438 can be controlled through /sys/devices/system/cpu.
1441 bool "Use local timer interrupts"
1444 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1446 Enable support for local timers on SMP platforms, rather then the
1447 legacy IPI broadcast method. Local timers allows the system
1448 accounting to be spread across the timer interval, preventing a
1449 "thundering herd" at every timer tick.
1451 source kernel/Kconfig.preempt
1455 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1456 ARCH_S5PV210 || ARCH_EXYNOS4
1457 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1458 default AT91_TIMER_HZ if ARCH_AT91
1459 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1462 config THUMB2_KERNEL
1463 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1464 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1466 select ARM_ASM_UNIFIED
1468 By enabling this option, the kernel will be compiled in
1469 Thumb-2 mode. A compiler/assembler that understand the unified
1470 ARM-Thumb syntax is needed.
1474 config THUMB2_AVOID_R_ARM_THM_JUMP11
1475 bool "Work around buggy Thumb-2 short branch relocations in gas"
1476 depends on THUMB2_KERNEL && MODULES
1479 Various binutils versions can resolve Thumb-2 branches to
1480 locally-defined, preemptible global symbols as short-range "b.n"
1481 branch instructions.
1483 This is a problem, because there's no guarantee the final
1484 destination of the symbol, or any candidate locations for a
1485 trampoline, are within range of the branch. For this reason, the
1486 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1487 relocation in modules at all, and it makes little sense to add
1490 The symptom is that the kernel fails with an "unsupported
1491 relocation" error when loading some modules.
1493 Until fixed tools are available, passing
1494 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1495 code which hits this problem, at the cost of a bit of extra runtime
1496 stack usage in some cases.
1498 The problem is described in more detail at:
1499 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1501 Only Thumb-2 kernels are affected.
1503 Unless you are sure your tools don't have this problem, say Y.
1505 config ARM_ASM_UNIFIED
1509 bool "Use the ARM EABI to compile the kernel"
1511 This option allows for the kernel to be compiled using the latest
1512 ARM ABI (aka EABI). This is only useful if you are using a user
1513 space environment that is also compiled with EABI.
1515 Since there are major incompatibilities between the legacy ABI and
1516 EABI, especially with regard to structure member alignment, this
1517 option also changes the kernel syscall calling convention to
1518 disambiguate both ABIs and allow for backward compatibility support
1519 (selected with CONFIG_OABI_COMPAT).
1521 To use this you need GCC version 4.0.0 or later.
1524 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1525 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1528 This option preserves the old syscall interface along with the
1529 new (ARM EABI) one. It also provides a compatibility layer to
1530 intercept syscalls that have structure arguments which layout
1531 in memory differs between the legacy ABI and the new ARM EABI
1532 (only for non "thumb" binaries). This option adds a tiny
1533 overhead to all syscalls and produces a slightly larger kernel.
1534 If you know you'll be using only pure EABI user space then you
1535 can say N here. If this option is not selected and you attempt
1536 to execute a legacy ABI binary then the result will be
1537 UNPREDICTABLE (in fact it can be predicted that it won't work
1538 at all). If in doubt say Y.
1540 config ARCH_HAS_HOLES_MEMORYMODEL
1543 config ARCH_SPARSEMEM_ENABLE
1546 config ARCH_SPARSEMEM_DEFAULT
1547 def_bool ARCH_SPARSEMEM_ENABLE
1549 config ARCH_SELECT_MEMORY_MODEL
1550 def_bool ARCH_SPARSEMEM_ENABLE
1552 config HAVE_ARCH_PFN_VALID
1553 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1556 bool "High Memory Support"
1559 The address space of ARM processors is only 4 Gigabytes large
1560 and it has to accommodate user address space, kernel address
1561 space as well as some memory mapped IO. That means that, if you
1562 have a large amount of physical memory and/or IO, not all of the
1563 memory can be "permanently mapped" by the kernel. The physical
1564 memory that is not permanently mapped is called "high memory".
1566 Depending on the selected kernel/user memory split, minimum
1567 vmalloc space and actual amount of RAM, you may not need this
1568 option which should result in a slightly faster kernel.
1573 bool "Allocate 2nd-level pagetables from highmem"
1576 config HW_PERF_EVENTS
1577 bool "Enable hardware performance counter support for perf events"
1578 depends on PERF_EVENTS && CPU_HAS_PMU
1581 Enable hardware performance counter support for perf events. If
1582 disabled, perf events will use software events only.
1586 config FORCE_MAX_ZONEORDER
1587 int "Maximum zone order" if ARCH_SHMOBILE
1588 range 11 64 if ARCH_SHMOBILE
1589 default "9" if SA1111
1592 The kernel memory allocator divides physically contiguous memory
1593 blocks into "zones", where each zone is a power of two number of
1594 pages. This option selects the largest power of two that the kernel
1595 keeps in the memory allocator. If you need to allocate very large
1596 blocks of physically contiguous memory, then you may need to
1597 increase this value.
1599 This config option is actually maximum order plus one. For example,
1600 a value of 11 means that the largest free memory block is 2^10 pages.
1603 bool "Timer and CPU usage LEDs"
1604 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1605 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1606 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1607 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1608 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1609 ARCH_AT91 || ARCH_DAVINCI || \
1610 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1612 If you say Y here, the LEDs on your machine will be used
1613 to provide useful information about your current system status.
1615 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1616 be able to select which LEDs are active using the options below. If
1617 you are compiling a kernel for the EBSA-110 or the LART however, the
1618 red LED will simply flash regularly to indicate that the system is
1619 still functional. It is safe to say Y here if you have a CATS
1620 system, but the driver will do nothing.
1623 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1624 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1625 || MACH_OMAP_PERSEUS2
1627 depends on !GENERIC_CLOCKEVENTS
1628 default y if ARCH_EBSA110
1630 If you say Y here, one of the system LEDs (the green one on the
1631 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1632 will flash regularly to indicate that the system is still
1633 operational. This is mainly useful to kernel hackers who are
1634 debugging unstable kernels.
1636 The LART uses the same LED for both Timer LED and CPU usage LED
1637 functions. You may choose to use both, but the Timer LED function
1638 will overrule the CPU usage LED.
1641 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1643 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1644 || MACH_OMAP_PERSEUS2
1647 If you say Y here, the red LED will be used to give a good real
1648 time indication of CPU usage, by lighting whenever the idle task
1649 is not currently executing.
1651 The LART uses the same LED for both Timer LED and CPU usage LED
1652 functions. You may choose to use both, but the Timer LED function
1653 will overrule the CPU usage LED.
1655 config ALIGNMENT_TRAP
1657 depends on CPU_CP15_MMU
1658 default y if !ARCH_EBSA110
1659 select HAVE_PROC_CPU if PROC_FS
1661 ARM processors cannot fetch/store information which is not
1662 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1663 address divisible by 4. On 32-bit ARM processors, these non-aligned
1664 fetch/store instructions will be emulated in software if you say
1665 here, which has a severe performance impact. This is necessary for
1666 correct operation of some network protocols. With an IP-only
1667 configuration it is safe to say N, otherwise say Y.
1669 config UACCESS_WITH_MEMCPY
1670 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1671 depends on MMU && EXPERIMENTAL
1672 default y if CPU_FEROCEON
1674 Implement faster copy_to_user and clear_user methods for CPU
1675 cores where a 8-word STM instruction give significantly higher
1676 memory write throughput than a sequence of individual 32bit stores.
1678 A possible side effect is a slight increase in scheduling latency
1679 between threads sharing the same address space if they invoke
1680 such copy operations with large buffers.
1682 However, if the CPU data cache is using a write-allocate mode,
1683 this option is unlikely to provide any performance gain.
1687 prompt "Enable seccomp to safely compute untrusted bytecode"
1689 This kernel feature is useful for number crunching applications
1690 that may need to compute untrusted bytecode during their
1691 execution. By using pipes or other transports made available to
1692 the process as file descriptors supporting the read/write
1693 syscalls, it's possible to isolate those applications in
1694 their own address space using seccomp. Once seccomp is
1695 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1696 and the task is only allowed to execute a few safe syscalls
1697 defined by each seccomp mode.
1699 config CC_STACKPROTECTOR
1700 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1701 depends on EXPERIMENTAL
1703 This option turns on the -fstack-protector GCC feature. This
1704 feature puts, at the beginning of functions, a canary value on
1705 the stack just before the return address, and validates
1706 the value just before actually returning. Stack based buffer
1707 overflows (that need to overwrite this return address) now also
1708 overwrite the canary, which gets detected and the attack is then
1709 neutralized via a kernel panic.
1710 This feature requires gcc version 4.2 or above.
1712 config DEPRECATED_PARAM_STRUCT
1713 bool "Provide old way to pass kernel parameters"
1715 This was deprecated in 2001 and announced to live on for 5 years.
1716 Some old boot loaders still use this way.
1723 bool "Flattened Device Tree support"
1725 select OF_EARLY_FLATTREE
1728 Include support for flattened device tree machine descriptions.
1730 # Compressed boot loader in ROM. Yes, we really want to ask about
1731 # TEXT and BSS so we preserve their values in the config files.
1732 config ZBOOT_ROM_TEXT
1733 hex "Compressed ROM boot loader base address"
1736 The physical address at which the ROM-able zImage is to be
1737 placed in the target. Platforms which normally make use of
1738 ROM-able zImage formats normally set this to a suitable
1739 value in their defconfig file.
1741 If ZBOOT_ROM is not enabled, this has no effect.
1743 config ZBOOT_ROM_BSS
1744 hex "Compressed ROM boot loader BSS address"
1747 The base address of an area of read/write memory in the target
1748 for the ROM-able zImage which must be available while the
1749 decompressor is running. It must be large enough to hold the
1750 entire decompressed kernel plus an additional 128 KiB.
1751 Platforms which normally make use of ROM-able zImage formats
1752 normally set this to a suitable value in their defconfig file.
1754 If ZBOOT_ROM is not enabled, this has no effect.
1757 bool "Compressed boot loader in ROM/flash"
1758 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1760 Say Y here if you intend to execute your compressed kernel image
1761 (zImage) directly from ROM or flash. If unsure, say N.
1764 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1765 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1766 default ZBOOT_ROM_NONE
1768 Include experimental SD/MMC loading code in the ROM-able zImage.
1769 With this enabled it is possible to write the the ROM-able zImage
1770 kernel image to an MMC or SD card and boot the kernel straight
1771 from the reset vector. At reset the processor Mask ROM will load
1772 the first part of the the ROM-able zImage which in turn loads the
1773 rest the kernel image to RAM.
1775 config ZBOOT_ROM_NONE
1776 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1778 Do not load image from SD or MMC
1780 config ZBOOT_ROM_MMCIF
1781 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1783 Load image from MMCIF hardware block.
1785 config ZBOOT_ROM_SH_MOBILE_SDHI
1786 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1788 Load image from SDHI hardware block
1793 string "Default kernel command string"
1796 On some architectures (EBSA110 and CATS), there is currently no way
1797 for the boot loader to pass arguments to the kernel. For these
1798 architectures, you should supply some command-line options at build
1799 time by entering them here. As a minimum, you should specify the
1800 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1803 prompt "Kernel command line type" if CMDLINE != ""
1804 default CMDLINE_FROM_BOOTLOADER
1806 config CMDLINE_FROM_BOOTLOADER
1807 bool "Use bootloader kernel arguments if available"
1809 Uses the command-line options passed by the boot loader. If
1810 the boot loader doesn't provide any, the default kernel command
1811 string provided in CMDLINE will be used.
1813 config CMDLINE_EXTEND
1814 bool "Extend bootloader kernel arguments"
1816 The command-line arguments provided by the boot loader will be
1817 appended to the default kernel command string.
1819 config CMDLINE_FORCE
1820 bool "Always use the default kernel command string"
1822 Always use the default kernel command string, even if the boot
1823 loader passes other arguments to the kernel.
1824 This is useful if you cannot or don't want to change the
1825 command-line options your boot loader passes to the kernel.
1829 bool "Kernel Execute-In-Place from ROM"
1830 depends on !ZBOOT_ROM
1832 Execute-In-Place allows the kernel to run from non-volatile storage
1833 directly addressable by the CPU, such as NOR flash. This saves RAM
1834 space since the text section of the kernel is not loaded from flash
1835 to RAM. Read-write sections, such as the data section and stack,
1836 are still copied to RAM. The XIP kernel is not compressed since
1837 it has to run directly from flash, so it will take more space to
1838 store it. The flash address used to link the kernel object files,
1839 and for storing it, is configuration dependent. Therefore, if you
1840 say Y here, you must know the proper physical address where to
1841 store the kernel image depending on your own flash memory usage.
1843 Also note that the make target becomes "make xipImage" rather than
1844 "make zImage" or "make Image". The final kernel binary to put in
1845 ROM memory will be arch/arm/boot/xipImage.
1849 config XIP_PHYS_ADDR
1850 hex "XIP Kernel Physical Location"
1851 depends on XIP_KERNEL
1852 default "0x00080000"
1854 This is the physical address in your flash memory the kernel will
1855 be linked for and stored to. This address is dependent on your
1859 bool "Kexec system call (EXPERIMENTAL)"
1860 depends on EXPERIMENTAL
1862 kexec is a system call that implements the ability to shutdown your
1863 current kernel, and to start another kernel. It is like a reboot
1864 but it is independent of the system firmware. And like a reboot
1865 you can start any kernel with it, not just Linux.
1867 It is an ongoing process to be certain the hardware in a machine
1868 is properly shutdown, so do not be surprised if this code does not
1869 initially work for you. It may help to enable device hotplugging
1873 bool "Export atags in procfs"
1877 Should the atags used to boot the kernel be exported in an "atags"
1878 file in procfs. Useful with kexec.
1881 bool "Build kdump crash kernel (EXPERIMENTAL)"
1882 depends on EXPERIMENTAL
1884 Generate crash dump after being started by kexec. This should
1885 be normally only set in special crash dump kernels which are
1886 loaded in the main kernel with kexec-tools into a specially
1887 reserved region and then later executed after a crash by
1888 kdump/kexec. The crash dump kernel must be compiled to a
1889 memory address not used by the main kernel
1891 For more details see Documentation/kdump/kdump.txt
1893 config AUTO_ZRELADDR
1894 bool "Auto calculation of the decompressed kernel image address"
1895 depends on !ZBOOT_ROM && !ARCH_U300
1897 ZRELADDR is the physical address where the decompressed kernel
1898 image will be placed. If AUTO_ZRELADDR is selected, the address
1899 will be determined at run-time by masking the current IP with
1900 0xf8000000. This assumes the zImage being placed in the first 128MB
1901 from start of memory.
1905 menu "CPU Power Management"
1909 source "drivers/cpufreq/Kconfig"
1912 tristate "CPUfreq driver for i.MX CPUs"
1913 depends on ARCH_MXC && CPU_FREQ
1915 This enables the CPUfreq driver for i.MX CPUs.
1917 config CPU_FREQ_SA1100
1920 config CPU_FREQ_SA1110
1923 config CPU_FREQ_INTEGRATOR
1924 tristate "CPUfreq driver for ARM Integrator CPUs"
1925 depends on ARCH_INTEGRATOR && CPU_FREQ
1928 This enables the CPUfreq driver for ARM Integrator CPUs.
1930 For details, take a look at <file:Documentation/cpu-freq>.
1936 depends on CPU_FREQ && ARCH_PXA && PXA25x
1938 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1943 Internal configuration node for common cpufreq on Samsung SoC
1945 config CPU_FREQ_S3C24XX
1946 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
1947 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1950 This enables the CPUfreq driver for the Samsung S3C24XX family
1953 For details, take a look at <file:Documentation/cpu-freq>.
1957 config CPU_FREQ_S3C24XX_PLL
1958 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
1959 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
1961 Compile in support for changing the PLL frequency from the
1962 S3C24XX series CPUfreq driver. The PLL takes time to settle
1963 after a frequency change, so by default it is not enabled.
1965 This also means that the PLL tables for the selected CPU(s) will
1966 be built which may increase the size of the kernel image.
1968 config CPU_FREQ_S3C24XX_DEBUG
1969 bool "Debug CPUfreq Samsung driver core"
1970 depends on CPU_FREQ_S3C24XX
1972 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
1974 config CPU_FREQ_S3C24XX_IODEBUG
1975 bool "Debug CPUfreq Samsung driver IO timing"
1976 depends on CPU_FREQ_S3C24XX
1978 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
1980 config CPU_FREQ_S3C24XX_DEBUGFS
1981 bool "Export debugfs for CPUFreq"
1982 depends on CPU_FREQ_S3C24XX && DEBUG_FS
1984 Export status information via debugfs.
1988 source "drivers/cpuidle/Kconfig"
1992 menu "Floating point emulation"
1994 comment "At least one emulation must be selected"
1997 bool "NWFPE math emulation"
1998 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2000 Say Y to include the NWFPE floating point emulator in the kernel.
2001 This is necessary to run most binaries. Linux does not currently
2002 support floating point hardware so you need to say Y here even if
2003 your machine has an FPA or floating point co-processor podule.
2005 You may say N here if you are going to load the Acorn FPEmulator
2006 early in the bootup.
2009 bool "Support extended precision"
2010 depends on FPE_NWFPE
2012 Say Y to include 80-bit support in the kernel floating-point
2013 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2014 Note that gcc does not generate 80-bit operations by default,
2015 so in most cases this option only enlarges the size of the
2016 floating point emulator without any good reason.
2018 You almost surely want to say N here.
2021 bool "FastFPE math emulation (EXPERIMENTAL)"
2022 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2024 Say Y here to include the FAST floating point emulator in the kernel.
2025 This is an experimental much faster emulator which now also has full
2026 precision for the mantissa. It does not support any exceptions.
2027 It is very simple, and approximately 3-6 times faster than NWFPE.
2029 It should be sufficient for most programs. It may be not suitable
2030 for scientific calculations, but you have to check this for yourself.
2031 If you do not feel you need a faster FP emulation you should better
2035 bool "VFP-format floating point maths"
2036 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2038 Say Y to include VFP support code in the kernel. This is needed
2039 if your hardware includes a VFP unit.
2041 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2042 release notes and additional status information.
2044 Say N if your target does not have VFP hardware.
2052 bool "Advanced SIMD (NEON) Extension support"
2053 depends on VFPv3 && CPU_V7
2055 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2060 menu "Userspace binary formats"
2062 source "fs/Kconfig.binfmt"
2065 tristate "RISC OS personality"
2068 Say Y here to include the kernel code necessary if you want to run
2069 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2070 experimental; if this sounds frightening, say N and sleep in peace.
2071 You can also say M here to compile this support as a module (which
2072 will be called arthur).
2076 menu "Power management options"
2078 source "kernel/power/Kconfig"
2080 config ARCH_SUSPEND_POSSIBLE
2081 depends on !ARCH_S5P64X0 && !ARCH_S5PC100
2082 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2083 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2088 source "net/Kconfig"
2090 source "drivers/Kconfig"
2094 source "arch/arm/Kconfig.debug"
2096 source "security/Kconfig"
2098 source "crypto/Kconfig"
2100 source "lib/Kconfig"